Changeset e7625fc6 in rtems


Ignore:
Timestamp:
Feb 20, 2003, 9:48:25 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Children:
5cfb5ca
Parents:
837a1323
Message:

2003-02-20 Till Straumann <strauman@…>

PR 349/bsps

  • console/polled_io.c, console/reboot.c, irq/irq.c, irq/irq_asm.S, irq/irq_init.c, openpic/Makefile.am, startup/linkcmds, vectors/vectors.S, vectors/vectors_init.c:
    • install the 'openpic.h' and 'pci.h' headers
    • avoid a name clash by renaming 'vsprintf' & friends to 'k_vsprintf' etc.
    • let 'rtemsReboot' print a stack trace (in case an 'assert' failed)
    • irq.c:
      • fix: remove implicit assumption that ISA interrupt vectors start

at 0

  • add BSP hook to let a VME interrupt acknowledge the PCI/openpic IRQ. (SEE ALSO THE ppc-sharedbsp-vme.diff patch)
  • fix: EABI compliance; isr/exception lowlevel handlers must not

clobber R2 or R13

  • fix: openpic_init was called with the polarity/senses tables

swapped (fixed wrong order of arguments)

  • cosmetics: use new _read_SPRXX() _write_SPRXX() macros
Location:
c/src/lib/libbsp/powerpc/shared
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/shared/ChangeLog

    r837a1323 re7625fc6  
     12003-02-20      Till Straumann <strauman@slac.stanford.edu>
     2
     3        PR 349/bsps
     4        * console/polled_io.c, console/reboot.c, irq/irq.c, irq/irq_asm.S,
     5        irq/irq_init.c, openpic/Makefile.am, startup/linkcmds,
     6        vectors/vectors.S, vectors/vectors_init.c:
     7          - install the 'openpic.h' and 'pci.h' headers
     8          - avoid a name clash by renaming 'vsprintf' & friends
     9            to 'k_vsprintf' etc.
     10          - let 'rtemsReboot' print a stack trace (in case an 'assert' failed)
     11          - irq.c:
     12             * fix: remove implicit assumption that ISA interrupt vectors start
     13                    at 0
     14             * add BSP hook to let a VME interrupt acknowledge the PCI/openpic
     15               IRQ. (SEE ALSO THE ppc-sharedbsp-vme.diff patch)
     16          - fix: EABI compliance; isr/exception lowlevel handlers must not
     17                 clobber R2 or R13
     18          - fix: openpic_init was called with the polarity/senses tables
     19                 swapped (fixed wrong order of arguments)
     20          - cosmetics: use new _read_SPRXX() _write_SPRXX() macros
     21
    1222003-02-20      Till Straumann <strauman@slac.stanford.edu>
    223
  • c/src/lib/libbsp/powerpc/shared/Makefile.am

    r837a1323 re7625fc6  
    66if need_shared
    77SUBDIRS = clock console include pci residual openpic irq vectors start \
    8     startup motorola bootloader
     8    startup motorola bootloader vme
    99endif
    1010
  • c/src/lib/libbsp/powerpc/shared/irq/irq.c

    r837a1323 re7625fc6  
    1515#include <bsp.h>
    1616#include <bsp/irq.h>
     17#include <bsp/VME.h>
    1718#include <bsp/openpic.h>
    1819#include <rtems/score/thread.h>
     
    8788static void compute_i8259_masks_from_prio ()
    8889{
    89   unsigned int i;
    90   unsigned int j;
     90  int i;
     91  int j;
    9192  /*
    9293   * Always mask at least current interrupt to prevent re-entrance
    9394   */
    94   for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_NUMBER; i++) {
     95  for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
    9596    * ((unsigned short*) &irq_mask_or_tbl[i]) = (1 << i);
    96     for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_NUMBER; j++) {
     97    for (j = BSP_ISA_IRQ_LOWEST_OFFSET; j < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; j++) {
    9798      /*
    9899       * Mask interrupts at i8259 level that have a lower priority
     
    262263    compute_i8259_masks_from_prio ();
    263264
    264     for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_NUMBER; i++) {
     265    for (i=BSP_ISA_IRQ_LOWEST_OFFSET; i < BSP_ISA_IRQ_LOWEST_OFFSET + BSP_ISA_IRQ_NUMBER; i++) {
    265266      if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    266267        BSP_irq_enable_at_i8259s (i);
     
    376377  }
    377378  else {
    378 #ifdef BSP_PCI_VME_BRIDGE_DOES_EOI
    379         /* leave it to the VME bridge to do EOI, so
    380          * it can re-enable the openpic while handling
    381          * VME interrupts (-> VME priorities in software)
     379#ifdef BSP_PCI_VME_DRIVER_DOES_EOI
     380        /* leave it to the VME bridge driver to do EOI, so
     381     * it can re-enable the openpic while handling
     382     * VME interrupts (-> VME priorities in software)
    382383         */
    383384        if (BSP_PCI_VME_BRIDGE_IRQ!=irq)
  • c/src/lib/libbsp/powerpc/shared/irq/irq_asm.S

    r837a1323 re7625fc6  
    7474         */
    7575        stw     r0, GPR0_OFFSET(r1)
     76        /* PPC EABI: R2 is reserved (pointer to short data .sdata2) - we won't touch it
     77         * but we still save/restore it, just in case...
     78         */
    7679        stw     r2, GPR2_OFFSET(r1)
    7780        stw     r3, GPR3_OFFSET(r1)
    7881       
    7982        mfsrr0  r0
    80         mfsrr1  r2
     83        mfsrr1  r3
     84       
     85        stw     r0, SRR0_FRAME_OFFSET(r1)
     86        stw     r3, SRR1_FRAME_OFFSET(r1)
     87
    8188        mfmsr   r3
    82        
    83         stw     r0, SRR0_FRAME_OFFSET(r1)
    84         stw     r2, SRR1_FRAME_OFFSET(r1)
    8589        /*
    8690         * Enable data and instruction address translation, exception recovery
     
    138142        addis r15,0, _Thread_Dispatch_disable_level@ha
    139143        /*
    140          * Get current nesting level in R2
    141          */
    142         mfspr   r2, SPRG0
     144         * Get current nesting level in R3
     145         */
     146        mfspr   r3, SPRG0
    143147        /*
    144148         * Check if stack switch is necessary
    145149         */
    146         cmpwi   r2,0
     150        cmpwi   r3,0
    147151        bne     nested
    148152        mfspr   r1, SPRG1
     
    150154nested:
    151155        /*
    152          * Start Incrementing nesting level in R2
    153          */
    154         addi    r2,r2,1
     156         * Start Incrementing nesting level in R3
     157         */
     158        addi    r3,r3,1
    155159        /*
    156160         * Start Incrementing _Thread_Dispatch_disable_level R4 = _Thread_Dispatch_disable_level
     
    160164         * store new nesting level in SPRG0
    161165         */
    162         mtspr   SPRG0, r2
     166        mtspr   SPRG0, r3
    163167       
    164168        addi    r6, r6, 1
     
    184188         * then _Thread_Dispatch_disable_level > 1
    185189         */
    186         mfspr   r2, SPRG0
     190        mfspr   r4, SPRG0
    187191        /*
    188192         * start decrementing _Thread_Dispatch_disable_level
    189193         */
    190194        lwz     r3,_Thread_Dispatch_disable_level@l(r15)
    191         addi    r2, r2, -1      /* Continue decrementing nesting level */
     195        addi    r4, r4, -1      /* Continue decrementing nesting level */
    192196        addi    r3, r3, -1      /* Continue decrementing _Thread_Dispatch_disable_level */
    193         mtspr   SPRG0, r2       /* End decrementing nesting level */
     197        mtspr   SPRG0, r4       /* End decrementing nesting level */
    194198        stw     r3,_Thread_Dispatch_disable_level@l(r15) /* End decrementing _Thread_Dispatch_disable_level */
    195199        cmpwi   r3, 0
     
    223227        stmw    r16, GPR16_OFFSET(r1)
    224228        addi    r3, r1, 0x8
    225         /*
    226         * compute SP at exception entry
    227         */
    228         addi    r2, r1, EXCEPTION_FRAME_END
    229         /*
    230         * store it at the right place
    231         */
    232         stw     r2, GPR1_OFFSET(r1)
     229        /*
     230        * compute SP at exception entry
     231        */
     232        addi    r4, r1, EXCEPTION_FRAME_END
     233        /*
     234        * store it at the right place
     235        */
     236        stw     r4, GPR1_OFFSET(r1)
    233237        /*
    234238         * Call High Level signal handling code
     
    315319                 
    316320        lwz     r4, SRR1_FRAME_OFFSET(r1)
    317         lwz     r2, SRR0_FRAME_OFFSET(r1)
     321        lwz     r3, SRR0_FRAME_OFFSET(r1)
     322        lwz     r2, GPR2_OFFSET(r1)
     323        lwz     r0, GPR0_OFFSET(r1)
     324
     325        mtsrr1  r4
     326        mtsrr0  r3
     327        lwz     r4, GPR4_OFFSET(r1)
    318328        lwz     r3, GPR3_OFFSET(r1)
    319         lwz     r0, GPR0_OFFSET(r1)
    320 
    321         mtsrr1  r4
    322         mtsrr0  r2
    323         lwz     r4, GPR4_OFFSET(r1)
    324         lwz     r2, GPR2_OFFSET(r1)
    325329        addi    r1,r1, EXCEPTION_FRAME_END
    326330        SYNC
  • c/src/lib/libbsp/powerpc/shared/irq/irq_init.c

    r837a1323 re7625fc6  
    238238  printk("Going to initialize raven interrupt controller (openpic compliant)\n");
    239239#endif       
    240   openpic_init(1, mcp750_openpic_initsenses, mcp750_openpic_initpolarities);
     240  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
    241241#ifdef TRACE_IRQ_INIT 
    242242  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
  • c/src/lib/libbsp/powerpc/shared/openpic/Makefile.am

    r837a1323 re7625fc6  
    66C_FILES = openpic.c
    77
    8 include_bspdir = $(includedir)/bsp
    9 include_bsp_HEADERS = openpic.h
     8H_FILES = openpic.h
    109
    1110$(PROJECT_INCLUDE)/bsp:
  • c/src/lib/libbsp/powerpc/shared/vectors/vectors.S

    r837a1323 re7625fc6  
    4141        stwu    r1, - (EXCEPTION_FRAME_END)(r1)
    4242        stw     r3, GPR3_OFFSET(r1)
     43        /* R2 should never change (EABI: pointer to .sdata2) - we
     44     * save it nevertheless..
     45         */
    4346        stw     r2, GPR2_OFFSET(r1)
    44         mflr    r2
    45         stw     r2, EXC_LR_OFFSET(r1)
     47        mflr    r3
     48        stw     r3, EXC_LR_OFFSET(r1)
    4649        bl      0f
    47500:      /*
     
    6568        stw     r3, EXCEPTION_NUMBER_OFFSET(r1)
    6669        stw     r0, GPR0_OFFSET(r1)
    67         mfsrr0  r2
    68         stw     r2, SRR0_FRAME_OFFSET(r1)
     70        mfsrr0  r3
     71        stw     r3, SRR0_FRAME_OFFSET(r1)
    6972        mfsrr1  r3
    7073        stw     r3, SRR1_FRAME_OFFSET(r1)
     
    9093        mfdar   r28
    9194        stw     r28,  EXC_DAR_OFFSET(r1)
    92         /*
    93         * compute SP at exception entry
    94         */
    95         addi    r2, r1, EXCEPTION_FRAME_END
    96         /*
    97         * store it at the right place
    98         */
    99         stw     r2, GPR1_OFFSET(r1)
     95        /*
     96        * compute SP at exception entry
     97        */
     98        addi    r3, r1, EXCEPTION_FRAME_END
     99        /*
     100        * store it at the right place
     101        */
     102        stw     r3, GPR1_OFFSET(r1)
    100103        /*
    101104         * Enable data and instruction address translation, exception nesting
  • c/src/lib/libbsp/powerpc/shared/vectors/vectors_init.c

    r837a1323 re7625fc6  
    1717#include <bsp/vectors.h>
    1818#include <libcpu/raw_exception.h>
     19#include <libcpu/spr.h>
    1920#include <bsp.h>
    2021
     
    3435#define STACK_CLAMP 50  /* in case we have a corrupted bottom */
    3536
     37SPR_RO(LR)
     38
    3639void
    3740BSP_printStackTrace(BSP_Exception_frame* excPtr)
    3841{
    39 LRFrame f;
    40 int     i;
     42LRFrame f;
     43int             i;
     44LRFrame sp;
     45void    *lr;
    4146
    42         printk("Stack Trace: ");
    43         printk("  IP: 0x%08x, LR: 0x%08x\n",
    44                         excPtr->EXC_SRR0, excPtr->EXC_LR);
    45         for (f=(LRFrame)excPtr->GPR1, i=0; f->frameLink && i<STACK_CLAMP; f=f->frameLink) {
     47        printk("Stack Trace: \n  ");
     48        if (excPtr) {
     49                printk("IP: 0x%08x, ",excPtr->EXC_SRR0);
     50                sp=(LRFrame)excPtr->GPR1;
     51                lr=(void*)excPtr->EXC_LR;
     52        } else {
     53                /* there's no macro for this */
     54                __asm__ __volatile__("mr %0, 1":"=r"(sp));
     55                lr=(LRFrame)_read_LR();
     56        }
     57        printk("LR: 0x%08x\n",lr);
     58        for (f=(LRFrame)sp, i=0; f->frameLink && i<STACK_CLAMP; f=f->frameLink) {
    4659                printk("--^ 0x%08x", (long)(f->frameLink->lr));
    4760                if (!(++i%5))
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