Changeset e75cef9 in rtems
- Timestamp:
- 03/31/04 11:12:13 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 509fec9c
- Parents:
- e208738
- Location:
- c/src/lib/libcpu/sh
- Files:
-
- 4 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/sh/ChangeLog
re208738 re75cef9 1 2004-03-31 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * sh7032/clock/ckinit.c, sh7750/include/sh/sh4uart.h, 4 sh7750/sci/sh4uart.c: Cosmetics. 5 1 6 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 7 -
c/src/lib/libcpu/sh/sh7032/clock/ckinit.c
re208738 re75cef9 104 104 double fclicks_per_tick = 105 105 ((double) clicks_per_sec * (double) usec_per_tick) / 1000000.0 ; 106 return (uint32_t 106 return (uint32_t) fclicks_per_tick ; 107 107 #endif 108 108 } -
c/src/lib/libcpu/sh/sh7750/include/sh/sh4uart.h
re208738 re75cef9 36 36 * Macros to call UART registers 37 37 */ 38 #define SCRDR(n) (*(volatile uint8_t 38 #define SCRDR(n) (*(volatile uint8_t*)SH7750_SCRDR(n)) 39 39 #define SCRDR1 SCRDR(1) 40 40 #define SCRDR2 SCRDR(2) 41 #define SCTDR(n) (*(volatile uint8_t 41 #define SCTDR(n) (*(volatile uint8_t*)SH7750_SCTDR(n)) 42 42 #define SCTDR1 SCTDR(1) 43 43 #define SCTDR2 SCTDR(2) 44 #define SCSMR(n) ((n) == 1 ? *(volatile uint8_t 45 *(volatile uint16_t 44 #define SCSMR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSMR1 : \ 45 *(volatile uint16_t*)SH7750_SCSMR2) 46 46 #define SCSMR1 SCSMR(1) 47 47 #define SCSMR2 SCSMR(2) 48 #define SCSCR(n) ((n) == 1 ? *(volatile uint8_t 49 *(volatile uint16_t 48 #define SCSCR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSCR1 : \ 49 *(volatile uint16_t*)SH7750_SCSCR2) 50 50 #define SCSCR1 SCSCR(1) 51 51 #define SCSCR2 SCSCR(2) 52 #define SCSSR(n) ((n) == 1 ? *(volatile uint8_t 53 *(volatile uint16_t 52 #define SCSSR(n) ((n) == 1 ? *(volatile uint8_t*)SH7750_SCSSR1 : \ 53 *(volatile uint16_t*)SH7750_SCSSR2) 54 54 #define SCSSR1 SCSSR(1) 55 55 #define SCSSR2 SCSSR(2) 56 #define SCSPTR1 (*(volatile uint8_t 57 #define SCSPTR2 (*(volatile uint16_t 58 #define SCBRR(n) (*(volatile uint8_t 56 #define SCSPTR1 (*(volatile uint8_t*)SH7750_SCSPTR1) 57 #define SCSPTR2 (*(volatile uint16_t*)SH7750_SCSPTR2) 58 #define SCBRR(n) (*(volatile uint8_t*)SH7750_SCBRR(n)) 59 59 #define SCBRR1 SCBRR(1) 60 60 #define SCBRR2 SCBRR(2) 61 #define SCFCR2 (*(volatile uint16_t 62 #define SCFDR2 (*(volatile uint16_t 63 #define SCLSR2 (*(volatile uint16_t 61 #define SCFCR2 (*(volatile uint16_t*)SH7750_SCFCR2) 62 #define SCFDR2 (*(volatile uint16_t*)SH7750_SCFDR2) 63 #define SCLSR2 (*(volatile uint16_t*)SH7750_SCLSR2) 64 64 65 #define IPRB (*(volatile uint16_t 66 #define IPRC (*(volatile uint16_t 65 #define IPRB (*(volatile uint16_t*)SH7750_IPRB) 66 #define IPRC (*(volatile uint16_t*)SH7750_IPRC) 67 67 68 68 /* -
c/src/lib/libcpu/sh/sh7750/sci/sh4uart.c
re208738 re75cef9 84 84 sh4uart_get_Pph(void) 85 85 { 86 uint16_t frqcr = *(volatile uint16_t 86 uint16_t frqcr = *(volatile uint16_t*)SH7750_FRQCR; 87 87 uint32_t Pph = CPU_CLOCK_RATE_HZ; 88 88 … … 361 361 uint16_t smr; 362 362 363 smr = (uint16_t )(*(uint8_t*)SH7750_SCSMR(uart->chn));363 smr = (uint16_t)(*(uint8_t*)SH7750_SCSMR(uart->chn)); 364 364 365 365 baud = cfgetospeed(t); … … 404 404 405 405 sh4uart_set_baudrate(uart, baud); 406 SCSMR(uart->chn) = (uint8_t 406 SCSMR(uart->chn) = (uint8_t)smr; 407 407 408 408 /* enable operations */
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