Changeset e755782 in rtems


Ignore:
Timestamp:
Jul 3, 2018, 7:54:47 AM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
d3dff40
Parents:
77fbbd6
git-author:
Sebastian Huber <sebastian.huber@…> (07/03/18 07:54:47)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/05/18 05:12:24)
Message:

riscv: Clear reservations

See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store?-Conditional Instructions".

Update #3433.

Location:
cpukit/score/cpu/riscv
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/include/rtems/asm.h

    r77fbbd6 re755782  
    172172.endm
    173173
     174.macro CLEAR_RESERVATIONS REG
     175#ifdef __riscv_atomic
     176        /*
     177         * Clear reservations, see also RISC-V User-Level ISA V2.3, comment in
     178         * section 8.2 "Load-Reserved/Store-Conditional Instructions".
     179         */
     180        sc.w    zero, zero, (\REG)
    174181#endif
     182.endm
     183
     184#endif
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    r77fbbd6 re755782  
    6464#define CPU_LITTLE_ENDIAN                        TRUE
    6565#define CPU_MODES_INTERRUPT_MASK   0x0000000000000001
    66 
    67 #define CPU_PER_CPU_CONTROL_SIZE 0
    6866
    6967#define CPU_CACHE_LINE_BYTES 64
     
    225223#define CPU_MAXIMUM_PROCESSORS 32
    226224
    227 typedef struct {
    228   /* There is no CPU specific per-CPU state */
    229 } CPU_Per_CPU_control;
    230 
    231225typedef uint16_t Priority_bit_map_Word;
    232226
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    r77fbbd6 re755782  
    3535#include <rtems/score/cpu.h>
    3636
     37#ifdef __riscv_atomic
     38#define CPU_PER_CPU_CONTROL_SIZE 16
     39#else
    3740#define CPU_PER_CPU_CONTROL_SIZE 0
     41#endif
    3842
    3943#ifdef RTEMS_SMP
     
    287291} RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame;
    288292
     293#ifdef __riscv_atomic
     294typedef struct {
     295  uint64_t clear_reservations;
     296  uint32_t reserved_for_alignment_of_interrupt_frame[ 2 ];
     297} CPU_Per_CPU_control;
     298#endif
     299
    289300static inline uint32_t _RISCV_Read_FCSR( void )
    290301{
  • cpukit/score/cpu/riscv/riscv-context-switch.S

    r77fbbd6 re755782  
    137137        sw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
    138138
     139        CLEAR_RESERVATIONS      a2
     140
    139141        ret
    140142
  • cpukit/score/cpu/riscv/riscv-exception-handler.S

    r77fbbd6 re755782  
    115115        sw      t2, PER_CPU_ISR_NEST_LEVEL(s0)
    116116        sw      t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
     117
     118        CLEAR_RESERVATIONS      s0
    117119
    118120        /* Keep sp (Exception frame address) in s1 */
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