Changeset e755782 in rtems

Timestamp:

07/03/18 07:54:47 (5 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

5, master

Children:

d3dff40

Parents:

77fbbd6

git-author:

Sebastian Huber <sebastian.huber@…> (07/03/18 07:54:47)

git-committer:

Sebastian Huber <sebastian.huber@…> (07/05/18 05:12:24)

Message:

riscv: Clear reservations

See also RISC-V User-Level ISA V2.3, comment in section 8.2
"Load-Reserved/Store?-Conditional Instructions".

Update #3433.

Location:

cpukit/score/cpu/riscv

Files:

• include/rtems/asm.h (modified) (1 diff)
• include/rtems/score/cpu.h (modified) (2 diffs)
• include/rtems/score/cpuimpl.h (modified) (2 diffs)
• riscv-context-switch.S (modified) (1 diff)
• riscv-exception-handler.S (modified) (1 diff)

cpukit/score/cpu/riscv/include/rtems/asm.h

@@ -172 +172 @@
 .endm
 
+.macro CLEAR_RESERVATIONS REG
+#ifdef __riscv_atomic
+        /*
+         * Clear reservations, see also RISC-V User-Level ISA V2.3, comment in
+         * section 8.2 "Load-Reserved/Store-Conditional Instructions".
+         */
+        sc.w    zero, zero, (\REG)
 #endif
+.endm
+
+#endif

cpukit/score/cpu/riscv/include/rtems/score/cpu.h

@@ -64 +64 @@
 #define CPU_LITTLE_ENDIAN                        TRUE
 #define CPU_MODES_INTERRUPT_MASK   0x0000000000000001
-
-#define CPU_PER_CPU_CONTROL_SIZE 0
 
 #define CPU_CACHE_LINE_BYTES 64
@@ -225 +223 @@
 #define CPU_MAXIMUM_PROCESSORS 32
 
-typedef struct {
-  /* There is no CPU specific per-CPU state */
-} CPU_Per_CPU_control;
-
 typedef uint16_t Priority_bit_map_Word;
 

cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

@@ -35 +35 @@
 #include <rtems/score/cpu.h>
 
+#ifdef __riscv_atomic
+#define CPU_PER_CPU_CONTROL_SIZE 16
+#else
 #define CPU_PER_CPU_CONTROL_SIZE 0
+#endif
 
 #ifdef RTEMS_SMP
@@ -287 +291 @@
 } RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame;
 
+#ifdef __riscv_atomic
+typedef struct {
+  uint64_t clear_reservations;
+  uint32_t reserved_for_alignment_of_interrupt_frame[ 2 ];
+} CPU_Per_CPU_control;
+#endif
+
 static inline uint32_t _RISCV_Read_FCSR( void )
 {

cpukit/score/cpu/riscv/riscv-context-switch.S

@@ -137 +137 @@
         sw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
 
+        CLEAR_RESERVATIONS      a2
+
         ret
 

cpukit/score/cpu/riscv/riscv-exception-handler.S

@@ -115 +115 @@
         sw      t2, PER_CPU_ISR_NEST_LEVEL(s0)
         sw      t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
+
+        CLEAR_RESERVATIONS      s0
 
         /* Keep sp (Exception frame address) in s1 */