Changeset e69307b7 in rtems

Timestamp:

Apr 12, 2004, 10:10:27 PM (16 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Branches:

4.10, 4.11, 4.8, 4.9, master

Children:

b6bf7d53

Parents:

8430205

Message:

2004-04-12 David Querbach <querbach@…>

• asm.h, rtems/new-exceptions/cpu.h, rtems/score/ppc.h: addition of MPC555 support as part of the addition of the SS555 BSP.

Location:

cpukit/score/cpu/powerpc

Files:

• ChangeLog (modified) (1 diff)
• asm.h (modified) (1 diff)
• rtems/asm.h (modified) (1 diff)
• rtems/new-exceptions/cpu.h (modified) (1 diff)
• rtems/score/ppc.h (modified) (2 diffs)

cpukit/score/cpu/powerpc/ChangeLog

@@ +1 @@
+2004-04-12      David Querbach <querbach@realtime.bc.ca>
+
+        * asm.h, rtems/new-exceptions/cpu.h, rtems/score/ppc.h: addition of
+        MPC555 support as part of the addition of the SS555 BSP.
+
 2004-04-06      Ralf Corsepius <ralf_corsepius@rtems.org>
 

cpukit/score/cpu/powerpc/asm.h

@@ -204 +204 @@
 /* end of IBM400 series register definitions */
 
+#elif defined(mpc555)
+/* The following registers are for the MPC5xx */
+#define eie     0x050   /* External Interrupt Enable Register */
+#define eid     0x051   /* External Interrupt Disable Register */
+#define nri     0x052   /* Non-Recoverable Interrupt Register */ 
+  
 #elif defined(mpc860) || defined(mpc821)
 /* The following registers are for the MPC8x0 */

cpukit/score/cpu/powerpc/rtems/asm.h

@@ -204 +204 @@
 /* end of IBM400 series register definitions */
 
+#elif defined(mpc555)
+/* The following registers are for the MPC5xx */
+#define eie     0x050   /* External Interrupt Enable Register */
+#define eid     0x051   /* External Interrupt Disable Register */
+#define nri     0x052   /* Non-Recoverable Interrupt Register */ 
+  
 #elif defined(mpc860) || defined(mpc821)
 /* The following registers are for the MPC8x0 */

cpukit/score/cpu/powerpc/rtems/new-exceptions/cpu.h

@@ -415 +415 @@
 #endif
 
-#if (defined(mpc860) || defined(mpc821) || defined(mpc8260))
+#if (defined(mpc555) || defined(mpc860) || defined(mpc821) || defined(mpc8260))
   uint32_t     clock_speed;            /* Speed of CPU in Hz */
 #endif

cpukit/score/cpu/powerpc/rtems/score/ppc.h

@@ -123 +123 @@
 #define PPC_ALIGNMENT           4
 #define PPC_CACHE_ALIGNMENT     16
+
+/* Added by querbach@realtime.bc.ca */
+#define PPC_LOW_POWER_MODE      PPC_LOW_POWER_MODE_STANDARD
 
 /* Based on comments by Sergei Organov <osv@Javad.RU> */
@@ -496 +499 @@
 #define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+ 4)
 #define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+ 5)
+
+#elif defined(mpc555)
+#define PPC_IRQ_SOFTEMU   (PPC_STD_IRQ_LAST+1)  /* Software emulation. */
+#define PPC_IRQ_INST_PE   (PPC_STD_IRQ_LAST+2)  /* Insn protection error */
+#define PPC_IRQ_DATA_PE   (PPC_STD_IRQ_LAST+3)  /* Data protection error */
+#define PPC_IRQ_DATA_BP   (PPC_STD_IRQ_LAST+4)  /* Data breakpoint */
+#define PPC_IRQ_INST_BP   (PPC_STD_IRQ_LAST+5)  /* Insn breakpoint */
+#define PPC_IRQ_MEXT_BP   (PPC_STD_IRQ_LAST+6)  /* Maskable ext bkpt */
+#define PPC_IRQ_NMEXT_BP  (PPC_STD_IRQ_LAST+7)  /* Non-maskable ext bkpt */
+#define PPC_IRQ_LAST      PPC_IRQ_NMEXT_BP
 
 #elif defined(ppc601)