Changeset e58ecb84 in rtems for bsps/arm/shared/irq/irq-gic.c


Ignore:
Timestamp:
Feb 21, 2020, 1:21:33 PM (3 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
f6fcfea1
Parents:
486829b2
git-author:
Sebastian Huber <sebastian.huber@…> (02/21/20 13:21:33)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/24/20 08:21:47)
Message:

bsps/arm: Initialize priorities of PPIs

At least on GICv1 the interrupts 0 up to including 31 are so called
Peripheral Private Interrupts (PPIs). We have to initialize the
priority of the PPIs on secondary processors.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/shared/irq/irq-gic.c

    r486829b2 re58ecb84  
    153153  volatile gic_cpuif *cpuif = GIC_CPUIF;
    154154  volatile gic_dist *dist = ARM_GIC_DIST;
     155  uint32_t id;
    155156
    156157  while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) {
     
    161162  dist->icdigr[0] = 0xffffffff;
    162163#endif
     164
     165  /* Initialize Peripheral Private Interrupts (PPIs) */
     166  for (id = 0; id < 32; ++id) {
     167    gic_id_set_priority(dist, id, PRIORITY_DEFAULT);
     168  }
    163169
    164170  cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
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