Changeset e57b0e2 in rtems for c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
- Timestamp:
- 12/05/95 19:23:05 (27 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- e88d2db
- Parents:
- 289ad86
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/powerpc/ppc403/clock/clock.c
r289ad86 re57b0e2 4 4 * PowerPC 403 CPU. The tick frequency is specified by the bsp. 5 5 * 6 * Author: Andrew Bray <andy@i-cubed.demon.co.uk>6 * Author: Andrew Bray <andy@i-cubed.co.uk> 7 7 * 8 8 * COPYRIGHT (c) 1995 by i-cubed ltd. … … 57 57 register rtems_unsigned32 rc; 58 58 59 asm volatile ("mf tblo %0" : "=r" ((rc)));59 asm volatile ("mfspr %0, 0x3dd" : "=r" ((rc))); /* TBLO */ 60 60 61 61 return rc; … … 70 70 { 71 71 if (!auto_restart) 72 { 73 rtems_unsigned32 clicks_til_next_interrupt; 74 rtems_unsigned32 itimer_value; 75 76 /* 77 * setup for next interrupt; making sure the new value is reasonably 78 * in the future.... in case we lost out on an interrupt somehow 79 */ 80 81 itimer_value = get_itimer(); 82 tick_time += pit_value; 83 84 /* 85 * how far away is next interrupt *really* 86 * It may be a long time; this subtraction works even if 87 * Clock_clicks_interrupt < Clock_clicks_low_order via 88 * the miracle of unsigned math. 89 */ 90 clicks_til_next_interrupt = tick_time - itimer_value; 91 92 /* 93 * If it is too soon then bump it up. 94 * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small. 95 * But setting it low is useful for debug, so... 96 */ 97 98 if (clicks_til_next_interrupt < 400) 99 { 100 tick_time = itimer_value + 1000; 101 clicks_til_next_interrupt = 1000; 102 /* XXX: count these! this should be rare */ 103 } 104 105 /* 106 * If it is too late, that means we missed the interrupt somehow. 107 * Rather than wait 35-50s for a wrap, we just fudge it here. 108 */ 109 110 if (clicks_til_next_interrupt > pit_value) 111 { 112 tick_time = itimer_value + 1000; 113 clicks_til_next_interrupt = 1000; 114 /* XXX: count these! this should never happen :-) */ 115 } 116 117 asm volatile ("mtpit %0" :: "r" (clicks_til_next_interrupt)); 118 } 119 120 asm volatile ( "mttsr %0" :: "r" (0x08000000)); 121 72 { 73 rtems_unsigned32 clicks_til_next_interrupt; 74 rtems_unsigned32 itimer_value; 75 76 /* 77 * setup for next interrupt; making sure the new value is reasonably 78 * in the future.... in case we lost out on an interrupt somehow 79 */ 80 81 itimer_value = get_itimer(); 82 tick_time += pit_value; 83 84 /* 85 * how far away is next interrupt *really* 86 * It may be a long time; this subtraction works even if 87 * Clock_clicks_interrupt < Clock_clicks_low_order via 88 * the miracle of unsigned math. 89 */ 90 clicks_til_next_interrupt = tick_time - itimer_value; 91 92 /* 93 * If it is too soon then bump it up. 94 * This should only happen if CPU_HPPA_CLICKS_PER_TICK is too small. 95 * But setting it low is useful for debug, so... 96 */ 97 98 if (clicks_til_next_interrupt < 400) 99 { 100 tick_time = itimer_value + 1000; 101 clicks_til_next_interrupt = 1000; 102 /* XXX: count these! this should be rare */ 103 } 104 105 /* 106 * If it is too late, that means we missed the interrupt somehow. 107 * Rather than wait 35-50s for a wrap, we just fudge it here. 108 */ 109 110 if (clicks_til_next_interrupt > pit_value) 111 { 112 tick_time = itimer_value + 1000; 113 clicks_til_next_interrupt = 1000; 114 /* XXX: count these! this should never happen :-) */ 115 } 116 117 asm volatile ("mtspr 0x3db, %0" :: "r" 118 (clicks_til_next_interrupt)); /* PIT */ 119 } 120 121 asm volatile ( "mtspr 0x3d8, %0" :: "r" (0x08000000)); /* TSR */ 122 122 123 Clock_driver_ticks++; 123 124 124 125 rtems_clock_tick(); 125 126 } … … 129 130 rtems_isr_entry previous_isr; 130 131 rtems_unsigned32 pvr, iocr; 131 132 132 133 Clock_driver_ticks = 0; 133 134 asm volatile ("mf iocr %0" : "=r" (iocr));134 135 asm volatile ("mfdcr %0, 0xa0" : "=r" (iocr)); /* IOCR */ 135 136 iocr &= ~4; 136 137 iocr |= 4; /* Select external timer clock */ 137 asm volatile ("mt iocr %0" : "=r" (iocr) : "0" (iocr));138 139 asm volatile ("mf pvr %0" : "=r" ((pvr)));140 138 asm volatile ("mtdcr 0xa0, %0" : "=r" (iocr) : "0" (iocr)); /* IOCR */ 139 140 asm volatile ("mfspr %0, 0x11f" : "=r" ((pvr))); /* PVR */ 141 141 142 if (((pvr & 0xffff0000) >> 16) != 0x0020) 142 143 143 return; /* Not a ppc403 */ 144 144 145 if ((pvr & 0xff00) == 0x0000) /* 403GA */ 145 146 auto_restart = (pvr & 0x00f0) > 0x0000 ? 1 : 0; 146 147 else if ((pvr & 0xff00) == 0x0100) /* 403GB */ 147 148 148 auto_restart = 1; 149 149 150 pit_value = BSP_Configuration.microseconds_per_tick * 150 151 151 Cpu_table.clicks_per_usec; 152 152 153 if (BSP_Configuration.ticks_per_timeslice) 153 154 { 154 register rtems_unsigned32 tcr; 155 register rtems_unsigned32 tcr; 156 155 157 /* 156 158 * initialize the interval here … … 160 162 * interrupt overhead 161 163 */ 162 163 rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, 164 &previous_isr); 165 166 asm volatile ("mtpit %0" : : "r" (pit_value)); 167 168 asm volatile ("mftcr %0" : "=r" ((tcr))); 169 170 tcr &= ~ 0x04400000; 171 172 tcr |= (auto_restart ? 0x04400000 : 0x04000000); 173 174 tick_time = get_itimer() + pit_value; 175 176 asm volatile ("mttcr %0" : "=r" ((tcr)) : "0" ((tcr))); 164 165 rtems_interrupt_catch(clock_isr, PPC_IRQ_PIT, &previous_isr); 166 167 asm volatile ("mtspr 0x3db, %0" : : "r" (pit_value)); /* PIT */ 168 169 asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ 170 171 tcr &= ~ 0x04400000; 172 173 tcr |= (auto_restart ? 0x04400000 : 0x04000000); 174 175 tick_time = get_itimer() + pit_value; 176 177 asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ 177 178 } 178 179 atexit(Clock_exit); … … 187 188 rtems_interrupt_disable(isrlevel); 188 189 189 rtems_interrupt_catch(new_clock_isr, PPC_IRQ_PIT, 190 &previous_isr); 190 rtems_interrupt_catch(new_clock_isr, PPC_IRQ_PIT, &previous_isr); 191 191 192 192 rtems_interrupt_enable(isrlevel); … … 204 204 if ( BSP_Configuration.ticks_per_timeslice ) 205 205 { 206 register rtems_unsigned32 tcr; 207 208 asm volatile ("mftcr %0" : "=r" ((tcr))); 209 210 tcr &= ~ 0x04400000; 211 212 asm volatile ("mttcr %0" : "=r" ((tcr)) : "0" ((tcr))); 213 214 (void) set_vector(0, PPC_IRQ_PIT, 1); 215 } 206 register rtems_unsigned32 tcr; 207 208 asm volatile ("mfspr %0, 0x3da" : "=r" ((tcr))); /* TCR */ 209 210 tcr &= ~ 0x04400000; 211 212 asm volatile ("mtspr 0x3da, %0" : "=r" ((tcr)) : "0" ((tcr))); /* TCR */ 213 214 (void) set_vector(0, PPC_IRQ_PIT, 1); 215 } 216 216 217 } 217 218
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