Changeset e492e7f8 in rtems
- Timestamp:
- 11/19/14 13:37:11 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 5f4f828
- Parents:
- 52d24b00
- git-author:
- Sebastian Huber <sebastian.huber@…> (11/19/14 13:37:11)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:28)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
r52d24b00 re492e7f8 716 716 } 717 717 718 static bool l2c_310_errata_is_applicable_588369( 719 uint32_t rtl_release 720 ) 721 { 722 bool is_applicable = false; 723 724 switch ( rtl_release ) { 725 case L2C_310_RTL_RELEASE_R3_P3: 726 case L2C_310_RTL_RELEASE_R3_P2: 727 case L2C_310_RTL_RELEASE_R3_P1: 728 case L2C_310_RTL_RELEASE_R3_P0: 729 case L2C_310_RTL_RELEASE_R2_P0: 730 is_applicable = false; 731 break; 732 case L2C_310_RTL_RELEASE_R1_P0: 733 case L2C_310_RTL_RELEASE_R0_P0: 734 is_applicable = true; 735 break; 736 default: 737 assert( 0 ); 738 break; 739 } 740 741 return is_applicable; 742 } 718 #if BSP_ARM_L2C_310_RTL_RELEASE == L2C_310_RTL_RELEASE_R0_P0 \ 719 || BSP_ARM_L2C_310_RTL_RELEASE == L2C_310_RTL_RELEASE_R1_P0 720 #define L2C_310_ERRATA_IS_APPLICABLE_588369 721 #endif 743 722 744 723 #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS … … 875 854 876 855 static inline void 877 l2c_310_flush_1_line( 878 const void *d_addr, 879 const bool is_errata_588369applicable 880 ) 881 { 882 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 883 884 if( is_errata_588369applicable ) { 885 /* 886 * Errata 588369 says that clean + inv may keep the 887 * cache line if it was clean, the recommended 888 * workaround is to clean then invalidate the cache 889 * line, with write-back and cache linefill disabled. 890 */ 891 l2cc->clean_pa = (uint32_t) d_addr; 892 l2c_310_sync( l2cc ); 893 l2cc->inv_pa = (uint32_t) d_addr; 894 } else { 895 l2cc->clean_inv_pa = (uint32_t) d_addr; 896 } 856 l2c_310_flush_1_line( volatile L2CC *l2cc, uint32_t d_addr ) 857 { 858 #ifdef L2C_310_ERRATA_IS_APPLICABLE_588369 859 /* 860 * Errata 588369 says that clean + inv may keep the 861 * cache line if it was clean, the recommended 862 * workaround is to clean then invalidate the cache 863 * line, with write-back and cache linefill disabled. 864 */ 865 l2cc->clean_pa = d_addr; 866 l2c_310_sync( l2cc ); 867 l2cc->inv_pa = d_addr; 868 #else 869 l2cc->clean_inv_pa = d_addr; 870 #endif 897 871 } 898 872 … … 909 883 L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); 910 884 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 911 uint32_t rtl_release =912 l2cc->cache_id & L2C_310_ID_RTL_MASK;913 bool is_errata_588369_applicable =914 l2c_310_errata_is_applicable_588369( rtl_release );915 885 916 886 rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); … … 921 891 block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { 922 892 for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) { 923 l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable);893 l2c_310_flush_1_line( l2cc, adx ); 924 894 } 925 895 if( block_end < ADDR_LAST ) {
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