Ignore:
Timestamp:
Jun 27, 2018, 8:05:50 AM (2 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
afb60eb
Parents:
a8188730
git-author:
Sebastian Huber <sebastian.huber@…> (06/27/18 08:05:50)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:37)
Message:

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/riscv-context-switch.S

    ra8188730 re43994d  
    4646        lw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
    4747
    48         SREG    x1, (1 * CPU_SIZEOF_POINTER)(a0)
    49         SREG    x2, (2 * CPU_SIZEOF_POINTER)(a0)
    50         SREG    x4, (4 * CPU_SIZEOF_POINTER)(a0)
    51         SREG    x5, (5 * CPU_SIZEOF_POINTER)(a0)
    52         SREG    x6, (6 * CPU_SIZEOF_POINTER)(a0)
    53         SREG    x7, (7 * CPU_SIZEOF_POINTER)(a0)
    54         SREG    x8, (8 * CPU_SIZEOF_POINTER)(a0)
    55         SREG    x9, (9 * CPU_SIZEOF_POINTER)(a0)
    56         SREG    x10, (10 * CPU_SIZEOF_POINTER)(a0)
    57         SREG    x11, (11 * CPU_SIZEOF_POINTER)(a0)
    58         SREG    x12, (12 * CPU_SIZEOF_POINTER)(a0)
    59         SREG    x13, (13 * CPU_SIZEOF_POINTER)(a0)
    60         SREG    x14, (14 * CPU_SIZEOF_POINTER)(a0)
    61         SREG    x15, (15 * CPU_SIZEOF_POINTER)(a0)
    62         SREG    x16, (16 * CPU_SIZEOF_POINTER)(a0)
    63         SREG    x17, (17 * CPU_SIZEOF_POINTER)(a0)
    64         SREG    x18, (18 * CPU_SIZEOF_POINTER)(a0)
    65         SREG    x19, (19 * CPU_SIZEOF_POINTER)(a0)
    66         SREG    x20, (20 * CPU_SIZEOF_POINTER)(a0)
    67         SREG    x21, (21 * CPU_SIZEOF_POINTER)(a0)
    68         SREG    x22, (22 * CPU_SIZEOF_POINTER)(a0)
    69         SREG    x23, (23 * CPU_SIZEOF_POINTER)(a0)
    70         SREG    x24, (24 * CPU_SIZEOF_POINTER)(a0)
    71         SREG    x25, (25 * CPU_SIZEOF_POINTER)(a0)
    72         SREG    x26, (26 * CPU_SIZEOF_POINTER)(a0)
    73         SREG    x27, (27 * CPU_SIZEOF_POINTER)(a0)
    74         SREG    x28, (28 * CPU_SIZEOF_POINTER)(a0)
    75         SREG    x29, (28 * CPU_SIZEOF_POINTER)(a0)
    76         SREG    x30, (30 * CPU_SIZEOF_POINTER)(a0)
    77         SREG    x31, (31 * CPU_SIZEOF_POINTER)(a0)
     48        SREG    ra, RISCV_CONTEXT_RA(a0)
     49        SREG    sp, RISCV_CONTEXT_SP(a0)
     50        SREG    s0, RISCV_CONTEXT_S0(a0)
     51        SREG    s1, RISCV_CONTEXT_S1(a0)
     52        SREG    s2, RISCV_CONTEXT_S2(a0)
     53        SREG    s3, RISCV_CONTEXT_S3(a0)
     54        SREG    s4, RISCV_CONTEXT_S4(a0)
     55        SREG    s5, RISCV_CONTEXT_S5(a0)
     56        SREG    s6, RISCV_CONTEXT_S6(a0)
     57        SREG    s7, RISCV_CONTEXT_S7(a0)
     58        SREG    s8, RISCV_CONTEXT_S8(a0)
     59        SREG    s9, RISCV_CONTEXT_S9(a0)
     60        SREG    s10, RISCV_CONTEXT_S10(a0)
     61        SREG    s11, RISCV_CONTEXT_S11(a0)
    7862
    7963        sw      a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a0)
     
    8266        lw      a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a1)
    8367
     68        LREG    ra, RISCV_CONTEXT_RA(a1)
     69        LREG    sp, RISCV_CONTEXT_SP(a1)
     70        LREG    s0, RISCV_CONTEXT_S0(a1)
     71        LREG    s1, RISCV_CONTEXT_S1(a1)
     72        LREG    s2, RISCV_CONTEXT_S2(a1)
     73        LREG    s3, RISCV_CONTEXT_S3(a1)
     74        LREG    s4, RISCV_CONTEXT_S4(a1)
     75        LREG    s5, RISCV_CONTEXT_S5(a1)
     76        LREG    s6, RISCV_CONTEXT_S6(a1)
     77        LREG    s7, RISCV_CONTEXT_S7(a1)
     78        LREG    s8, RISCV_CONTEXT_S8(a1)
     79        LREG    s9, RISCV_CONTEXT_S9(a1)
     80        LREG    s10, RISCV_CONTEXT_S10(a1)
     81        LREG    s11, RISCV_CONTEXT_S11(a1)
     82
    8483        sw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
    85 
    86         LREG    x1, (1 * CPU_SIZEOF_POINTER)(a1)
    87         LREG    x2, (2 * CPU_SIZEOF_POINTER)(a1)
    88         LREG    x4, (4 * CPU_SIZEOF_POINTER)(a1)
    89         LREG    x5, (5 * CPU_SIZEOF_POINTER)(a1)
    90         LREG    x6, (6 * CPU_SIZEOF_POINTER)(a1)
    91         LREG    x7, (7 * CPU_SIZEOF_POINTER)(a1)
    92         LREG    x8, (8 * CPU_SIZEOF_POINTER)(a1)
    93         LREG    x9, (9 * CPU_SIZEOF_POINTER)(a1)
    94         LREG    x10, (10 * CPU_SIZEOF_POINTER)(a1)
    95         /* Skip a1/x11 */
    96         LREG    x12, (12 * CPU_SIZEOF_POINTER)(a1)
    97         LREG    x13, (13 * CPU_SIZEOF_POINTER)(a1)
    98         LREG    x14, (14 * CPU_SIZEOF_POINTER)(a1)
    99         LREG    x15, (15 * CPU_SIZEOF_POINTER)(a1)
    100         LREG    x16, (16 * CPU_SIZEOF_POINTER)(a1)
    101         LREG    x17, (17 * CPU_SIZEOF_POINTER)(a1)
    102         LREG    x18, (18 * CPU_SIZEOF_POINTER)(a1)
    103         LREG    x19, (19 * CPU_SIZEOF_POINTER)(a1)
    104         LREG    x20, (20 * CPU_SIZEOF_POINTER)(a1)
    105         LREG    x21, (21 * CPU_SIZEOF_POINTER)(a1)
    106         LREG    x22, (22 * CPU_SIZEOF_POINTER)(a1)
    107         LREG    x23, (23 * CPU_SIZEOF_POINTER)(a1)
    108         LREG    x24, (24 * CPU_SIZEOF_POINTER)(a1)
    109         LREG    x25, (25 * CPU_SIZEOF_POINTER)(a1)
    110         LREG    x26, (26 * CPU_SIZEOF_POINTER)(a1)
    111         LREG    x27, (27 * CPU_SIZEOF_POINTER)(a1)
    112         LREG    x28, (28 * CPU_SIZEOF_POINTER)(a1)
    113         LREG    x29, (29 * CPU_SIZEOF_POINTER)(a1)
    114         LREG    x30, (30 * CPU_SIZEOF_POINTER)(a1)
    115 
    116         LREG    x11, (11 * CPU_SIZEOF_POINTER)(a1)
    11784
    11885        ret
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