Ignore:
Timestamp:
Jun 27, 2018, 8:05:50 AM (2 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
afb60eb
Parents:
a8188730
git-author:
Sebastian Huber <sebastian.huber@…> (06/27/18 08:05:50)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:37)
Message:

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    ra8188730 re43994d  
    3737#define CPU_PER_CPU_CONTROL_SIZE 0
    3838
     39#ifdef RTEMS_SMP
     40#define RISCV_CONTEXT_IS_EXECUTING 0
     41#endif
     42
     43#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 4
     44
    3945#if __riscv_xlen == 32
    4046
    41 #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 128
     47#define RISCV_CONTEXT_RA 8
     48#define RISCV_CONTEXT_SP 12
     49#define RISCV_CONTEXT_TP 16
     50#define RISCV_CONTEXT_S0 20
     51#define RISCV_CONTEXT_S1 24
     52#define RISCV_CONTEXT_S2 28
     53#define RISCV_CONTEXT_S3 32
     54#define RISCV_CONTEXT_S4 36
     55#define RISCV_CONTEXT_S5 40
     56#define RISCV_CONTEXT_S6 44
     57#define RISCV_CONTEXT_S7 48
     58#define RISCV_CONTEXT_S8 52
     59#define RISCV_CONTEXT_S9 56
     60#define RISCV_CONTEXT_S10 60
     61#define RISCV_CONTEXT_S11 64
    4262
    43 #define CPU_INTERRUPT_FRAME_SIZE 140
     63#define RISCV_INTERRUPT_FRAME_MSTATUS 0
     64#define RISCV_INTERRUPT_FRAME_MEPC 4
     65#define RISCV_INTERRUPT_FRAME_A2 8
     66#define RISCV_INTERRUPT_FRAME_S0 12
     67#define RISCV_INTERRUPT_FRAME_S1 16
     68#define RISCV_INTERRUPT_FRAME_RA 20
     69#define RISCV_INTERRUPT_FRAME_A3 24
     70#define RISCV_INTERRUPT_FRAME_A4 28
     71#define RISCV_INTERRUPT_FRAME_A5 32
     72#define RISCV_INTERRUPT_FRAME_A6 36
     73#define RISCV_INTERRUPT_FRAME_A7 40
     74#define RISCV_INTERRUPT_FRAME_T0 44
     75#define RISCV_INTERRUPT_FRAME_T1 48
     76#define RISCV_INTERRUPT_FRAME_T2 52
     77#define RISCV_INTERRUPT_FRAME_T3 56
     78#define RISCV_INTERRUPT_FRAME_T4 60
     79#define RISCV_INTERRUPT_FRAME_T5 64
     80#define RISCV_INTERRUPT_FRAME_T6 68
     81#define RISCV_INTERRUPT_FRAME_A0 72
     82#define RISCV_INTERRUPT_FRAME_A1 76
     83
     84#define CPU_INTERRUPT_FRAME_SIZE 80
    4485
    4586#elif __riscv_xlen == 64
    4687
    47 #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 256
     88#define RISCV_CONTEXT_RA 8
     89#define RISCV_CONTEXT_SP 16
     90#define RISCV_CONTEXT_TP 24
     91#define RISCV_CONTEXT_S0 32
     92#define RISCV_CONTEXT_S1 40
     93#define RISCV_CONTEXT_S2 48
     94#define RISCV_CONTEXT_S3 56
     95#define RISCV_CONTEXT_S4 64
     96#define RISCV_CONTEXT_S5 72
     97#define RISCV_CONTEXT_S6 80
     98#define RISCV_CONTEXT_S7 88
     99#define RISCV_CONTEXT_S8 96
     100#define RISCV_CONTEXT_S9 104
     101#define RISCV_CONTEXT_S10 112
     102#define RISCV_CONTEXT_S11 120
    48103
    49 #define CPU_INTERRUPT_FRAME_SIZE 280
     104#define RISCV_INTERRUPT_FRAME_MSTATUS 0
     105#define RISCV_INTERRUPT_FRAME_MEPC 8
     106#define RISCV_INTERRUPT_FRAME_A2 16
     107#define RISCV_INTERRUPT_FRAME_S0 24
     108#define RISCV_INTERRUPT_FRAME_S1 32
     109#define RISCV_INTERRUPT_FRAME_RA 40
     110#define RISCV_INTERRUPT_FRAME_A3 48
     111#define RISCV_INTERRUPT_FRAME_A4 56
     112#define RISCV_INTERRUPT_FRAME_A5 64
     113#define RISCV_INTERRUPT_FRAME_A6 72
     114#define RISCV_INTERRUPT_FRAME_A7 80
     115#define RISCV_INTERRUPT_FRAME_T0 88
     116#define RISCV_INTERRUPT_FRAME_T1 96
     117#define RISCV_INTERRUPT_FRAME_T2 104
     118#define RISCV_INTERRUPT_FRAME_T3 112
     119#define RISCV_INTERRUPT_FRAME_T4 120
     120#define RISCV_INTERRUPT_FRAME_T5 128
     121#define RISCV_INTERRUPT_FRAME_T6 136
     122#define RISCV_INTERRUPT_FRAME_A0 144
     123#define RISCV_INTERRUPT_FRAME_A1 152
     124
     125#define CPU_INTERRUPT_FRAME_SIZE 160
    50126
    51127#endif /* __riscv_xlen */
     
    58134
    59135typedef struct {
    60   unsigned long x[32];
    61   unsigned long mstatus;
    62   unsigned long mcause;
    63   unsigned long mepc;
    64 } CPU_Interrupt_frame;
     136  uintptr_t mstatus;
     137  uintptr_t mepc;
     138  uintptr_t a2;
     139  uintptr_t s0;
     140  uintptr_t s1;
     141  uintptr_t ra;
     142  uintptr_t a3;
     143  uintptr_t a4;
     144  uintptr_t a5;
     145  uintptr_t a6;
     146  uintptr_t a7;
     147  uintptr_t t0;
     148  uintptr_t t1;
     149  uintptr_t t2;
     150  uintptr_t t3;
     151  uintptr_t t4;
     152  uintptr_t t5;
     153  uintptr_t t6;
     154  uintptr_t a0;
     155  uintptr_t a1;
     156} RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame;
    65157
    66158#ifdef RTEMS_SMP
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