Changeset e43994d in rtems for cpukit/score/cpu/riscv/cpu.c


Ignore:
Timestamp:
Jun 27, 2018, 8:05:50 AM (2 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
afb60eb
Parents:
a8188730
git-author:
Sebastian Huber <sebastian.huber@…> (06/27/18 08:05:50)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:37)
Message:

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/cpu.c

    ra8188730 re43994d  
    4141
    4242RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE );
     43#ifdef RTEMS_SMP
     44RISCV_ASSERT_CONTEXT_OFFSET( is_executing, IS_EXECUTING );
     45#endif
     46RISCV_ASSERT_CONTEXT_OFFSET( ra, RA );
     47RISCV_ASSERT_CONTEXT_OFFSET( sp, SP );
     48RISCV_ASSERT_CONTEXT_OFFSET( tp, TP );
     49RISCV_ASSERT_CONTEXT_OFFSET( s0, S0 );
     50RISCV_ASSERT_CONTEXT_OFFSET( s1, S1 );
     51RISCV_ASSERT_CONTEXT_OFFSET( s2, S2 );
     52RISCV_ASSERT_CONTEXT_OFFSET( s3, S3 );
     53RISCV_ASSERT_CONTEXT_OFFSET( s4, S4 );
     54RISCV_ASSERT_CONTEXT_OFFSET( s5, S5 );
     55RISCV_ASSERT_CONTEXT_OFFSET( s6, S6 );
     56RISCV_ASSERT_CONTEXT_OFFSET( s7, S7 );
     57RISCV_ASSERT_CONTEXT_OFFSET( s8, S8 );
     58RISCV_ASSERT_CONTEXT_OFFSET( s9, S9 );
     59RISCV_ASSERT_CONTEXT_OFFSET( s10, S10 );
     60RISCV_ASSERT_CONTEXT_OFFSET( s11, S11 );
     61
     62#define RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( field, off ) \
     63  RTEMS_STATIC_ASSERT( \
     64    offsetof( CPU_Interrupt_frame, field) == RISCV_INTERRUPT_FRAME_ ## off, \
     65    riscv_interrupt_frame_offset_ ## field \
     66  )
     67
     68RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mstatus, MSTATUS );
     69RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mepc, MEPC );
     70RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a2, A2 );
     71RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s0, S0 );
     72RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s1, S1 );
     73RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ra, RA );
     74RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a3, A3 );
     75RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a4, A4 );
     76RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a5, A5 );
     77RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a6, A6 );
     78RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a7, A7 );
     79RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t0, T0 );
     80RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t1, T1 );
     81RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t2, T2 );
     82RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t3, T3 );
     83RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t4, T4 );
     84RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t5, T5 );
     85RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t6, T6 );
     86RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a0, A0 );
     87RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a1, A1 );
     88
     89RTEMS_STATIC_ASSERT(
     90  sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0,
     91  riscv_interrupt_frame_size
     92);
    4393
    4494/* bsp_start_vector_table_begin is the start address of the vector table
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