Changeset e43994d in rtems


Ignore:
Timestamp:
Jun 27, 2018, 8:05:50 AM (11 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
afb60eb
Parents:
a8188730
git-author:
Sebastian Huber <sebastian.huber@…> (06/27/18 08:05:50)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:37)
Message:

riscv: Optimize context switch and interrupts

Save/restore non-volatile registers in _CPU_Context_switch().

Save/restore volatile registers in _ISR_Handler().

Update #3433.

Location:
cpukit/score/cpu/riscv
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/cpu.c

    ra8188730 re43994d  
    4141
    4242RISCV_ASSERT_CONTEXT_OFFSET( isr_dispatch_disable, ISR_DISPATCH_DISABLE );
     43#ifdef RTEMS_SMP
     44RISCV_ASSERT_CONTEXT_OFFSET( is_executing, IS_EXECUTING );
     45#endif
     46RISCV_ASSERT_CONTEXT_OFFSET( ra, RA );
     47RISCV_ASSERT_CONTEXT_OFFSET( sp, SP );
     48RISCV_ASSERT_CONTEXT_OFFSET( tp, TP );
     49RISCV_ASSERT_CONTEXT_OFFSET( s0, S0 );
     50RISCV_ASSERT_CONTEXT_OFFSET( s1, S1 );
     51RISCV_ASSERT_CONTEXT_OFFSET( s2, S2 );
     52RISCV_ASSERT_CONTEXT_OFFSET( s3, S3 );
     53RISCV_ASSERT_CONTEXT_OFFSET( s4, S4 );
     54RISCV_ASSERT_CONTEXT_OFFSET( s5, S5 );
     55RISCV_ASSERT_CONTEXT_OFFSET( s6, S6 );
     56RISCV_ASSERT_CONTEXT_OFFSET( s7, S7 );
     57RISCV_ASSERT_CONTEXT_OFFSET( s8, S8 );
     58RISCV_ASSERT_CONTEXT_OFFSET( s9, S9 );
     59RISCV_ASSERT_CONTEXT_OFFSET( s10, S10 );
     60RISCV_ASSERT_CONTEXT_OFFSET( s11, S11 );
     61
     62#define RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( field, off ) \
     63  RTEMS_STATIC_ASSERT( \
     64    offsetof( CPU_Interrupt_frame, field) == RISCV_INTERRUPT_FRAME_ ## off, \
     65    riscv_interrupt_frame_offset_ ## field \
     66  )
     67
     68RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mstatus, MSTATUS );
     69RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( mepc, MEPC );
     70RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a2, A2 );
     71RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s0, S0 );
     72RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( s1, S1 );
     73RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( ra, RA );
     74RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a3, A3 );
     75RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a4, A4 );
     76RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a5, A5 );
     77RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a6, A6 );
     78RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a7, A7 );
     79RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t0, T0 );
     80RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t1, T1 );
     81RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t2, T2 );
     82RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t3, T3 );
     83RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t4, T4 );
     84RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t5, T5 );
     85RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( t6, T6 );
     86RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a0, A0 );
     87RISCV_ASSERT_INTERRUPT_FRAME_OFFSET( a1, A1 );
     88
     89RTEMS_STATIC_ASSERT(
     90  sizeof( CPU_Interrupt_frame ) % CPU_STACK_ALIGNMENT == 0,
     91  riscv_interrupt_frame_size
     92);
    4393
    4494/* bsp_start_vector_table_begin is the start address of the vector table
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    ra8188730 re43994d  
    106106
    107107typedef struct {
    108   /* riscv has 32 xlen-bit (where xlen can be 32 or 64) general purpose registers (x0-x31)*/
    109   unsigned long x[32];
    110 
     108#ifdef RTEMS_SMP
     109  volatile uint32_t is_executing;
     110#else
     111  uint32_t reserved;
     112#endif
    111113  uint32_t isr_dispatch_disable;
    112 #ifdef RTEMS_SMP
    113   volatile bool is_executing;
    114 #endif
     114  uintptr_t ra;
     115  uintptr_t sp;
     116  uintptr_t tp;
     117  uintptr_t s0;
     118  uintptr_t s1;
     119  uintptr_t s2;
     120  uintptr_t s3;
     121  uintptr_t s4;
     122  uintptr_t s5;
     123  uintptr_t s6;
     124  uintptr_t s7;
     125  uintptr_t s8;
     126  uintptr_t s9;
     127  uintptr_t s10;
     128  uintptr_t s11;
    115129} Context_Control;
    116130
    117131#define _CPU_Context_Get_SP( _context ) \
    118   (_context)->x[2]
     132  (_context)->sp
    119133
    120134typedef struct {
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    ra8188730 re43994d  
    3737#define CPU_PER_CPU_CONTROL_SIZE 0
    3838
     39#ifdef RTEMS_SMP
     40#define RISCV_CONTEXT_IS_EXECUTING 0
     41#endif
     42
     43#define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 4
     44
    3945#if __riscv_xlen == 32
    4046
    41 #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 128
     47#define RISCV_CONTEXT_RA 8
     48#define RISCV_CONTEXT_SP 12
     49#define RISCV_CONTEXT_TP 16
     50#define RISCV_CONTEXT_S0 20
     51#define RISCV_CONTEXT_S1 24
     52#define RISCV_CONTEXT_S2 28
     53#define RISCV_CONTEXT_S3 32
     54#define RISCV_CONTEXT_S4 36
     55#define RISCV_CONTEXT_S5 40
     56#define RISCV_CONTEXT_S6 44
     57#define RISCV_CONTEXT_S7 48
     58#define RISCV_CONTEXT_S8 52
     59#define RISCV_CONTEXT_S9 56
     60#define RISCV_CONTEXT_S10 60
     61#define RISCV_CONTEXT_S11 64
    4262
    43 #define CPU_INTERRUPT_FRAME_SIZE 140
     63#define RISCV_INTERRUPT_FRAME_MSTATUS 0
     64#define RISCV_INTERRUPT_FRAME_MEPC 4
     65#define RISCV_INTERRUPT_FRAME_A2 8
     66#define RISCV_INTERRUPT_FRAME_S0 12
     67#define RISCV_INTERRUPT_FRAME_S1 16
     68#define RISCV_INTERRUPT_FRAME_RA 20
     69#define RISCV_INTERRUPT_FRAME_A3 24
     70#define RISCV_INTERRUPT_FRAME_A4 28
     71#define RISCV_INTERRUPT_FRAME_A5 32
     72#define RISCV_INTERRUPT_FRAME_A6 36
     73#define RISCV_INTERRUPT_FRAME_A7 40
     74#define RISCV_INTERRUPT_FRAME_T0 44
     75#define RISCV_INTERRUPT_FRAME_T1 48
     76#define RISCV_INTERRUPT_FRAME_T2 52
     77#define RISCV_INTERRUPT_FRAME_T3 56
     78#define RISCV_INTERRUPT_FRAME_T4 60
     79#define RISCV_INTERRUPT_FRAME_T5 64
     80#define RISCV_INTERRUPT_FRAME_T6 68
     81#define RISCV_INTERRUPT_FRAME_A0 72
     82#define RISCV_INTERRUPT_FRAME_A1 76
     83
     84#define CPU_INTERRUPT_FRAME_SIZE 80
    4485
    4586#elif __riscv_xlen == 64
    4687
    47 #define RISCV_CONTEXT_ISR_DISPATCH_DISABLE 256
     88#define RISCV_CONTEXT_RA 8
     89#define RISCV_CONTEXT_SP 16
     90#define RISCV_CONTEXT_TP 24
     91#define RISCV_CONTEXT_S0 32
     92#define RISCV_CONTEXT_S1 40
     93#define RISCV_CONTEXT_S2 48
     94#define RISCV_CONTEXT_S3 56
     95#define RISCV_CONTEXT_S4 64
     96#define RISCV_CONTEXT_S5 72
     97#define RISCV_CONTEXT_S6 80
     98#define RISCV_CONTEXT_S7 88
     99#define RISCV_CONTEXT_S8 96
     100#define RISCV_CONTEXT_S9 104
     101#define RISCV_CONTEXT_S10 112
     102#define RISCV_CONTEXT_S11 120
    48103
    49 #define CPU_INTERRUPT_FRAME_SIZE 280
     104#define RISCV_INTERRUPT_FRAME_MSTATUS 0
     105#define RISCV_INTERRUPT_FRAME_MEPC 8
     106#define RISCV_INTERRUPT_FRAME_A2 16
     107#define RISCV_INTERRUPT_FRAME_S0 24
     108#define RISCV_INTERRUPT_FRAME_S1 32
     109#define RISCV_INTERRUPT_FRAME_RA 40
     110#define RISCV_INTERRUPT_FRAME_A3 48
     111#define RISCV_INTERRUPT_FRAME_A4 56
     112#define RISCV_INTERRUPT_FRAME_A5 64
     113#define RISCV_INTERRUPT_FRAME_A6 72
     114#define RISCV_INTERRUPT_FRAME_A7 80
     115#define RISCV_INTERRUPT_FRAME_T0 88
     116#define RISCV_INTERRUPT_FRAME_T1 96
     117#define RISCV_INTERRUPT_FRAME_T2 104
     118#define RISCV_INTERRUPT_FRAME_T3 112
     119#define RISCV_INTERRUPT_FRAME_T4 120
     120#define RISCV_INTERRUPT_FRAME_T5 128
     121#define RISCV_INTERRUPT_FRAME_T6 136
     122#define RISCV_INTERRUPT_FRAME_A0 144
     123#define RISCV_INTERRUPT_FRAME_A1 152
     124
     125#define CPU_INTERRUPT_FRAME_SIZE 160
    50126
    51127#endif /* __riscv_xlen */
     
    58134
    59135typedef struct {
    60   unsigned long x[32];
    61   unsigned long mstatus;
    62   unsigned long mcause;
    63   unsigned long mepc;
    64 } CPU_Interrupt_frame;
     136  uintptr_t mstatus;
     137  uintptr_t mepc;
     138  uintptr_t a2;
     139  uintptr_t s0;
     140  uintptr_t s1;
     141  uintptr_t ra;
     142  uintptr_t a3;
     143  uintptr_t a4;
     144  uintptr_t a5;
     145  uintptr_t a6;
     146  uintptr_t a7;
     147  uintptr_t t0;
     148  uintptr_t t1;
     149  uintptr_t t2;
     150  uintptr_t t3;
     151  uintptr_t t4;
     152  uintptr_t t5;
     153  uintptr_t t6;
     154  uintptr_t a0;
     155  uintptr_t a1;
     156} RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame;
    65157
    66158#ifdef RTEMS_SMP
  • cpukit/score/cpu/riscv/riscv-context-initialize.c

    ra8188730 re43994d  
    5252  stack = _Addresses_Align_down( stack, CPU_STACK_ALIGNMENT );
    5353
    54   /* Stack Pointer - sp/x2 */
    55   context->x[2] = (uintptr_t) stack;
    56 
    57   /* Return Address - ra/x1 */
    58   context->x[1] = (uintptr_t) entry_point;
    59 
     54  context->ra = (uintptr_t) entry_point;
     55  context->sp = (uintptr_t) stack;
    6056  context->isr_dispatch_disable = 0;
    6157}
  • cpukit/score/cpu/riscv/riscv-context-switch.S

    ra8188730 re43994d  
    4646        lw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
    4747
    48         SREG    x1, (1 * CPU_SIZEOF_POINTER)(a0)
    49         SREG    x2, (2 * CPU_SIZEOF_POINTER)(a0)
    50         SREG    x4, (4 * CPU_SIZEOF_POINTER)(a0)
    51         SREG    x5, (5 * CPU_SIZEOF_POINTER)(a0)
    52         SREG    x6, (6 * CPU_SIZEOF_POINTER)(a0)
    53         SREG    x7, (7 * CPU_SIZEOF_POINTER)(a0)
    54         SREG    x8, (8 * CPU_SIZEOF_POINTER)(a0)
    55         SREG    x9, (9 * CPU_SIZEOF_POINTER)(a0)
    56         SREG    x10, (10 * CPU_SIZEOF_POINTER)(a0)
    57         SREG    x11, (11 * CPU_SIZEOF_POINTER)(a0)
    58         SREG    x12, (12 * CPU_SIZEOF_POINTER)(a0)
    59         SREG    x13, (13 * CPU_SIZEOF_POINTER)(a0)
    60         SREG    x14, (14 * CPU_SIZEOF_POINTER)(a0)
    61         SREG    x15, (15 * CPU_SIZEOF_POINTER)(a0)
    62         SREG    x16, (16 * CPU_SIZEOF_POINTER)(a0)
    63         SREG    x17, (17 * CPU_SIZEOF_POINTER)(a0)
    64         SREG    x18, (18 * CPU_SIZEOF_POINTER)(a0)
    65         SREG    x19, (19 * CPU_SIZEOF_POINTER)(a0)
    66         SREG    x20, (20 * CPU_SIZEOF_POINTER)(a0)
    67         SREG    x21, (21 * CPU_SIZEOF_POINTER)(a0)
    68         SREG    x22, (22 * CPU_SIZEOF_POINTER)(a0)
    69         SREG    x23, (23 * CPU_SIZEOF_POINTER)(a0)
    70         SREG    x24, (24 * CPU_SIZEOF_POINTER)(a0)
    71         SREG    x25, (25 * CPU_SIZEOF_POINTER)(a0)
    72         SREG    x26, (26 * CPU_SIZEOF_POINTER)(a0)
    73         SREG    x27, (27 * CPU_SIZEOF_POINTER)(a0)
    74         SREG    x28, (28 * CPU_SIZEOF_POINTER)(a0)
    75         SREG    x29, (28 * CPU_SIZEOF_POINTER)(a0)
    76         SREG    x30, (30 * CPU_SIZEOF_POINTER)(a0)
    77         SREG    x31, (31 * CPU_SIZEOF_POINTER)(a0)
     48        SREG    ra, RISCV_CONTEXT_RA(a0)
     49        SREG    sp, RISCV_CONTEXT_SP(a0)
     50        SREG    s0, RISCV_CONTEXT_S0(a0)
     51        SREG    s1, RISCV_CONTEXT_S1(a0)
     52        SREG    s2, RISCV_CONTEXT_S2(a0)
     53        SREG    s3, RISCV_CONTEXT_S3(a0)
     54        SREG    s4, RISCV_CONTEXT_S4(a0)
     55        SREG    s5, RISCV_CONTEXT_S5(a0)
     56        SREG    s6, RISCV_CONTEXT_S6(a0)
     57        SREG    s7, RISCV_CONTEXT_S7(a0)
     58        SREG    s8, RISCV_CONTEXT_S8(a0)
     59        SREG    s9, RISCV_CONTEXT_S9(a0)
     60        SREG    s10, RISCV_CONTEXT_S10(a0)
     61        SREG    s11, RISCV_CONTEXT_S11(a0)
    7862
    7963        sw      a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a0)
     
    8266        lw      a3, RISCV_CONTEXT_ISR_DISPATCH_DISABLE(a1)
    8367
     68        LREG    ra, RISCV_CONTEXT_RA(a1)
     69        LREG    sp, RISCV_CONTEXT_SP(a1)
     70        LREG    s0, RISCV_CONTEXT_S0(a1)
     71        LREG    s1, RISCV_CONTEXT_S1(a1)
     72        LREG    s2, RISCV_CONTEXT_S2(a1)
     73        LREG    s3, RISCV_CONTEXT_S3(a1)
     74        LREG    s4, RISCV_CONTEXT_S4(a1)
     75        LREG    s5, RISCV_CONTEXT_S5(a1)
     76        LREG    s6, RISCV_CONTEXT_S6(a1)
     77        LREG    s7, RISCV_CONTEXT_S7(a1)
     78        LREG    s8, RISCV_CONTEXT_S8(a1)
     79        LREG    s9, RISCV_CONTEXT_S9(a1)
     80        LREG    s10, RISCV_CONTEXT_S10(a1)
     81        LREG    s11, RISCV_CONTEXT_S11(a1)
     82
    8483        sw      a3, PER_CPU_ISR_DISPATCH_DISABLE(a2)
    85 
    86         LREG    x1, (1 * CPU_SIZEOF_POINTER)(a1)
    87         LREG    x2, (2 * CPU_SIZEOF_POINTER)(a1)
    88         LREG    x4, (4 * CPU_SIZEOF_POINTER)(a1)
    89         LREG    x5, (5 * CPU_SIZEOF_POINTER)(a1)
    90         LREG    x6, (6 * CPU_SIZEOF_POINTER)(a1)
    91         LREG    x7, (7 * CPU_SIZEOF_POINTER)(a1)
    92         LREG    x8, (8 * CPU_SIZEOF_POINTER)(a1)
    93         LREG    x9, (9 * CPU_SIZEOF_POINTER)(a1)
    94         LREG    x10, (10 * CPU_SIZEOF_POINTER)(a1)
    95         /* Skip a1/x11 */
    96         LREG    x12, (12 * CPU_SIZEOF_POINTER)(a1)
    97         LREG    x13, (13 * CPU_SIZEOF_POINTER)(a1)
    98         LREG    x14, (14 * CPU_SIZEOF_POINTER)(a1)
    99         LREG    x15, (15 * CPU_SIZEOF_POINTER)(a1)
    100         LREG    x16, (16 * CPU_SIZEOF_POINTER)(a1)
    101         LREG    x17, (17 * CPU_SIZEOF_POINTER)(a1)
    102         LREG    x18, (18 * CPU_SIZEOF_POINTER)(a1)
    103         LREG    x19, (19 * CPU_SIZEOF_POINTER)(a1)
    104         LREG    x20, (20 * CPU_SIZEOF_POINTER)(a1)
    105         LREG    x21, (21 * CPU_SIZEOF_POINTER)(a1)
    106         LREG    x22, (22 * CPU_SIZEOF_POINTER)(a1)
    107         LREG    x23, (23 * CPU_SIZEOF_POINTER)(a1)
    108         LREG    x24, (24 * CPU_SIZEOF_POINTER)(a1)
    109         LREG    x25, (25 * CPU_SIZEOF_POINTER)(a1)
    110         LREG    x26, (26 * CPU_SIZEOF_POINTER)(a1)
    111         LREG    x27, (27 * CPU_SIZEOF_POINTER)(a1)
    112         LREG    x28, (28 * CPU_SIZEOF_POINTER)(a1)
    113         LREG    x29, (29 * CPU_SIZEOF_POINTER)(a1)
    114         LREG    x30, (30 * CPU_SIZEOF_POINTER)(a1)
    115 
    116         LREG    x11, (11 * CPU_SIZEOF_POINTER)(a1)
    11784
    11885        ret
  • cpukit/score/cpu/riscv/riscv-exception-handler.S

    ra8188730 re43994d  
    5151TYPE_FUNC(ISR_Handler)
    5252SYM(ISR_Handler):
    53         addi    sp, sp, -1 * 36 * CPU_SIZEOF_POINTER
     53        addi    sp, sp, -CPU_INTERRUPT_FRAME_SIZE
    5454
    55         SREG    x1, (1 * CPU_SIZEOF_POINTER)(sp)
    56         /* Skip x2/sp */
    57         SREG    x3, (3 * CPU_SIZEOF_POINTER)(sp)
    58         SREG    x4, (4 * CPU_SIZEOF_POINTER)(sp)
    59         SREG    x5, (5 * CPU_SIZEOF_POINTER)(sp)
    60         SREG    x6, (6 * CPU_SIZEOF_POINTER)(sp)
    61         SREG    x7, (7 * CPU_SIZEOF_POINTER)(sp)
    62         SREG    x8, (8 * CPU_SIZEOF_POINTER)(sp)
    63         SREG    x9, (9 * CPU_SIZEOF_POINTER)(sp)
    64         SREG    x10, (10 * CPU_SIZEOF_POINTER)(sp)
    65         SREG    x11, (11 * CPU_SIZEOF_POINTER)(sp)
    66         SREG    x12, (12 * CPU_SIZEOF_POINTER)(sp)
    67         SREG    x13, (13 * CPU_SIZEOF_POINTER)(sp)
    68         SREG    x14, (14 * CPU_SIZEOF_POINTER)(sp)
    69         SREG    x15, (15 * CPU_SIZEOF_POINTER)(sp)
    70         SREG    x16, (16 * CPU_SIZEOF_POINTER)(sp)
    71         SREG    x17, (17 * CPU_SIZEOF_POINTER)(sp)
    72         SREG    x18, (18 * CPU_SIZEOF_POINTER)(sp)
    73         SREG    x19, (19 * CPU_SIZEOF_POINTER)(sp)
    74         SREG    x20, (20 * CPU_SIZEOF_POINTER)(sp)
    75         SREG    x21, (21 * CPU_SIZEOF_POINTER)(sp)
    76         SREG    x22, (22 * CPU_SIZEOF_POINTER)(sp)
    77         SREG    x23, (23 * CPU_SIZEOF_POINTER)(sp)
    78         SREG    x24, (24 * CPU_SIZEOF_POINTER)(sp)
    79         SREG    x25, (25 * CPU_SIZEOF_POINTER)(sp)
    80         SREG    x26, (26 * CPU_SIZEOF_POINTER)(sp)
    81         SREG    x27, (27 * CPU_SIZEOF_POINTER)(sp)
    82         SREG    x28, (28 * CPU_SIZEOF_POINTER)(sp)
    83         SREG    x29, (29 * CPU_SIZEOF_POINTER)(sp)
    84         SREG    x30, (30 * CPU_SIZEOF_POINTER)(sp)
    85         SREG    x31, (31 * CPU_SIZEOF_POINTER)(sp)
    86 
    87         /* Exception level related registers */
    88         csrr    a0, mstatus
    89         SREG    a0, (32 * CPU_SIZEOF_POINTER)(sp)
     55        /* Save */
     56        SREG    a0, RISCV_INTERRUPT_FRAME_A0(sp)
     57        SREG    a1, RISCV_INTERRUPT_FRAME_A1(sp)
     58        SREG    a2, RISCV_INTERRUPT_FRAME_A2(sp)
     59        SREG    s0, RISCV_INTERRUPT_FRAME_S0(sp)
    9060        csrr    a0, mcause
    91         SREG    a0, (33 * CPU_SIZEOF_POINTER)(sp)
    92         csrr    a1, mepc
    93         SREG    a1, (34 * CPU_SIZEOF_POINTER)(sp)
     61        csrr    a1, mstatus
     62        csrr    a2, mepc
     63        GET_SELF_CPU_CONTROL    s0
     64        SREG    s1, RISCV_INTERRUPT_FRAME_S1(sp)
     65        SREG    ra, RISCV_INTERRUPT_FRAME_RA(sp)
     66        SREG    a3, RISCV_INTERRUPT_FRAME_A3(sp)
     67        SREG    a4, RISCV_INTERRUPT_FRAME_A4(sp)
     68        SREG    a5, RISCV_INTERRUPT_FRAME_A5(sp)
     69        SREG    a6, RISCV_INTERRUPT_FRAME_A6(sp)
     70        SREG    a7, RISCV_INTERRUPT_FRAME_A7(sp)
     71        SREG    t0, RISCV_INTERRUPT_FRAME_T0(sp)
     72        SREG    t1, RISCV_INTERRUPT_FRAME_T1(sp)
     73        SREG    t2, RISCV_INTERRUPT_FRAME_T2(sp)
     74        SREG    t3, RISCV_INTERRUPT_FRAME_T3(sp)
     75        SREG    t4, RISCV_INTERRUPT_FRAME_T4(sp)
     76        SREG    t5, RISCV_INTERRUPT_FRAME_T5(sp)
     77        SREG    t6, RISCV_INTERRUPT_FRAME_T6(sp)
     78        SREG    a1, RISCV_INTERRUPT_FRAME_MSTATUS(sp)
     79        SREG    a2, RISCV_INTERRUPT_FRAME_MEPC(sp)
    9480
    9581        /* FIXME Only handle interrupts for now (MSB = 1) */
    9682        andi    a0, a0, 0xf
    97 
    98         /* Get per-CPU control of current processor */
    99         GET_SELF_CPU_CONTROL    s0
    10083
    10184        /* Increment interrupt nest and thread dispatch disable level */
     
    10689        sw      t2, PER_CPU_ISR_NEST_LEVEL(s0)
    10790        sw      t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
    108 
    109         /* Save interrupted task stack pointer */
    110         addi    t4, sp, 36 * CPU_SIZEOF_POINTER
    111         SREG    t4, (2 * CPU_SIZEOF_POINTER)(sp)
    11291
    11392        /* Keep sp (Exception frame address) in s1 */
     
    192171.Lthread_dispatch_done:
    193172
    194         LREG    x1, (1 * CPU_SIZEOF_POINTER)(sp)
    195         /* Skip sp/x2 */
    196         LREG    x3, (3 * CPU_SIZEOF_POINTER)(sp)
    197         LREG    x4, (4 * CPU_SIZEOF_POINTER)(sp)
    198         LREG    x5, (5 * CPU_SIZEOF_POINTER)(sp)
    199         LREG    x6, (6 * CPU_SIZEOF_POINTER)(sp)
    200         LREG    x7, (7 * CPU_SIZEOF_POINTER)(sp)
    201         LREG    x8, (8 * CPU_SIZEOF_POINTER)(sp)
    202         LREG    x9, (9 * CPU_SIZEOF_POINTER)(sp)
    203         LREG    x10, (10 * CPU_SIZEOF_POINTER)(sp)
    204         LREG    x11, (11 * CPU_SIZEOF_POINTER)(sp)
    205         LREG    x12, (12 * CPU_SIZEOF_POINTER)(sp)
    206         LREG    x13, (13 * CPU_SIZEOF_POINTER)(sp)
    207         LREG    x14, (14 * CPU_SIZEOF_POINTER)(sp)
    208         LREG    x15, (15 * CPU_SIZEOF_POINTER)(sp)
    209         LREG    x16, (16 * CPU_SIZEOF_POINTER)(sp)
    210         LREG    x17, (17 * CPU_SIZEOF_POINTER)(sp)
    211         LREG    x18, (18 * CPU_SIZEOF_POINTER)(sp)
    212         LREG    x19, (19 * CPU_SIZEOF_POINTER)(sp)
    213         LREG    x20, (20 * CPU_SIZEOF_POINTER)(sp)
    214         LREG    x21, (21 * CPU_SIZEOF_POINTER)(sp)
    215         LREG    x22, (22 * CPU_SIZEOF_POINTER)(sp)
    216         LREG    x23, (23 * CPU_SIZEOF_POINTER)(sp)
    217         LREG    x24, (24 * CPU_SIZEOF_POINTER)(sp)
    218         LREG    x25, (25 * CPU_SIZEOF_POINTER)(sp)
    219         LREG    x26, (26 * CPU_SIZEOF_POINTER)(sp)
    220         LREG    x27, (27 * CPU_SIZEOF_POINTER)(sp)
    221         LREG    x28, (28 * CPU_SIZEOF_POINTER)(sp)
    222         LREG    x29, (29 * CPU_SIZEOF_POINTER)(sp)
    223         LREG    x30, (30 * CPU_SIZEOF_POINTER)(sp)
     173        /* Restore */
     174        LREG    a0, RISCV_INTERRUPT_FRAME_MSTATUS(sp)
     175        LREG    a1, RISCV_INTERRUPT_FRAME_MEPC(sp)
     176        LREG    a2, RISCV_INTERRUPT_FRAME_A2(sp)
     177        LREG    s0, RISCV_INTERRUPT_FRAME_S0(sp)
     178        LREG    s1, RISCV_INTERRUPT_FRAME_S1(sp)
     179        LREG    ra, RISCV_INTERRUPT_FRAME_RA(sp)
     180        LREG    a3, RISCV_INTERRUPT_FRAME_A3(sp)
     181        LREG    a4, RISCV_INTERRUPT_FRAME_A4(sp)
     182        LREG    a5, RISCV_INTERRUPT_FRAME_A5(sp)
     183        LREG    a6, RISCV_INTERRUPT_FRAME_A6(sp)
     184        LREG    a7, RISCV_INTERRUPT_FRAME_A7(sp)
     185        LREG    t0, RISCV_INTERRUPT_FRAME_T0(sp)
     186        LREG    t1, RISCV_INTERRUPT_FRAME_T1(sp)
     187        LREG    t2, RISCV_INTERRUPT_FRAME_T2(sp)
     188        LREG    t3, RISCV_INTERRUPT_FRAME_T3(sp)
     189        LREG    t4, RISCV_INTERRUPT_FRAME_T4(sp)
     190        LREG    t5, RISCV_INTERRUPT_FRAME_T5(sp)
     191        LREG    t6, RISCV_INTERRUPT_FRAME_T6(sp)
     192        csrw    mstatus, a0
     193        csrw    mepc, a1
     194        LREG    a0, RISCV_INTERRUPT_FRAME_A0(sp)
     195        LREG    a1, RISCV_INTERRUPT_FRAME_A1(sp)
    224196
    225         /* Load mstatus */
    226         LREG    x31, (32 * CPU_SIZEOF_POINTER)(sp)
    227         csrw    mstatus, x31
    228         /* Load mepc */
    229         LREG    x31, (34 * CPU_SIZEOF_POINTER)(sp)
    230         csrw    mepc, x31
    231 
    232         LREG    x31, (31 * CPU_SIZEOF_POINTER)(sp)
    233 
    234         /* Unwind exception frame */
    235         addi    sp, sp, 36 * CPU_SIZEOF_POINTER
     197        addi    sp, sp, CPU_INTERRUPT_FRAME_SIZE
    236198
    237199        mret
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