Changeset e36390a6 in rtems for c/src/lib/libbsp/powerpc/ep1a


Ignore:
Timestamp:
Sep 3, 2008, 8:35:43 PM (11 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.9, master
Children:
40e7ae2
Parents:
4598164
Message:

2008-09-03 Joel Sherrill <joel.sherrill@…>

  • Makefile.am, configure.ac, console/alloc360.c, console/console.c, console/console.h, console/m68360.h, console/mc68360_scc.c, console/ns16550cfg.c, console/rsPMCQ1.c, console/rsPMCQ1.h, include/bsp.h, irq/irq_init.c, vme/VMEConfig.h: Initiate update and testing. Add missing files. Does not run hello yet.
  • console/debugio.c, console/polled_io.c, irq/openpic_xxx_irq.c: New files.
Location:
c/src/lib/libbsp/powerpc/ep1a
Files:
3 added
14 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ep1a/ChangeLog

    r4598164 re36390a6  
     12008-09-03      Joel Sherrill <joel.sherrill@OARcorp.com>
     2
     3        * Makefile.am, configure.ac, console/alloc360.c, console/console.c,
     4        console/console.h, console/m68360.h, console/mc68360_scc.c,
     5        console/ns16550cfg.c, console/rsPMCQ1.c, console/rsPMCQ1.h,
     6        include/bsp.h, irq/irq_init.c, vme/VMEConfig.h: Initiate update and
     7        testing. Add missing files. Does not run hello yet.
     8        * console/debugio.c, console/polled_io.c, irq/openpic_xxx_irq.c: New files.
     9
    1102008-08-20      Ralf Corsépius <ralf.corsepius@rtems.org>
    211
  • c/src/lib/libbsp/powerpc/ep1a/Makefile.am

    r4598164 re36390a6  
    5555        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/vectors.h \
    5656        ../../../libcpu/@RTEMS_CPU@/@exceptions@/bspsupport/irq_supp.h
    57 irq_SOURCES = irq/irq_init.c ../shared/irq/openpic_i8259_irq.c ../../powerpc/shared/irq/i8259.c
     57irq_SOURCES = irq/irq_init.c irq/openpic_xxx_irq.c ../../powerpc/shared/irq/i8259.c
    5858
    5959include_bsp_HEADERS += ../../shared/vmeUniverse/vmeUniverse.h \
  • c/src/lib/libbsp/powerpc/ep1a/configure.ac

    r4598164 re36390a6  
    1616RTEMS_PROG_CCAS
    1717
     18RTEMS_BSPOPTS_SET([PPC_USE_DATA_CACHE],[*],[0])
     19RTEMS_BSPOPTS_HELP([PPC_USE_DATA_CACHE],
     20[If defined, then the PowerPC specific code in RTEMS will use
     21 data cache instructions to optimize the context switch code.
     22 This code can conflict with debuggers or emulators.  It is known
     23 to break the Corelis PowerPC emulator with at least some combinations
     24 of PowerPC 603e revisions and emulator versions.
     25 The BSP actually contains the call that enables this.])
     26
     27RTEMS_BSPOPTS_SET([INSTRUCTION_CACHE_ENABLE],[*],[0])
     28RTEMS_BSPOPTS_HELP([INSTRUCTION_CACHE_ENABLE],
     29[If defined, the instruction cache will be enabled after address translation
     30 is turned on.])
     31
    1832RTEMS_BSPOPTS_SET([CONSOLE_USE_INTERRUPTS],[*],[0])
    1933RTEMS_BSPOPTS_HELP([CONSOLE_USE_INTERRUPTS],
  • c/src/lib/libbsp/powerpc/ep1a/console/alloc360.c

    r4598164 re36390a6  
    88 *  eric@skatter.usask.ca
    99 *
    10  *  COPYRIGHT (c) 1989-1999.
     10 *  COPYRIGHT (c) 2008.
    1111 *  On-Line Applications Research Corporation (OAR).
    1212 *
     
    2525#include <rtems/bspIo.h>
    2626
     27
     28#define DEBUG_PRINT 1
     29
    2730void M360SetupMemory( M68360_t ptr ){
    2831  volatile m360_t  *m360;
     
    3033  m360  = ptr->m360;
    3134
     35#if DEBUG_PRINT
     36printk("m360->mcr:0x%08x  Q1_360_SIM_MCR:0x%08x\n",
     37       (unsigned int)&(m360->mcr), ((unsigned int)m360+Q1_360_SIM_MCR));
     38#endif
    3239  ptr->bdregions[0].base = (char *)&m360->dpram1[0];
    3340  ptr->bdregions[0].size = sizeof m360->dpram1;
  • c/src/lib/libbsp/powerpc/ep1a/console/console.c

    r4598164 re36390a6  
    1 /*
     1/*XXX
    22 *  This file contains the TTY driver for the ep1a
    33 *
    44 *  This driver uses the termios pseudo driver.
    55 *
    6  *  COPYRIGHT (c) 1989-1999.
     6 *  COPYRIGHT (c) 2008.
    77 *  On-Line Applications Research Corporation (OAR).
    88 *
     
    242242  return RTEMS_SUCCESSFUL;
    243243}
     244#if 0
     245/* PAGE
     246 *
     247 *  DEBUG_puts
     248 *
     249 *  This should be safe in the event of an error.  It attempts to ensure
     250 *  that no TX empty interrupts occur while it is doing polled IO.  Then
     251 *  it restores the state of that external interrupt.
     252 *
     253 *  Input parameters:
     254 *    string  - pointer to debug output string
     255 *
     256 *  Output parameters:  NONE
     257 *
     258 *  Return values:      NONE
     259 */
     260
     261void DEBUG_puts(
     262        char *string
     263)
     264{
     265        char *s;
     266        unsigned32      Irql;
     267
     268        rtems_interrupt_disable(Irql);
     269
     270        for ( s = string ; *s ; s++ )
     271        {
     272                Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
     273                        deviceWritePolled(Console_Port_Minor, *s);
     274        }
     275
     276        rtems_interrupt_enable(Irql);
     277}
     278
     279/* PAGE
     280 *
     281 *  DEBUG_puth
     282 *
     283 *  This should be safe in the event of an error.  It attempts to ensure
     284 *  that no TX empty interrupts occur while it is doing polled IO.  Then
     285 *  it restores the state of that external interrupt.
     286 *
     287 *  Input parameters:
     288 *    ulHexNum - value to display
     289 *
     290 *  Output parameters:  NONE
     291 *
     292 *  Return values:      NONE
     293 */
     294void
     295DEBUG_puth(
     296    unsigned32 ulHexNum
     297    )
     298{
     299        unsigned long i,d;
     300        unsigned32 Irql;
     301
     302        rtems_interrupt_disable(Irql);
     303       
     304        Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
     305                deviceWritePolled(Console_Port_Minor, '0');
     306        Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
     307                deviceWritePolled(Console_Port_Minor, 'x');
     308
     309        for(i=32;i;)
     310        {
     311                i-=4;
     312                d=(ulHexNum>>i)&0xf;
     313                Console_Port_Tbl[Console_Port_Minor].pDeviceFns->
     314                        deviceWritePolled(Console_Port_Minor,
     315                                          (d<=9) ? d+'0' : d+'a'-0xa);
     316        }
     317
     318        rtems_interrupt_enable(Irql);
     319}
     320#endif
    244321
    245322/* const char arg to be compatible with BSP_output_char decl. */
  • c/src/lib/libbsp/powerpc/ep1a/console/console.h

    r4598164 re36390a6  
    1818 *
    1919 *
    20  *  COPYRIGHT (c) 1989-1999.
     20 *  COPYRIGHT (c) 1989-2008.
    2121 *  On-Line Applications Research Corporation (OAR).
    2222 *
     
    2626 *
    2727 *  $Id$
    28 */
     28 */
    2929
    3030#include <rtems/ringbuf.h>
  • c/src/lib/libbsp/powerpc/ep1a/console/m68360.h

    r4598164 re36390a6  
    4949
    5050#define M360_GSMR_RFW            0x00000020
     51
     52#define M360_GSMR_RINV           0x02000000
     53#define M360_GSMR_TINV           0x01000000
    5154#define M360_GSMR_TDCR_16X       0x00020000
    5255#define M360_GSMR_RDCR_16X       0x00008000
    53 #define M360_GSMR_MODE_UART      0x00000004
    5456#define M360_GSMR_DIAG_LLOOP     0x00000040
    5557#define M360_GSMR_ENR            0x00000020
    5658#define M360_GSMR_ENT            0x00000010
     59#define M360_GSMR_MODE_UART      0x00000004
    5760
    5861#define  M360_PSMR_FLC           0x8000
    59 #define  M360_PSMR_SL            0x4000
     62#define  M360_PSMR_SL_1          0x0000
     63#define  M360_PSMR_SL_2          0x4000
     64#define  M360_PSMR_CL5           0x0000
     65#define  M360_PSMR_CL6           0x1000
     66#define  M360_PSMR_CL7           0x2000
    6067#define  M360_PSMR_CL8           0x3000
    6168#define  M360_PSMR_UM_NORMAL     0x0000
     
    971978int mc68360_scc_create_chip( PPMCQ1BoardData BoardData, uint8_t int_vector );
    972979
     980#if 0
     981extern volatile m360_t *m360;
     982#endif
     983
    973984#endif /* __MC68360_h */
  • c/src/lib/libbsp/powerpc/ep1a/console/mc68360_scc.c

    r4598164 re36390a6  
    1 /*  This file contains the termios TTY driver for the Motorola MC68360 SCC ports.
    2  *
    3  *  COPYRIGHT (c) 1989-1999.
     1/*  This file contains the termios TTY driver for the
     2 *  Motorola MC68360 SCC ports.
     3 *
     4 *  COPYRIGHT (c) 1989-2008.
    45 *  On-Line Applications Research Corporation (OAR).
    56 *
     
    2324#include <stdlib.h>
    2425#include <rtems/bspIo.h>
    25 #include <rtems/termiostypes.h>
    2626#include <string.h>
    2727
    28 #define MC68360_LENGHT_SIZE 100
    29 int mc68360_length_array[ MC68360_LENGHT_SIZE ];
     28#if 0
     29#define DEBUG_360
     30#endif
     31
     32#if 1   /* XXX */
     33int EP1A_READ_LENGTH_GREATER_THAN_1 = 0;
     34
     35#define MC68360_LENGTH_SIZE 400
     36int mc68360_length_array[ MC68360_LENGTH_SIZE ];
    3037int mc68360_length_count=0;
    3138
    3239void mc68360_Show_length_array(void) {
    3340  int i;
    34   for (i=0; i<MC68360_LENGHT_SIZE; i++)
     41  for (i=0; i<MC68360_LENGTH_SIZE; i++)
    3542    printf(" %d", mc68360_length_array[i] );
    3643  printf("\n\n");
    3744}
     45#endif
     46
    3847
    3948M68360_t    M68360_chips = NULL;
    4049
    4150#define SYNC     eieio
     51#define mc68360_scc_Is_422( _minor ) (Console_Port_Tbl[minor].sDeviceName[7] == '4' )
     52
    4253
    4354void mc68360_scc_nullFunc(void) {}
     
    172183{
    173184   int data;
     185#if 0
     186   int divisor;
     187   int div16;
     188
     189   div16 = 0;
     190   divisor = ((m360_clock_rate / 16) + (baud / 2)) / baud;
     191   if (divisor > 4096)
     192   {
     193      div16   = 1;
     194      divisor = (divisor + 8) / 16;
     195   }
     196   return(M360_BRG_EN | M360_BRG_EXTC_BRGCLK |
     197          ((divisor - 1) << 1) | div16);
     198#endif
    174199
    175200  /*
     
    215240 *                                                                        *
    216241 **************************************************************************/
    217 void mc68360_sccInterruptHandler( rtems_irq_hdl_param handle )
     242void mc68360_sccInterruptHandler( M68360_t chip )
    218243{
    219244  volatile m360_t    *m360;
     
    224249  char               data;
    225250  int                clear_isr;
    226   M68360_t           chip = (M68360_t)handle;
    227 
     251
     252
     253#ifdef DEBUG_360
     254  printk("mc68360_sccInterruptHandler\n");
     255#endif
    228256  for (port=0; port<4; port++) {
    229257
    230258      clear_isr = FALSE;
    231259      m360  = chip->m360;
     260
     261      /*
     262       * XXX - Can we add something here to check if this is our interrupt.
     263       * XXX - We need a parameter here so that we know which 360 instead of
     264       *       looping through them all!
     265       */
    232266
    233267      /*
     
    242276        {
    243277           length= scc_read16("sccRxBd->length",&chip->port[port].sccRxBd->length);
     278if (length > 1)
     279  EP1A_READ_LENGTH_GREATER_THAN_1 = length;
     280
    244281           for (i=0;i<length;i++) {
    245282             data= chip->port[port].rxBuf[i];
     
    266303        {
    267304           scc_write16("sccTxBd->status",&chip->port[port].sccTxBd->status,0);
     305#if 1
    268306           rtems_termios_dequeue_characters(
    269307             Console_Port_Data[chip->port[port].minor].termios_data,
    270308             chip->port[port].sccTxBd->length);
     309#else
     310           mc68360_scc_write_support_int(chip->port[port].minor,"*****", 5);
     311#endif
    271312        }
    272313      }
     
    294335)
    295336{
     337  M68360_serial_ports_t  ptr;
     338  volatile m360_t       *m360;
     339  uint32_t               data;
     340
     341#ifdef DEBUG_360
     342  printk("mc68360_scc_open %d\n", minor);
     343#endif
     344
     345
     346  ptr   = Console_Port_Tbl[minor].pDeviceParams;
     347  m360  = ptr->chip->m360;
     348
     349  /*
     350   * Enable the receiver and the transmitter.
     351   */
     352
     353  SYNC();
     354  data = scc_read32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l);
     355  scc_write32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l,
     356    (data | M360_GSMR_ENR | M360_GSMR_ENT) );
     357
     358  data  = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK );
     359  data &= (~PMCQ1_INT_MASK_QUICC);
     360  PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK, data );
     361
     362  data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS );
     363  data &= (~PMCQ1_INT_STATUS_QUICC);
     364  PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS, data );
    296365
    297366  return RTEMS_SUCCESSFUL;
     367}
     368
     369uint32_t mc68360_scc_calculate_pbdat( M68360_t chip )
     370{
     371  uint32_t               i;
     372  uint32_t               pbdat_data;
     373  int                    minor;
     374  uint32_t               type422data[4] = {
     375    0x00440,  0x00880,  0x10100,  0x20200
     376  };
     377
     378  pbdat_data = 0x3;
     379  for (i=0; i<4; i++) {
     380    minor = chip->port[i].minor;
     381    if mc68360_scc_Is_422( minor )
     382      pbdat_data |= type422data[i];
     383  }
     384
     385  return pbdat_data;
    298386}
    299387
     
    321409  ptr   = Console_Port_Tbl[minor].pDeviceParams;
    322410  m360  = ptr->chip->m360;
     411 
    323412#ifdef DEBUG_360
    324413  printk("m360 0x%08x baseaddr 0x%08x\n",
     
    338427  data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_DRIVER_ENABLE );
    339428  SYNC();
    340   data |= (PMCQ1_DRIVER_ENABLE_3 | PMCQ1_DRIVER_ENABLE_2 |
    341            PMCQ1_DRIVER_ENABLE_1 | PMCQ1_DRIVER_ENABLE_0);
     429  data = data & ~(PMCQ1_DRIVER_ENABLE_3 | PMCQ1_DRIVER_ENABLE_2 |
     430                  PMCQ1_DRIVER_ENABLE_1 | PMCQ1_DRIVER_ENABLE_0);
    342431  PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_DRIVER_ENABLE, data);
    343432  data = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_DRIVER_ENABLE );
     
    384473   * XXX
    385474   */
     475
     476#if 0
    386477  scc_write32( "pbpar", &m360->pbpar, 0x00000000 );
    387478  scc_write32( "pbdir", &m360->pbdir, 0x0003ffff );
    388479  scc_write32( "pbdat", &m360->pbdat, 0x0000003f );
    389480  SYNC();
     481#else
     482  data = mc68360_scc_calculate_pbdat( ptr->chip );
     483  scc_write32( "pbpar", &m360->pbpar, 0x00000000 );
     484  scc_write32( "pbdat", &m360->pbdat, data );
     485  SYNC();
     486  scc_write32( "pbdir", &m360->pbdir, 0x0003fc3 );
     487  SYNC();
     488#endif
     489
    390490
    391491  /*
     
    530630  SYNC();
    531631
     632#if 0          /* XXX - ??? */
    532633  /*
    533634   * Enable the receiver and the transmitter.
     
    537638  data = scc_read32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l);
    538639  scc_write32( "pSCCR->gsmr_l", &ptr->pSCCR->gsmr_l,
    539                (data | M360_GSMR_ENR | M360_GSMR_ENT) );
     640    (data | M360_GSMR_ENR | M360_GSMR_ENT) );
    540641
    541642  data  = PMCQ1_Read_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_MASK );
     
    546647  data &= (~PMCQ1_INT_STATUS_QUICC);
    547648  PMCQ1_Write_EPLD(ptr->chip->board_data->baseaddr, PMCQ1_INT_STATUS, data );
     649#endif
    548650}
    549651
     
    563665  M68360_serial_ports_t  ptr;
    564666
     667#if 1
    565668  mc68360_length_array[ mc68360_length_count ] = len;
    566669  mc68360_length_count++;
    567   if ( mc68360_length_count >= MC68360_LENGHT_SIZE )
     670  if ( mc68360_length_count >= MC68360_LENGTH_SIZE )
    568671    mc68360_length_count=0;
     672#endif
    569673
    570674  ptr   = Console_Port_Tbl[minor].pDeviceParams;
     
    635739   volatile m360_t        *m360;
    636740   M68360_serial_ports_t  ptr;
     741   uint16_t               value;
     742
     743#ifdef DEBUG_360
     744printk("mc68360_scc_set_attributes\n");
     745#endif
    637746
    638747   ptr   = Console_Port_Tbl[minor].pDeviceParams;
    639748   m360  = ptr->chip->m360;
    640749
    641   baud = termios_baud_to_number(t->c_cflag & CBAUD);
    642    if (baud > 0) {
     750   switch (t->c_cflag & CBAUD)
     751   {
     752      case B50:      baud = 50;      break;
     753      case B75:      baud = 75;      break;
     754      case B110:     baud = 110;     break;
     755      case B134:     baud = 134;     break;
     756      case B150:     baud = 150;     break;
     757      case B200:     baud = 200;     break;
     758      case B300:     baud = 300;     break;
     759      case B600:     baud = 600;     break;
     760      case B1200:    baud = 1200;    break;
     761      case B1800:    baud = 1800;    break;
     762      case B2400:    baud = 2400;    break;
     763      case B4800:    baud = 4800;    break;
     764      case B9600:    baud = 9600;    break;
     765      case B19200:   baud = 19200;   break;
     766      case B38400:   baud = 38400;   break;
     767      case B57600:   baud = 57600;   break;
     768      case B115200:  baud = 115200;  break;
     769      case B230400:  baud = 230400;  break;
     770      case B460800:  baud = 460800;  break;
     771      default:       baud = -1;      break;
     772   }
     773
     774   if (baud > 0)
     775   {
    643776      scc_write32(
    644777        "pBRGC",
     
    647780      );
    648781   }
     782
     783  /* Initial value of PSMR should be 0 */
     784  value = M360_PSMR_UM_NORMAL;
     785
     786  /* set the number of data bits, 8 is most common */
     787  if (t->c_cflag & CSIZE)                     /* was it specified? */
     788  {
     789    switch (t->c_cflag & CSIZE) {
     790      case CS5: value |= M360_PSMR_CL5; break;
     791      case CS6: value |= M360_PSMR_CL6; break;
     792      case CS7: value |= M360_PSMR_CL7; break;
     793      case CS8: value |= M360_PSMR_CL8; break;
     794    }
     795  } else {
     796    value |= M360_PSMR_CL8;         /* default to 8 data bits */
     797  }
     798
     799  /* the number of stop bits */
     800  if (t->c_cflag & CSTOPB)
     801    value |= M360_PSMR_SL_2;   /* Two stop bits */
     802  else
     803    value |= M360_PSMR_SL_1;   /* One stop bit  */
     804
     805  /* Set Parity M360_PSMR_PEN bit should be clear on no parity so
     806   * do nothing in that case
     807   */
     808  if (t->c_cflag & PARENB)                /* enable parity detection? */
     809  {
     810    value |= M360_PSMR_PEN;               
     811    if (t->c_cflag & PARODD){
     812      value |= M360_PSMR_RPM_ODD;        /* select odd parity */
     813      value |= M360_PSMR_TPM_ODD;
     814    } else {
     815      value |= M360_PSMR_RPM_EVEN;       /* select even parity */
     816      value |= M360_PSMR_TPM_EVEN;
     817    }
     818  }
     819
     820  SYNC();
     821  scc_write16( "pSCCR->psmr", &ptr->pSCCR->psmr, value );
     822  SYNC();
    649823
    650824  return 0;
  • c/src/lib/libbsp/powerpc/ep1a/console/ns16550cfg.c

    r4598164 re36390a6  
    1 /*
     1/* 
    22 *  This include file contains all console driver definations for the nc16550
    33 *
     
    2727)
    2828{
    29   struct uart_reg *p = (struct uart_reg *)ulCtrlPort;
     29volatile struct uart_reg *p = (volatile struct uart_reg *)ulCtrlPort;
    3030  uint8_t  ucData;
    3131  ucData = p[ucRegNum].reg;
     
    4040)
    4141{
    42   struct uart_reg *p = (struct uart_reg *)ulCtrlPort;
     42  volatile struct uart_reg *p = (volatile struct uart_reg *)ulCtrlPort;
    4343  volatile int i;
    4444  p[ucRegNum].reg = ucData;
    4545  asm volatile("sync");
    46   for (i=0;i<0x08ff;i++);
     46  asm volatile("isync");
     47  asm volatile("eieio");
     48  for (i=0;i<0x08ff;i++)
     49    asm volatile("isync");
    4750}
  • c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.c

    r4598164 re36390a6  
    4242
    4343/* defines */
    44 #if 0
     44#if 1
    4545#define DEBUG_360
    4646#endif
     
    116116void rsPMCQ1Int( void *ptr )
    117117{
    118   unsigned long status;
    119   unsigned long status1;
    120   unsigned long mask;
     118  unsigned long   status;
     119  unsigned long   status1;
     120  unsigned long   mask;
     121  uint32_t        data;
    121122  PPMCQ1BoardData boardData = ptr;
    122123
     
    130131      boardData->quiccInt(boardData->quiccArg);
    131132    } else {
    132       *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
     133      *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_QUICC;
    133134    }
    134135  }
     
    139140    if (boardData->maInt) {
    140141      boardData->maInt(boardData->maArg);
     142
     143      data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
     144      data &= (~PMCQ1_INT_STATUS_MA);
     145      PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data );
     146
    141147    } else {
    142      *(unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
    143     }
    144   }
     148     *(volatile unsigned long *)(boardData->baseaddr + PMCQ1_INT_MASK) |= PMCQ1_INT_MASK_MA;
     149    }
     150  }
     151
     152  RTEMS_COMPILER_MEMORY_BARRIER();
    145153
    146154  /* Clear Interrupt on QSPAN */
    147   *(unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000;
     155  *(volatile unsigned long *)(boardData->bridgeaddr + 0x600) = 0x00001000;
    148156
    149157  /* read back the status register to ensure that the pci write has completed */
    150158  status1 = *(volatile unsigned long *)(boardData->bridgeaddr + 0x600);
     159  RTEMS_COMPILER_MEMORY_BARRIER();
     160
    151161}
    152162
     
    166176    unsigned long       slotNo, /* Pci Slot number of PMCQ1 */
    167177    unsigned long       funcNo, /* Pci Function number of PMCQ1 */
    168     rtems_irq_hdl       routine,/* interrupt routine */
    169     rtems_irq_hdl_param arg     /* argument to pass to interrupt routine */
     178    FUNCION_PTR routine,/* interrupt routine */
     179    int         arg     /* argument to pass to interrupt routine */
    170180)
    171181{
    172182  PPMCQ1BoardData boardData;
    173   unsigned int status = RTEMS_IO_ERROR;
     183  uint32_t        data;
     184  unsigned int    status = RTEMS_IO_ERROR;
    174185
    175186  for (boardData = pmcq1BoardData; boardData; boardData = boardData->pNext)
     
    180191      boardData->maInt = routine;
    181192      boardData->maArg = arg;
     193
     194      data  = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_MASK );
     195      data &= (~PMCQ1_INT_MASK_MA);
     196      PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_MASK, data );
     197
     198      data = PMCQ1_Read_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS );
     199      data &= (~PMCQ1_INT_STATUS_MA);
     200      PMCQ1_Write_EPLD(boardData->baseaddr, PMCQ1_INT_STATUS, data );
     201
    182202      status = RTEMS_SUCCESSFUL;
    183203      break;
     
    235255    unsigned long       slotNo, /* Pci Slot number of PMCQ1 */
    236256    unsigned long       funcNo, /* Pci Function number of PMCQ1 */
    237     rtems_irq_hdl       routine,/* interrupt routine */
    238     rtems_irq_hdl_param arg     /* argument to pass to interrupt routine */
     257    FUNCION_PTR routine,/* interrupt routine */
     258    int         arg     /* argument to pass to interrupt routine */
    239259)
    240260{
     
    304324  int busNo;
    305325  int slotNo;
    306   uint32_t baseaddr = 0;
    307   uint32_t bridgeaddr = 0;
     326  unsigned int baseaddr = 0;
     327  unsigned int bridgeaddr = 0;
    308328  unsigned long pbti0_ctl;
    309329  int i;
    310330  unsigned char int_vector;
    311331  int fun;
    312   uint32_t temp;
     332  int temp;
    313333  PPMCQ1BoardData       boardData;
    314334  rtems_irq_connect_data IrqData = {0,
    315335                                    rsPMCQ1Int,
    316                                     NULL,
    317                                     (rtems_irq_enable)rsPMCQ1_scc_nullFunc,
    318                                     (rtems_irq_disable)rsPMCQ1_scc_nullFunc,
    319                                     (rtems_irq_is_enabled)rsPMCQ1_scc_nullFunc,
     336                                    rsPMCQ1_scc_nullFunc,
     337                                    rsPMCQ1_scc_nullFunc,
     338                                    rsPMCQ1_scc_nullFunc,
    320339                                    NULL};
    321340
     
    437456    printk("PMCQ1 int_vector %d\n", int_vector);
    438457#endif
    439     IrqData.name  = (rtems_irq_number)((unsigned int)BSP_PCI_IRQ0 + int_vector);
     458    IrqData.name  = ((unsigned int)BSP_PCI_IRQ0 + int_vector);
    440459    IrqData.handle = boardData;
    441460    if (!BSP_install_rtems_shared_irq_handler (&IrqData)) {
     
    475494{
    476495  unsigned int status = RTEMS_IO_ERROR;
    477   uint32_t bridgeaddr = 0;
     496  uint32_t     bridgeaddr = 0;
    478497  unsigned long val;
    479498  int i;
  • c/src/lib/libbsp/powerpc/ep1a/console/rsPMCQ1.h

    r4598164 re36390a6  
    2222 */
    2323
     24#include <libcpu/io.h>
     25#include <bsp/irq.h>
     26
    2427/*
    2528   modification history
     
    3033#ifndef __INCPMCQ1H
    3134#define __INCPMCQ1H
    32 
    33 #include <libcpu/io.h>
    34 #include <bsp/irq.h>
    3535
    3636/*
     
    9797
    9898/*
    99 #define PMCQ1_Read_EPLD( _base, _reg ) ( *((unsigned long *) ((uint32_t)_base + _reg)) )
    100 #define PMCQ1_Write_EPLD( _base, _reg, _data ) *((unsigned long *) ((uint32_t)_base + _reg)) = _data
     99#define PMCQ1_Read_EPLD( _base, _reg ) ( *((unsigned long *) ((unsigned32)_base + _reg)) )
     100#define PMCQ1_Write_EPLD( _base, _reg, _data ) *((unsigned long *) ((unsigned32)_base + _reg)) = _data
    101101*/
    102102uint32_t PMCQ1_Read_EPLD( uint32_t base, uint32_t reg );
     
    109109#define QSPAN2_INT_STATUS       0x00000600
    110110
     111typedef void (*FUNCION_PTR) (int);
    111112
    112113#define PCI_ID(v, d) ((d << 16) | v)
     
    131132    unsigned long                       baseaddr;
    132133    unsigned long                       bridgeaddr;
    133     rtems_irq_hdl                       quiccInt;
    134     rtems_irq_hdl_param                 quiccArg;
    135     rtems_irq_hdl                       maInt;
    136     rtems_irq_hdl_param                 maArg;
     134    FUNCION_PTR                         quiccInt;
     135    int                                 quiccArg;
     136    FUNCION_PTR                         maInt;
     137    int                                 maArg;
    137138} PMCQ1BoardData, *PPMCQ1BoardData;
    138139
     
    142143 * Function declarations
    143144 */
    144 extern unsigned int rsPMCQ1QuiccIntConnect(
    145   unsigned long busNo, unsigned long slotNo,unsigned long funcNo, rtems_irq_hdl routine,rtems_irq_hdl_param arg );
    146 extern unsigned int rsPMCQ1Init(void);
     145extern unsigned int rsPMCQ1QuiccIntConnect(
     146  unsigned long         busNo,
     147  unsigned long         slotNo,
     148  unsigned long         funcNo,
     149  FUNCION_PTR           routine,
     150  int                   arg
     151);
     152unsigned int rsPMCQ1Init();
     153unsigned int rsPMCQ1MaIntConnect (
     154    unsigned long       busNo,  /* Pci Bus number of PMCQ1 */
     155    unsigned long       slotNo, /* Pci Slot number of PMCQ1 */
     156    unsigned long       funcNo, /* Pci Function number of PMCQ1 */
     157    FUNCION_PTR         routine,/* interrupt routine */
     158    int                 arg     /* argument to pass to interrupt routine */
     159);
    147160
    148161#endif                          /* __INCPMCQ1H */
  • c/src/lib/libbsp/powerpc/ep1a/include/bsp.h

    r4598164 re36390a6  
    3737#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
    3838#define PCI_MEM_BASE            0x80000000
    39 #define PCI_MEM_BASE_ADJUSTMENT 0
    40 
     39#define PCI_MEM_BASE_ADJUSTMENT 0
    4140/* address of our ram on the PCI bus   */
    4241#define PCI_DRAM_OFFSET         CHRP_PCI_DRAM_OFFSET
    4342
    4443/* offset of pci memory as seen from the CPU */
     44#undef  PCI_MEM_BASE
    4545#define PCI_MEM_BASE            0x00000000 
    4646
  • c/src/lib/libbsp/powerpc/ep1a/irq/irq_init.c

    r4598164 re36390a6  
    3636#define SHOW_ISA_PCI_BRIDGE_SETTINGS
    3737*/
     38#define TRACE_IRQ_INIT
    3839
    3940/*
     
    185186    initial_config.irqPrioTbl   = irqPrioTable;
    186187
     188printk("Call BSP_rtems_irq_mngt_set\n");
    187189    if (!BSP_rtems_irq_mngt_set(&initial_config)) {
    188190      /*
  • c/src/lib/libbsp/powerpc/ep1a/vme/VMEConfig.h

    r4598164 re36390a6  
    6464#undef   BSP_VME_BAT_IDX
    6565
    66 #define _VME_A32_WIN0_ON_PCI    0x10000000
    67 #define _VME_A24_ON_PCI                 0x1f000000
    68 #define _VME_A16_ON_PCI                 0x1fff0000
     66#define _VME_A32_WIN0_ON_PCI    0x90000000
     67#define _VME_A24_ON_PCI         0x9f000000
     68#define _VME_A16_ON_PCI         0x9fff0000
    6969
    7070/* start of the A32 window on the VME bus
     
    7878 */
    7979#undef  _VME_DRAM_OFFSET
     80#define _VME_DRAM_OFFSET                0xc0000000 
     81#define _VME_DRAM_32_OFFSET1            0x20000000
     82#define _VME_DRAM_32_OFFSET2            0x20b00000
     83#define _VME_DRAM_24_OFFSET1            0x00000000
     84#define _VME_DRAM_24_OFFSET2            0x00100000
     85#define _VME_DRAM_16_OFFSET1            0x00000000
     86#define _VME_DRAM_16_OFFSET2            0x00008000
     87
     88#define _VME_A24_SIZE                   0x00100000
     89#define _VME_A16_SIZE                   0x00008000
    8090
    8191#undef _VME_CSR_ON_PCI
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