Changeset e35c696 in rtems
- Timestamp:
- Aug 10, 2007, 8:15:58 AM (14 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 267c7c5
- Parents:
- 38630e98
- Files:
-
- 3 added
- 11 edited
Legend:
- Unmodified
- Added
- Removed
-
README.configure
r38630e98 re35c696 203 203 mvme5500 ep1a pm520_cr825 pm520_ze30 gen405 helas403 204 204 mbx821_001 mbx821_002 mbx821_002b mbx860_001b 205 mbx860_002 mbx860_005b mtx603e brs5l gen5200 ep5200 206 virtex gen83xx mpc8349eamds 205 207 mbx860_002 mbx860_005b mtx603e brs5l gen5200 icecube 206 virtex gen83xx mpc8349eamds 208 virtex gen83xx mpc8349eamds hsc_cm01 207 209 208 210 NOTE: The "motorola_powerpc" BSP is a single BSP which -
aclocal/bsp-alias.m4
r38630e98 re35c696 28 28 icecube) $2=gen5200 ;; # MPC5200 based board - LITE5200B 29 29 mpc8349eamds) $2=gen83xx ;; # MPC8349 based board 30 hsc_cm01) $2=gen83xx ;; # MPC8349 based board 30 31 simcpu32) $2=sim68000 ;; # BSVC CPU32 variant 31 32 simsh7032) $2=shsim ;; # SH7032 simulator -
aclocal/check-bsps.m4
r38630e98 re35c696 27 27 ;; 28 28 gen5200) bsps="pm520_cr825 pm520_ze30 brs5l";; 29 gen83xx) bsps="mpc8349eamds ";;29 gen83xx) bsps="mpc8349eamds hsc_cm01";; 30 30 motorola_powerpc) bsps="mvme2307 mcp750 mtx603e mvme2100";; 31 31 pc386) bsps="pc386 pc386dx pc486 pc586 pc686 pck6";; -
c/src/lib/libbsp/powerpc/gen83xx/ChangeLog
r38630e98 re35c696 1 2007-08-08 Thomas Doerfler <Thomas.Doerfler@embedded-brains.de> 2 3 * Makefile.am, i2c/i2c_init.c: add i2c initialization 4 1 5 2007-07-13 Joel Sherrill <joel.sherrill@OARcorp.com> 2 6 -
c/src/lib/libbsp/powerpc/gen83xx/Makefile.am
r38630e98 re35c696 34 34 project_lib_DATA += rtems_crti.$(OBJEXT) 35 35 36 dist_project_lib_DATA += startup/linkcmds startup/linkcmds.mpc8349eamds 36 dist_project_lib_DATA += startup/linkcmds \ 37 startup/linkcmds.mpc8349eamds \ 38 startup/linkcmds.hsc_cm01 37 39 38 40 noinst_PROGRAMS += mpc83xx_regs.rel … … 86 88 network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) 87 89 90 noinst_PROGRAMS += bsp_i2c.rel 91 bsp_i2c_rel_SOURCES = i2c/i2c_init.c 92 bsp_i2c_rel_CPPFLAGS = $(AM_CPPFLAGS) 93 bsp_i2c_rel_LDFLAGS = $(RTEMS_RELLDFLAGS) 94 88 95 noinst_LIBRARIES = libbsp.a 89 96 libbsp_a_SOURCES = 90 97 libbsp_a_LIBADD = startup.rel pclock.rel console.rel \ 91 98 vectors.rel irq.rel mpc83xx_regs.rel 92 libbsp_a_LIBADD += network.rel 99 libbsp_a_LIBADD += network.rel bsp_i2c.rel 93 100 libbsp_a_LIBADD += ../../../libcpu/@RTEMS_CPU@/shared/cpuIdent.rel \ 94 101 ../../../libcpu/@RTEMS_CPU@/shared/cache.rel \ … … 100 107 ../../../libcpu/@RTEMS_CPU@/mpc6xx/mmu.rel \ 101 108 ../../../libcpu/@RTEMS_CPU@/mpc6xx/timer.rel \ 102 ../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel 109 ../../../libcpu/@RTEMS_CPU@/mpc83xx/tsec.rel \ 110 ../../../libcpu/@RTEMS_CPU@/mpc83xx/i2c.rel 103 111 104 112 EXTRA_DIST += README.mpc8349eamds -
c/src/lib/libbsp/powerpc/gen83xx/include/bsp.h
r38630e98 re35c696 42 42 43 43 /* 44 * Reset configuration words 45 */ 46 #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ 47 RCWLR_DDRCM_1_1 | \ 48 RCWLR_SPMF(4) | \ 49 RCWLR_COREPLL(4)) 50 51 #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ 52 RCWHR_PCI_32 | \ 53 RCWHR_PCI1ARB_EN | \ 54 RCWHR_PCI2ARB_EN | \ 55 RCWHR_CORE_EN | \ 56 RCWHR_BMS_LOW | \ 57 RCWHR_BOOTSEQ_NONE | \ 58 RCWHR_SW_DIS | \ 59 RCWHR_ROMLOC_LB16 | \ 60 RCWHR_TSEC1M_GMII | \ 61 RCWHR_TSEC2M_GMII | \ 62 RCWHR_ENDIAN_BIG | \ 63 RCWHR_LALE_NORM | \ 64 RCWHR_LDP_PAR) 65 /* 66 * for JPK HSC_CM01 67 */ 68 #elsif defined(HSC_CM01) 69 /* 70 * one DUART channel (UART1) supported 71 */ 72 #define GEN83xx_DUART_AVAIL_MASK 0x01 73 74 /* we need the low level initialization in start.S*/ 75 #define NEED_LOW_LEVEL_INIT 76 /* 77 * clocking infos 78 */ 79 #define BSP_CLKIN_FRQ 66000000L 80 #define BSP_SYSPLL_MF 4 /* FIXME: derive from clock register */ 81 82 /* 83 * Reset configuration words 84 */ 85 #define RESET_CONF_WRD_L (RCWLR_LBIUCM_1_1 | \ 86 RCWLR_DDRCM_1_1 | \ 87 RCWLR_SPMF(4) | \ 88 RCWLR_COREPLL(4)) 89 90 #define RESET_CONF_WRD_H (RCWHR_PCI_HOST | \ 91 RCWHR_PCI_32 | \ 92 RCWHR_PCI1ARB_EN | \ 93 RCWHR_PCI2ARB_EN | \ 94 RCWHR_CORE_EN | \ 95 RCWHR_BMS_LOW | \ 96 RCWHR_BOOTSEQ_NONE | \ 97 RCWHR_SW_DIS | \ 98 RCWHR_ROMLOC_LB16 | \ 99 RCWHR_TSEC1M_RGMII | \ 100 RCWHR_TSEC2M_GMII | \ 101 RCWHR_ENDIAN_BIG | \ 102 RCWHR_LALE_NORM | \ 103 RCWHR_LDP_PAR) 104 #else 105 #error "board type not defined" 106 #endif 107 108 /* 109 * for JPK HSC_CM01 and freescale MPC8349EAMDS 110 */ 111 #if defined(MPC8349EAMDS) || defined(HSC_CM01) 112 /* 44 113 * address range definitions 45 114 */ 46 /* ROM definitions ( 2 MB) */47 #define ROM_START 0xF FE0000048 #define ROM_SIZE 0x0 0200000115 /* ROM definitions (8 MB, mirrored multiple times) */ 116 #define ROM_START 0xFE000000 117 #define ROM_SIZE 0x02000000 49 118 #define ROM_END (ROM_START+ROM_SIZE-1) 50 119 #define BOOT_START ROM_START … … 55 124 #define RAM_SIZE 0x10000000 56 125 #define RAM_END (RAM_START+RAM_SIZE-1) 126 57 127 58 128 /* working internal memory map base address */ … … 126 196 #include <bsp/vectors.h> 127 197 128 /*129 * Network driver configuration130 */131 struct rtems_bsdnet_ifconfig;132 extern int rtems_mpc83xx_tsec_driver_attach_detach (struct rtems_bsdnet_ifconfig *config, int attaching);133 #define RTEMS_BSP_NETWORK_DRIVER_NAME "tsec1"134 #define RTEMS_BSP_NETWORK_DRIVER_ATTACH rtems_mpc83xx_tsec_driver_attach_detach135 136 198 /* miscellaneous stuff assumed to exist */ 137 199 … … 177 239 178 240 void bsp_cleanup(void); 241 rtems_status_code bsp_register_i2c(void); 179 242 180 243 /* console modes (only termios) */ … … 212 275 #define RTEMS_BSP_NETWORK_DRIVER_NAME2 "tsec2" 213 276 277 /* 278 * i2c EEPROM device name 279 */ 280 #define RTEMS_BSP_I2C_EEPROM_DEVICE_NAME "eeprom" 281 #define RTEMS_BSP_I2C_EEPROM_DEVICE_PATH "/dev/i2c1.eeprom" 282 214 283 #ifdef __cplusplus 215 284 } -
c/src/lib/libbsp/powerpc/gen83xx/preinstall.am
r38630e98 re35c696 74 74 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc8349eamds 75 75 76 $(PROJECT_LIB)/linkcmds.hsc_cm01: startup/linkcmds.hsc_cm01 $(PROJECT_LIB)/$(dirstamp) 77 $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.hsc_cm01 78 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.hsc_cm01 79 76 80 $(PROJECT_INCLUDE)/bsp/irq.h: ./irq/irq.h $(PROJECT_INCLUDE)/bsp/$(dirstamp) 77 81 $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/irq.h -
c/src/lib/libbsp/powerpc/gen83xx/start/start.S
r38630e98 re35c696 74 74 .endm 75 75 76 #define REP8(l) l ; l; l; l; l; l; l; l; 77 76 78 .extern _bss_start 77 79 .extern _bss_size … … 84 86 .extern MBAR 85 87 86 .section ".vectors" 88 .section ".resconf","ax" 89 PUBLIC_VAR (reset_conf_words) 90 reset_conf_words: 91 REP8( .byte ((RESET_CONF_WRD_L >> 24) & 0xff)) 92 REP8( .byte ((RESET_CONF_WRD_L >> 16) & 0xff)) 93 REP8( .byte ((RESET_CONF_WRD_L >> 8) & 0xff)) 94 REP8( .byte ((RESET_CONF_WRD_L >> 0) & 0xff)) 95 96 REP8( .byte ((RESET_CONF_WRD_H >> 24) & 0xff)) 97 REP8( .byte ((RESET_CONF_WRD_H >> 16) & 0xff)) 98 REP8( .byte ((RESET_CONF_WRD_H >> 8) & 0xff)) 99 REP8( .byte ((RESET_CONF_WRD_H >> 0) & 0xff)) 100 101 .section ".vectors","ax" 87 102 PUBLIC_VAR (reset_vec) 88 103 reset_vec: 89 bl start 104 bl rom_entry 105 90 106 .section ".entry" 91 107 PUBLIC_VAR (start) 92 108 start: 93 109 /* 94 * FIXME:basic CPU setup:95 * 110 * basic CPU setup: 111 * init MSR 96 112 */ 97 113 mfmsr r30 … … 99 115 CLRBITS r30, r29, MSR_IP|MSR_EE 100 116 mtmsr r30 /* Set RI/ME, Clr EE in MSR */ 101 /* 102 * check, wether we are starting from ROM 103 * detect this using the absolute code address: 104 * when the upper 4 bits are 0xF, then we are in ROM 105 */ 106 bl 1f 107 1: mflr r28 108 LWI r29,0xF0000000 109 TSTBITS r28,r29,r30,0xF0000000 110 bne start_rom_skip 117 b start_rom_skip 118 119 PUBLIC_VAR (rom_entry) 120 rom_entry: 121 /* 122 * basic CPU setup: 123 * init MSR 124 */ 125 mfmsr r30 126 SETBITS r30, r29, MSR_ME|MSR_RI 127 CLRBITS r30, r29, MSR_IP|MSR_EE 128 mtmsr r30 /* Set RI/ME, Clr EE in MSR */ 129 111 130 /* 112 131 * ROM startup: remap IMMR to 0xE0000000 … … 117 136 lwz r29,0(r30) 118 137 stw r31,0(r30) 138 #if 0 119 139 lwz r29,0(r28) /* read from ROM... */ 140 #endif 120 141 isync 121 142 lwz r29,0(r31) /* read from IMMRBAR... */ … … 123 144 /* 124 145 * NOTE: now r31 points to onchip registers 125 126 /* 127 * ROM startup: init local access windows 128 */ 146 */ 147 /* 148 * FIXME: 149 * we start from 0x100, so ROM is currently mapped to 150 * 0x00000000.. 151 * in the next step, ROM will be remapped to its final location 152 * at 0xfe000000... (using LBLAWBAR1 with LBLAWBAR0 value) 153 * and we jump to that location. 154 * then we remove the ROM mapping to zero 155 */ 156 #ifdef LBLAWBAR0_VAL 157 SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR0_VAL 158 #endif 159 #ifdef LBLAWAR0_VAL 160 SET_IMM_REGW r31,r30,LBLAWAR1_OFF,LBLAWAR0_VAL 161 #endif 162 163 164 /* 165 * ROM startup: jump to code final ROM location 166 */ 167 LA r20, ROM_START /* ROM-RAM reloc in r20 */ 168 LA r29, start_code_in_rom /* get compile time addr of label */ 169 add r29,r20,r29 /* compute exec address */ 170 mtlr r29 171 blr /* now further execution in upper ROM */ 172 173 start_code_in_rom: 174 129 175 #ifdef LBLAWBAR0_VAL 130 176 SET_IMM_REGW r31,r30,LBLAWBAR0_OFF,LBLAWBAR0_VAL … … 132 178 #ifdef LBLAWAR0_VAL 133 179 SET_IMM_REGW r31,r30,LBLAWAR0_OFF,LBLAWAR0_VAL 134 #endif 180 #endif 135 181 #ifdef LBLAWBAR1_VAL 136 182 SET_IMM_REGW r31,r30,LBLAWBAR1_OFF,LBLAWBAR1_VAL … … 276 322 LA r28, _data_size /* get size of RAM image */ 277 323 bl copy_image /* copy initialized data section from ROM to RAM location */ 324 /* 325 * ROM startup: jump to code copy in SDRAM 326 */ 327 LA r29, start_code_in_ram /* get compile time address of label */ 328 mtlr r29 329 blr /* now further execution RAM */ 330 331 start_code_in_ram: 332 278 333 start_rom_skip: 279 334 /* 280 * ROM startup: clear bss in SDRAM335 * ROM/RAM startup: clear bss in SDRAM 281 336 */ 282 337 LWI r30, _bss_start /* get start address of bss section */ 283 338 LWI r29, _bss_size /* get size of bss section */ 284 339 bl clr_mem /* Clear the bss section */ 285 /*286 * ROM startup: jump to code copy in SDRAM287 */288 LA r29, start_code_in_ram /* get compile time address of label */289 mtlr r29290 blr /* now further execution RAM */291 start_code_in_ram:292 340 /* 293 341 * call boot_card -
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds
r38630e98 re35c696 46 46 *mpc83xx_regs*(*) 47 47 } > mpc83xx_regs 48 49 .resconf 0x000 : 50 { 51 *(.resconf) 52 } > ram 48 53 49 54 .vectors 0x100 : -
c/src/lib/libbsp/powerpc/gen83xx/startup/linkcmds.mpc8349eamds
r38630e98 re35c696 43 43 *mpc83xx_regs*(*) 44 44 } > mpc83xx_regs 45 46 .resconf 0x000 : 47 { 48 *(.resconf) 49 } > ram 45 50 46 51 .vectors 0x100 : -
make/custom/mpc8349eamds.cfg
r38630e98 re35c696 1 1 # 2 # Config file for customer specific MPC5200board2 # Config file for freescale's MPC8349EAMDS evaluation board 3 3 # 4 4 # $Id$
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