Changeset e358088 in rtems for cpukit/score/src/threaddispatchdisablelevel.c
- Timestamp:
- 05/28/13 08:54:46 (11 years ago)
- Branches:
- 4.11, 5, master
- Children:
- bbed1866
- Parents:
- 7c5ceea5
- git-author:
- Sebastian Huber <sebastian.huber@…> (05/28/13 08:54:46)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (05/31/13 13:20:32)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/src/threaddispatchdisablelevel.c
r7c5ceea5 re358088 27 27 #include <rtems/score/thread.h> 28 28 29 #define NO_OWNER_CPU (-1) 30 29 31 void _Thread_Dispatch_initialization( void ) 30 32 { 31 _Thread_Dispatch_disable_level = 0; 32 _SMP_lock_spinlock_nested_Initialize(&_Thread_Dispatch_disable_level_lock); 33 Thread_Dispatch_disable_level_lock_control *level_lock = 34 &_Thread_Dispatch_disable_level_lock; 35 36 _Thread_Dispatch_disable_level = 0; 37 _SMP_lock_Initialize( &level_lock->lock ); 38 level_lock->owner_cpu = NO_OWNER_CPU; 33 39 _Thread_Dispatch_set_disable_level( 1 ); 34 40 } … … 47 53 } 48 54 49 uint32_t _Thread_Dispatch_increment_disable_level( void)55 uint32_t _Thread_Dispatch_increment_disable_level( void ) 50 56 { 51 ISR_Level isr_level; 52 uint32_t level; 57 Thread_Dispatch_disable_level_lock_control *level_lock = 58 &_Thread_Dispatch_disable_level_lock; 59 int self_cpu = bsp_smp_processor_id(); 60 ISR_Level isr_level; 61 uint32_t disable_level; 53 62 54 /* 55 * Note: _SMP_lock_spinlock_nested_Obtain returns 56 * with ISR's disabled and the isr_level that 57 * should be restored after a short period. 58 * 59 * Here we obtain the lock and increment the 60 * Thread dispatch disable level while under the 61 * protection of the isr being off. After this 62 * point it is safe to re-enable ISRs and allow 63 * the dispatch disable lock to provide protection. 64 */ 63 _ISR_Disable_on_this_core( isr_level ); 65 64 66 isr_level = _SMP_lock_spinlock_nested_Obtain( 67 &_Thread_Dispatch_disable_level_lock 68 ); 69 70 _Thread_Dispatch_disable_level++; 71 level = _Thread_Dispatch_disable_level; 65 if ( level_lock->owner_cpu != self_cpu ) { 66 _SMP_lock_Acquire( &level_lock->lock ); 67 level_lock->owner_cpu = self_cpu; 68 level_lock->nest_level = 1; 69 } else { 70 ++level_lock->nest_level; 71 } 72 72 73 _ISR_Enable_on_this_core(isr_level); 74 return level; 73 disable_level = _Thread_Dispatch_disable_level; 74 ++disable_level; 75 _Thread_Dispatch_disable_level = disable_level; 76 77 _ISR_Enable_on_this_core( isr_level ); 78 79 return disable_level; 75 80 } 76 81 77 uint32_t _Thread_Dispatch_decrement_disable_level( void)82 uint32_t _Thread_Dispatch_decrement_disable_level( void ) 78 83 { 79 ISR_Level isr_level; 80 uint32_t level; 84 Thread_Dispatch_disable_level_lock_control *level_lock = 85 &_Thread_Dispatch_disable_level_lock; 86 ISR_Level isr_level; 87 uint32_t disable_level; 81 88 82 /* First we must disable ISRs in order to protect83 * accesses to the dispatch disable level.84 */85 89 _ISR_Disable_on_this_core( isr_level ); 86 90 87 _Thread_Dispatch_disable_level--; 88 level = _Thread_Dispatch_disable_level; 91 --level_lock->nest_level; 92 if ( level_lock->nest_level == 0 ) { 93 level_lock->owner_cpu = NO_OWNER_CPU; 94 _SMP_lock_Release( &level_lock->lock ); 95 } 89 96 97 disable_level = _Thread_Dispatch_disable_level; 98 --disable_level; 99 _Thread_Dispatch_disable_level = disable_level; 90 100 91 /* 92 * Note: _SMP_lock_spinlock_nested_Obtain returns with 93 * ISR's disabled and _SMP_lock_spinlock_nested_Release 94 * is responsable for re-enabling interrupts. 95 */ 96 _SMP_lock_spinlock_nested_Release( 97 &_Thread_Dispatch_disable_level_lock, 98 isr_level 99 ); 101 _ISR_Enable_on_this_core( isr_level ); 100 102 101 return level;103 return disable_level; 102 104 } 103 105
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