Index: bsps/arm/include/bsp/arm-gic-irq.h
===================================================================
--- bsps/arm/include/bsp/arm-gic-irq.h	(revision feea03b625fecc507deab8dbaaafc6b19045e3f1)
+++ bsps/arm/include/bsp/arm-gic-irq.h	(revision e33be09cfbf549228fea16f4421b277bfb9ae7dc)
@@ -8,5 +8,5 @@
 
 /*
- * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
@@ -58,4 +58,14 @@
   rtems_vector_number vector,
   uint8_t *priority
+);
+
+rtems_status_code arm_gic_irq_set_group(
+  rtems_vector_number vector,
+  gic_group group
+);
+
+rtems_status_code arm_gic_irq_get_group(
+  rtems_vector_number vector,
+  gic_group *group
 );
 
Index: bsps/arm/include/bsp/arm-gic-regs.h
===================================================================
--- bsps/arm/include/bsp/arm-gic-regs.h	(revision feea03b625fecc507deab8dbaaafc6b19045e3f1)
+++ bsps/arm/include/bsp/arm-gic-regs.h	(revision e33be09cfbf549228fea16f4421b277bfb9ae7dc)
@@ -8,5 +8,5 @@
 
 /*
- * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
@@ -28,4 +28,8 @@
 typedef struct {
   uint32_t iccicr;
+#define GIC_CPUIF_ICCICR_CBPR BSP_BIT32(4)
+#define GIC_CPUIF_ICCICR_FIQ_EN BSP_BIT32(3)
+#define GIC_CPUIF_ICCICR_ACK_CTL BSP_BIT32(2)
+#define GIC_CPUIF_ICCICR_ENABLE_GRP_1 BSP_BIT32(1)
 #define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0)
   uint32_t iccpmr;
@@ -84,4 +88,5 @@
 typedef struct {
   uint32_t icddcr;
+#define GIC_DIST_ICDDCR_ENABLE_GRP_1 BSP_BIT32(1)
 #define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0)
   uint32_t icdictr;
@@ -110,5 +115,5 @@
 #define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11)
   uint32_t reserved_0c[29];
-  uint32_t icdisr[32];
+  uint32_t icdigr[32];
   uint32_t icdiser[32];
   uint32_t icdicer[32];
Index: bsps/arm/include/bsp/arm-gic.h
===================================================================
--- bsps/arm/include/bsp/arm-gic.h	(revision feea03b625fecc507deab8dbaaafc6b19045e3f1)
+++ bsps/arm/include/bsp/arm-gic.h	(revision e33be09cfbf549228fea16f4421b277bfb9ae7dc)
@@ -8,5 +8,5 @@
 
 /*
- * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
@@ -102,4 +102,39 @@
 }
 
+typedef enum {
+  GIC_GROUP_0,
+  GIC_GROUP_1
+} gic_group;
+
+static inline gic_group gic_id_get_group(
+  volatile gic_dist *dist,
+  uint32_t id
+)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+
+  return (dist->icdigr[i] & bit) != 0 ?  GIC_GROUP_1 : GIC_GROUP_0;
+}
+
+static inline void gic_id_set_group(
+  volatile gic_dist *dist,
+  uint32_t id,
+  gic_group group
+)
+{
+  uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id);
+  uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id);
+  uint32_t icdigr = dist->icdigr[i];
+
+  icdigr &= ~bit;
+
+  if (group == GIC_GROUP_1) {
+    icdigr |= bit;
+  }
+
+  dist->icdigr[i] = icdigr;
+}
+
 static inline void gic_id_set_priority(
   volatile gic_dist *dist,
Index: bsps/arm/shared/irq/irq-gic.c
===================================================================
--- bsps/arm/shared/irq/irq-gic.c	(revision feea03b625fecc507deab8dbaaafc6b19045e3f1)
+++ bsps/arm/shared/irq/irq-gic.c	(revision e33be09cfbf549228fea16f4421b277bfb9ae7dc)
@@ -1,4 +1,4 @@
 /*
- * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013, 2019 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
@@ -158,4 +158,40 @@
 }
 
+rtems_status_code arm_gic_irq_set_group(
+  rtems_vector_number vector,
+  gic_group group
+)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  if (bsp_interrupt_is_valid_vector(vector)) {
+    volatile gic_dist *dist = ARM_GIC_DIST;
+
+    gic_id_set_group(dist, vector, group);
+  } else {
+    sc = RTEMS_INVALID_ID;
+  }
+
+  return sc;
+}
+
+rtems_status_code arm_gic_irq_get_group(
+  rtems_vector_number vector,
+  gic_group *group
+)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  if (bsp_interrupt_is_valid_vector(vector)) {
+    volatile gic_dist *dist = ARM_GIC_DIST;
+
+    *group = gic_id_get_group(dist, vector);
+  } else {
+    sc = RTEMS_INVALID_ID;
+  }
+
+  return sc;
+}
+
 void bsp_interrupt_set_affinity(
   rtems_vector_number vector,
