Changeset e2d0c68 in rtems


Ignore:
Timestamp:
Sep 1, 2011, 3:52:12 PM (10 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
900d9e66
Parents:
84649da
Message:

2011-09-01 Sebastian Huber <sebastian.huber@…>

  • cpu.c, cpu_asm.S: Removed files.
  • nios2-context-initialize.c, nios2-context-switch.S, nios2-fatal-halt.c, nios2-initialize-vectors.c, nios2-initialize.c, nios2-isr-get-level.c, nios2-isr-install-raw-handler.c, nios2-isr-install-vector.c, nios2-isr-is-in-progress.c, nios2-isr-set-level.c, nios2-thread-dispatch-disabled.c, rtems/score/nios2-utility.h: New files.
  • Makefile.am, preinstall.am: Reflect changes above.
  • irq.c: Update due to API changes.
  • rtems/score/cpu.h: New functions _CPU_Initialize_vectors(), _CPU_ISR_Set_level(), and _CPU_Fatal_halt() (instead of macros). Support for external interrupt controller (EIC). Documentation changes.
Location:
cpukit/score/cpu/nios2
Files:
12 added
2 deleted
5 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/nios2/ChangeLog

    r84649da re2d0c68  
     12011-09-01      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * cpu.c, cpu_asm.S: Removed files.
     4        * nios2-context-initialize.c, nios2-context-switch.S,
     5        nios2-fatal-halt.c, nios2-initialize-vectors.c, nios2-initialize.c,
     6        nios2-isr-get-level.c, nios2-isr-install-raw-handler.c,
     7        nios2-isr-install-vector.c, nios2-isr-is-in-progress.c,
     8        nios2-isr-set-level.c, nios2-thread-dispatch-disabled.c,
     9        rtems/score/nios2-utility.h: New files.
     10        * Makefile.am, preinstall.am: Reflect changes above.
     11        * irq.c: Update due to API changes.
     12        * rtems/score/cpu.h: New functions _CPU_Initialize_vectors(),
     13        _CPU_ISR_Set_level(), and _CPU_Fatal_halt() (instead of macros).
     14        Support for external interrupt controller (EIC).  Documentation
     15        changes.
     16
    1172011-08-18      Chris Johns <chrisj@rtems.org>
    218
  • cpukit/score/cpu/nios2/Makefile.am

    r84649da re2d0c68  
    99
    1010include_rtemsdir = $(includedir)/rtems
     11
    1112include_rtems_HEADERS = rtems/asm.h
    1213
    1314include_rtems_scoredir = $(includedir)/rtems/score
    14 include_rtems_score_HEADERS = rtems/score/cpu.h
     15
     16include_rtems_score_HEADERS =
     17include_rtems_score_HEADERS += rtems/score/cpu.h
    1518include_rtems_score_HEADERS += rtems/score/nios2.h
     19include_rtems_score_HEADERS += rtems/score/nios2-utility.h
    1620include_rtems_score_HEADERS += rtems/score/cpu_asm.h
    1721include_rtems_score_HEADERS += rtems/score/types.h
    1822
    1923noinst_LIBRARIES = libscorecpu.a
    20 libscorecpu_a_SOURCES = cpu.c \
    21         irq.c \
    22         nios2-iic-low-level.S \
    23         cpu_asm.S
     24
     25libscorecpu_a_SOURCES =
     26libscorecpu_a_SOURCES += irq.c
     27libscorecpu_a_SOURCES += nios2-context-initialize.c
     28libscorecpu_a_SOURCES += nios2-context-switch.S
     29libscorecpu_a_SOURCES += nios2-fatal-halt.c
     30libscorecpu_a_SOURCES += nios2-iic-low-level.S
     31libscorecpu_a_SOURCES += nios2-initialize.c
     32libscorecpu_a_SOURCES += nios2-initialize-vectors.c
     33libscorecpu_a_SOURCES += nios2-isr-get-level.c
     34libscorecpu_a_SOURCES += nios2-isr-install-raw-handler.c
     35libscorecpu_a_SOURCES += nios2-isr-install-vector.c
     36libscorecpu_a_SOURCES += nios2-isr-is-in-progress.c
     37libscorecpu_a_SOURCES += nios2-isr-set-level.c
     38libscorecpu_a_SOURCES += nios2-thread-dispatch-disabled.c
     39
    2440libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
    2541
  • cpukit/score/cpu/nios2/irq.c

    r84649da re2d0c68  
    2222#include <rtems/score/isr.h>
    2323#include <rtems/score/thread.h>
     24#include <rtems/score/nios2-utility.h>
    2425
    2526/*
     
    5455   */
    5556
    56   _CPU_read_ipending (active);
     57  active = _Nios2_Get_ctlreg_ipending();
    5758
    5859  while (active)
     
    7879    };
    7980
    80     _CPU_read_ipending (active);
     81    active = _Nios2_Get_ctlreg_ipending();
    8182  }
    8283 
  • cpukit/score/cpu/nios2/preinstall.am

    r84649da re2d0c68  
    3636PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/nios2.h
    3737
     38$(PROJECT_INCLUDE)/rtems/score/nios2-utility.h: rtems/score/nios2-utility.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
     39        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/nios2-utility.h
     40PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/nios2-utility.h
     41
    3842$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
    3943        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
  • cpukit/score/cpu/nios2/rtems/score/cpu.h

    r84649da re2d0c68  
    4242#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
    4343
    44 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
     44#define CPU_PROVIDES_ISR_IS_IN_PROGRESS TRUE
    4545
    4646#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
     
    8787#define CPU_PARTITION_ALIGNMENT CPU_ALIGNMENT
    8888
    89 #define CPU_STACK_ALIGNMENT CPU_ALIGNMENT
    90 
    91 #define CPU_MODES_INTERRUPT_MASK 0x1
     89/*
     90 * Alignment value according to "Nios II Processor Reference" chapter 7
     91 * "Application Binary Interface" section "Stacks".
     92 */
     93#define CPU_STACK_ALIGNMENT 4
     94
     95/*
     96 * A Nios II configuration with an external interrupt controller (EIC) supports
     97 * up to 64 interrupt levels.  A Nios II configuration with an internal
     98 * interrupt controller (IIC) has only two interrupt levels (enabled and
     99 * disabled).  The _CPU_ISR_Get_level() and _CPU_ISR_Set_level() functions will
     100 * take care about configuration specific mappings.
     101 */
     102#define CPU_MODES_INTERRUPT_MASK 0x3f
    92103
    93104#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
     
    107118 * There is no need to save the global pointer (gp) since it is a system wide
    108119 * constant and set-up with the C runtime environment.
     120 *
     121 * The @a thread_dispatch_disabled field is used for the external interrupt
     122 * controller (EIC) support.
     123 *
     124 * @see _Nios2_Thread_dispatch_disabled
    109125 */
    110126typedef struct {
     
    118134  uint32_t r23;
    119135  uint32_t fp;
     136  uint32_t status;
    120137  uint32_t sp;
    121138  uint32_t ra;
    122   uint32_t status;
     139  uint32_t thread_dispatch_disabled;
    123140} Context_Control;
    124141
     
    183200} CPU_Exception_frame;
    184201
    185 #if (CPU_SIMPLE_VECTORED_INTERRUPTS == TRUE)
    186 #define _CPU_Initialize_vectors() \
    187   memset(_ISR_Vector_table, 0, sizeof(ISR_Handler_entry) * ISR_NUMBER_OF_VECTORS)
    188 #else
    189 #define _CPU_Initialize_vectors()
    190 #endif
    191 
    192 /**
    193  *  @brief Read the ienable register.
    194  */
    195 #define _CPU_read_ienable( value ) \
    196     do { value = __builtin_rdctl(3); } while (0)
    197 
    198 /**
    199  *  @brief Write the ienable register.
    200  */
    201 #define _CPU_write_ienable( value ) \
    202     do { __builtin_wrctl(3, value); } while (0)
    203 
    204 /**
    205  *  @brief Read the ipending register.
    206  */
    207 #define _CPU_read_ipending( value ) \
    208     do { value = __builtin_rdctl(4); } while (0)
    209 
    210 /**
    211  *  Disable all interrupts for a critical section.  The previous
    212  *  level is returned in _level.
     202void _CPU_Initialize_vectors( void );
     203
     204/**
     205 * @brief Macro to disable interrupts.
     206 *
     207 * The processor status before disabling the interrupts will be stored in
     208 * @a _isr_cookie.  This value will be used in _CPU_ISR_Flash() and
     209 * _CPU_ISR_Enable().
     210 *
     211 * The global symbol _Nios2_ISR_Status_mask will be used to clear the bits in
     212 * the status register representing the interrupt level.  The global symbol
     213 * _Nios2_ISR_Status_bits will be used to set the bits representing an
     214 * interrupt level that disables interrupts.  Both global symbols must be
     215 * provided by the board support package.
     216 *
     217 * In case the Nios II uses the internal interrupt controller (IIC), then only
     218 * the PIE status bit is used.
     219 *
     220 * In case the Nios II uses the external interrupt controller (EIC), then the
     221 * RSIE status bit or the IL status field is used depending on the interrupt
     222 * handling variant and the shadow register usage.
    213223 */
    214224#define _CPU_ISR_Disable( _isr_cookie ) \
    215225  do { \
    216     _isr_cookie = __builtin_rdctl( 0 ); \
    217     __builtin_wrctl( 0, 0 ); \
     226    int _tmp; \
     227    __asm__ volatile ( \
     228      "rdctl %0, status\n" \
     229      "movhi %1, %%hiadj(_Nios2_ISR_Status_mask)\n" \
     230      "addi %1, %1, %%lo(_Nios2_ISR_Status_mask)\n" \
     231      "and %1, %0, %1\n" \
     232      "ori %1, %1, %%lo(_Nios2_ISR_Status_bits)\n" \
     233      "wrctl status, %1" \
     234      : "=&r" (_isr_cookie), "=&r" (_tmp) \
     235    ); \
    218236  } while ( 0 )
    219237
    220238/**
    221  *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
    222  *  This indicates the end of a critical section.  The parameter
    223  *  _level is not modified.
     239 * @brief Macro to restore the processor status.
     240 *
     241 * The @a _isr_cookie must contain the processor status returned by
     242 * _CPU_ISR_Disable().  The value is not modified.
    224243 */
    225244#define _CPU_ISR_Enable( _isr_cookie ) \
    226   do { \
    227     __builtin_wrctl( 0, (int) _isr_cookie ); \
    228   } while ( 0 )
    229 
    230 /**
    231  *  This temporarily restores the interrupt to _level before immediately
    232  *  disabling them again.  This is used to divide long critical
    233  *  sections into two or more parts.  The parameter _level is not
    234  *  modified.
     245  __builtin_wrctl( 0, (int) _isr_cookie )
     246
     247/**
     248 * @brief Macro to restore the processor status and disable the interrupts
     249 * again.
     250 *
     251 * The @a _isr_cookie must contain the processor status returned by
     252 * _CPU_ISR_Disable().  The value is not modified.
     253 *
     254 * This flash code is optimal for all Nios II configurations.  The rdctl does
     255 * not flush the pipeline and has only a late result penalty.  The wrctl on the
     256 * other hand leads to a pipeline flush.
    235257 */
    236258#define _CPU_ISR_Flash( _isr_cookie ) \
    237259  do { \
     260    int _status = __builtin_rdctl( 0 ); \
    238261    __builtin_wrctl( 0, (int) _isr_cookie ); \
    239     __builtin_wrctl( 0, 0 ); \
     262    __builtin_wrctl( 0, _status ); \
    240263  } while ( 0 )
    241264
    242265/**
    243  *  Map interrupt level in task mode onto the hardware that the CPU
    244  *  actually provides.  Currently, interrupt levels which do not
    245  *  map onto the CPU in a straight fashion are undefined.
    246  */
    247 #define _CPU_ISR_Set_level( new_level )      \
    248   _CPU_ISR_Enable( new_level == 0 ? 1 : 0 );
    249 
    250 /**
    251  *  @brief Obtain the Current Interrupt Disable Level
    252  *
    253  *  This method is invoked to return the current interrupt disable level.
    254  *
    255  *  @return This method returns the current interrupt disable level.
     266 * @brief Sets the interrupt level for the executing thread.
     267 *
     268 * The valid values of @a new_level depend on the Nios II configuration.  A
     269 * value of zero represents enabled interrupts in all configurations.
     270 *
     271 * @see _CPU_ISR_Get_level()
     272 */
     273void _CPU_ISR_Set_level( uint32_t new_level );
     274
     275/**
     276 * @brief Returns the interrupt level of the executing thread.
     277 *
     278 * @retval 0 Interrupts are enabled.
     279 * @retval otherwise The value depends on the Nios II configuration.  In case
     280 * of an internal interrupt controller (IIC) the only valid value is one which
     281 * indicates disabled interrupts.  In case of an external interrupt controller
     282 * (EIC) there are two possibilities.  Firstly if the RSIE status bit is used
     283 * to disable interrupts, then one is the only valid value indicating disabled
     284 * interrupts.  Secondly if the IL status field is used to disable interrupts,
     285 * then this value will be returned.  Interrupts are disabled at the maximum
     286 * level specified by the _Nios2_ISR_Status_bits.
    256287 */
    257288uint32_t _CPU_ISR_Get_level( void );
    258289
    259290/**
    260  *  Initialize the context to a state suitable for starting a
    261  *  task after a context restore operation.  Generally, this
    262  *  involves:
    263  *
     291 * @brief Initializes the CPU context.
     292 *
     293 * The following steps are performed:
    264294 *  - setting a starting address
    265295 *  - preparing the stack
    266296 *  - preparing the stack and frame pointers
    267297 *  - setting the proper interrupt level in the context
    268  *  - initializing the floating point context
    269  *
    270  * @param[in] the_context points to the context area
    271  * @param[in] stack_base is the low address of the allocated stack area
    272  * @param[in] size is the size of the stack area in bytes
     298 *
     299 * @param[in] context points to the context area
     300 * @param[in] stack_area_begin is the low address of the allocated stack area
     301 * @param[in] stack_area_size is the size of the stack area in bytes
    273302 * @param[in] new_level is the interrupt level for the task
    274303 * @param[in] entry_point is the task's entry point
    275  * @param[in] is_fp is set to TRUE if the task is a floating point task
    276  *
    277  *  @note  Implemented as a subroutine for the NIOS2 port.
     304 * @param[in] is_fp is set to @c true if the task is a floating point task
    278305 */
    279306void _CPU_Context_Initialize(
    280   Context_Control  *the_context,
    281   uint32_t         *stack_base,
    282   uint32_t          size,
    283   uint32_t          new_level,
    284   void             *entry_point,
    285   bool              is_fp
     307  Context_Control *context,
     308  void *stack_area_begin,
     309  size_t stack_area_size,
     310  uint32_t new_level,
     311  void (*entry_point)( void ),
     312  bool is_fp
    286313);
    287314
     
    289316  _CPU_Context_restore( (_the_context) );
    290317
    291 #define _CPU_Fatal_halt( _error ) \
    292   do { \
    293     __builtin_wrctl(0, 0); /* write 0 to status register (disable interrupts) */ \
    294     __asm volatile ("mov et, %z0" : : "rM" (_error)); /* write error code to ET register */ \
    295     for (;;); \
    296   } while ( 0 )
     318void _CPU_Fatal_halt( uint32_t _error ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
    297319
    298320void _CPU_Initialize( void );
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