Changeset e2191d6c in rtems for c/src/lib/libbsp/arm/tms570


Ignore:
Timestamp:
Mar 27, 2017, 11:21:59 AM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
b8e97e5
Parents:
0a6a2a7b
git-author:
Sebastian Huber <sebastian.huber@…> (03/27/17 11:21:59)
git-committer:
Sebastian Huber <sebastian.huber@…> (03/27/17 11:38:54)
Message:

bsp/tms570: Simplify CPU counter support

Only touch the cycle counter settings. Do not enable user mode access.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/tms570/misc/cpucounterread.c

    r0a6a2a7b re2191d6c  
    3030#include <rtems/sysinit.h>
    3131
     32#include <libcpu/arm-cp15.h>
     33
    3234#include <bsp.h>
    3335
    34 /**
    35  * @brief set mode of Cortex-R performance counters
    36  *
    37  * Based on example found on http://stackoverflow.com
    38  *
    39  * @param[in] do_reset if set, values of the counters are reset
    40  * @param[in] enable_divider if set, CCNT counts clocks divided by 64
    41  * @retval Void
    42  */
    43 static inline void tms570_init_perfcounters(
    44     int32_t do_reset,
    45     int32_t enable_divider
    46 )
    47 {
    48   /* in general enable all counters (including cycle counter) */
    49   int32_t value = 1;
    50 
    51   /* peform reset */
    52   if (do_reset)
    53   {
    54     value |= 2;     /* reset all counters to zero */
    55     value |= 4;     /* reset cycle counter to zero */
    56   }
    57 
    58   if (enable_divider)
    59     value |= 8;     /* enable "by 64" divider for CCNT */
    60 
    61   value |= 16;
    62 
    63   /* program the performance-counter control-register */
    64   asm volatile ("mcr p15, 0, %0, c9, c12, 0\t\n" :: "r"(value));
    65 
    66   /* enable all counters */
    67   asm volatile ("mcr p15, 0, %0, c9, c12, 1\t\n" :: "r"(0x8000000f));
    68 
    69   /* clear overflows */
    70   asm volatile ("mcr p15, 0, %0, c9, c12, 3\t\n" :: "r"(0x8000000f));
    71 }
    72 
    73 /**
    74  * @brief initialize Cortex-R performance counters subsystem
    75  *
    76  * Based on example found on http://stackoverflow.com
    77  *
    78  * @retval Void
    79  *
    80  */
    8136static void tms570_cpu_counter_initialize(void)
    8237{
    83   /* enable user-mode access to the performance counter */
    84   asm volatile ("mcr p15, 0, %0, c9, c14, 0\n\t" :: "r"(1));
     38  uint32_t cycle_counter;
     39  uint32_t pmcr;
    8540
    86   /* disable counter overflow interrupts (just in case) */
    87   asm volatile ("mcr p15, 0, %0, c9, c14, 2\n\t" :: "r"(0x8000000f));
     41  cycle_counter = ARM_CP15_PMCLRSET_CYCLE_COUNTER;
     42  arm_cp15_set_performance_monitors_interrupt_enable_clear(cycle_counter);
     43  arm_cp15_set_performance_monitors_count_enable_set(cycle_counter);
    8844
    89   tms570_init_perfcounters(false, false);
     45  pmcr = arm_cp15_get_performance_monitors_control();
     46  pmcr &= ~ARM_CP15_PMCR_D;
     47  pmcr |= ARM_CP15_PMCR_E;
     48  arm_cp15_set_performance_monitors_control(pmcr);
     49
    9050  rtems_counter_initialize_converter(2 * BSP_PLL_OUT_CLOCK);
    9151}
    9252
    93 /**
    94  * @brief returns the actual value of Cortex-R cycle counter register
    95  *
    96  * The register is incremented at each core clock period
    97  *
    98  * @retval x actual core clock counter value
    99  *
    100  */
    10153CPU_Counter_ticks _CPU_Counter_read(void)
    10254{
    103   uint32_t ticks;
    104   asm volatile ("mrc p15, 0, %0, c9, c13, 0\n": "=r" (ticks));
    105   return ticks;
     55  return arm_cp15_get_performance_monitors_cycle_count();
    10656}
    10757
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