Changeset e2040ba in rtems


Ignore:
Timestamp:
May 22, 2001, 10:59:42 PM (19 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
a355e3ea
Parents:
baf22b9
Message:

2001-05-22 Greg Menke <gregory.menke@…>

  • rtems/score/cpu.h: Add the interrupt stack structure and enhance the context initialization to account for floating point tasks.
  • rtems/score/mips.h: Added the routines mips_set_cause(), mips_get_fcr31(), and mips_set_fcr31().
  • Assisted in design and debug by Joel Sherrill <joel@…>.
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/mips/ChangeLog

    rbaf22b9 re2040ba  
     12001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
     2
     3        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
     4        the context initialization to account for floating point tasks. 
     5        * rtems/score/mips.h: Added the routines mips_set_cause(),
     6        mips_get_fcr31(), and mips_set_fcr31().
     7        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
     8
    192001-05-07      Joel Sherrill <joel@OARcorp.com>
    210
  • c/src/exec/score/cpu/mips/rtems/score/cpu.h

    rbaf22b9 re2040ba  
    1 /* 
     1/*
    22 *  Mips CPU Dependent Header File
    3  * 
     3 *
    44 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
    55 *           Joel Sherrill <joel@OARcorp.com>.
    6  * 
     6 *
    77 *    These changes made the code conditional on standard cpp predefines,
    88 *    merged the mips1 and mips3 code sequences as much as possible,
     
    1212 *    added the new interrupt vectoring support in libcpu and
    1313 *    tried to better support the various interrupt controllers.
    14  *     
     14 *
    1515 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
    16  *           COPYRIGHT (c) 1996 by Transition Networks Inc. 
     16 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
    1717 *
    1818 *    To anyone who acknowledges that this file is provided "AS IS"
     
    147147/*
    148148 *  Does the RTEMS invoke the user's ISR with the vector number and
    149  *  a pointer to the saved interrupt frame (1) or just the vector 
     149 *  a pointer to the saved interrupt frame (1) or just the vector
    150150 *  number (0)?
    151  */
    152 
    153 #define CPU_ISR_PASSES_FRAME_POINTER 0
     151 *
     152 */
     153
     154#define CPU_ISR_PASSES_FRAME_POINTER 1
     155
     156
    154157
    155158/*
     
    257260
    258261/* we can use the low power wait instruction for the IDLE thread */
    259 #define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE 
     262#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
    260263
    261264/*
     
    294297#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
    295298#else
    296 #define CPU_STRUCTURE_ALIGNMENT 
     299#define CPU_STRUCTURE_ALIGNMENT
    297300#endif
    298301
     
    381384    __MIPS_REGISTER_TYPE ra;
    382385    __MIPS_REGISTER_TYPE c0_sr;
    383     __MIPS_REGISTER_TYPE c0_epc;
     386/*    __MIPS_REGISTER_TYPE c0_epc; */
    384387} Context_Control;
    385388
     
    425428} Context_Control_fp;
    426429
    427 typedef struct {
    428     unsigned32 special_interrupt_register;
     430
     431
     432
     433
     434/*
     435 This struct reflects the stack frame employed in ISR_Handler.  Note
     436 that the ISR routine doesn't save all registers to this frame, so
     437 cpu_asm.S should be consulted to see if the registers you're
     438 interested in are actually there.
     439*/
     440
     441typedef struct
     442{
     443#if __mips == 1
     444      unsigned int regs[80];
     445#endif
     446#if  __mips == 3
     447      unsigned int regs[94];
     448#endif
    429449} CPU_Interrupt_frame;
    430450
     
    452472
    453473/*
    454  *  Macros to access required entires in the CPU Table are in 
     474 *  Macros to access required entires in the CPU Table are in
    455475 *  the file rtems/system.h.
    456476 */
     
    644664 *  via the rtems_task_mode directive.
    645665 *
    646  *  On the MIPS, 0 is all on.  Non-zero is all off.  This only 
     666 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
    647667 *  manipulates the IEC.
    648668 */
     
    686706        (_the_context)->fp = _stack_tmp; \
    687707        (_the_context)->ra = (unsigned64)_entry_point; \
    688         if (_isr) (_the_context)->c0_sr = 0xff00; \
    689         else      (_the_context)->c0_sr = 0xff01; \
     708        (_the_context)->c0_sr = ((_the_context)->c0_sr & 0x0fff0000) | \
     709                                ((_isr)?0xff00:0xff01) | \
     710                                ((_is_fp)?0x20000000:0x10000000); \
    690711  }
    691712
     
    875896 *  _CPU_ISR_install_raw_handler
    876897 *
    877  *  This routine installs a "raw" interrupt handler directly into the 
     898 *  This routine installs a "raw" interrupt handler directly into the
    878899 *  processor's vector table.
    879900 */
    880  
     901
    881902void _CPU_ISR_install_raw_handler(
    882903  unsigned32  vector,
     
    9821003 *  will be fetched incorrectly.
    9831004 */
    984  
     1005
    9851006static inline unsigned int CPU_swap_u32(
    9861007  unsigned int value
     
    9881009{
    9891010  unsigned32 byte1, byte2, byte3, byte4, swapped;
    990  
     1011
    9911012  byte4 = (value >> 24) & 0xff;
    9921013  byte3 = (value >> 16) & 0xff;
    9931014  byte2 = (value >> 8)  & 0xff;
    9941015  byte1 =  value        & 0xff;
    995  
     1016
    9961017  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    9971018  return( swapped );
  • c/src/exec/score/cpu/mips/rtems/score/mips.h

    rbaf22b9 re2040ba  
    9191  } while (0)
    9292
     93
     94
     95
     96
     97#define mips_get_cause( _x ) \
     98  do { \
     99    asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
     100  } while (0)
     101
     102
     103#define mips_set_cause( _x ) \
     104  do { \
     105    register unsigned int __x = (_x); \
     106    asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
     107  } while (0)
     108
     109
     110
     111
     112
     113#define mips_get_fcr31( _x ) \
     114  do { \
     115    asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
     116  } while(0)
     117
     118
     119#define mips_set_fcr31( _x ) \
     120  do { \
     121    register unsigned int __x = (_x); \
     122    asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
     123  } while(0)
     124
     125
     126
     127
     128
    93129/*
    94130 *  Manipulate interrupt mask
  • cpukit/score/cpu/mips/ChangeLog

    rbaf22b9 re2040ba  
     12001-05-22      Greg Menke <gregory.menke@gsfc.nasa.gov>
     2
     3        * rtems/score/cpu.h: Add the interrupt stack structure and enhance
     4        the context initialization to account for floating point tasks. 
     5        * rtems/score/mips.h: Added the routines mips_set_cause(),
     6        mips_get_fcr31(), and mips_set_fcr31().
     7        * Assisted in design and debug by Joel Sherrill <joel@OARcorp.com>.
     8
    192001-05-07      Joel Sherrill <joel@OARcorp.com>
    210
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    rbaf22b9 re2040ba  
    1 /* 
     1/*
    22 *  Mips CPU Dependent Header File
    3  * 
     3 *
    44 *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
    55 *           Joel Sherrill <joel@OARcorp.com>.
    6  * 
     6 *
    77 *    These changes made the code conditional on standard cpp predefines,
    88 *    merged the mips1 and mips3 code sequences as much as possible,
     
    1212 *    added the new interrupt vectoring support in libcpu and
    1313 *    tried to better support the various interrupt controllers.
    14  *     
     14 *
    1515 *  Original MIP64ORION port by Craig Lebakken <craigl@transition.com>
    16  *           COPYRIGHT (c) 1996 by Transition Networks Inc. 
     16 *           COPYRIGHT (c) 1996 by Transition Networks Inc.
    1717 *
    1818 *    To anyone who acknowledges that this file is provided "AS IS"
     
    147147/*
    148148 *  Does the RTEMS invoke the user's ISR with the vector number and
    149  *  a pointer to the saved interrupt frame (1) or just the vector 
     149 *  a pointer to the saved interrupt frame (1) or just the vector
    150150 *  number (0)?
    151  */
    152 
    153 #define CPU_ISR_PASSES_FRAME_POINTER 0
     151 *
     152 */
     153
     154#define CPU_ISR_PASSES_FRAME_POINTER 1
     155
     156
    154157
    155158/*
     
    257260
    258261/* we can use the low power wait instruction for the IDLE thread */
    259 #define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE 
     262#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
    260263
    261264/*
     
    294297#define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (16)))
    295298#else
    296 #define CPU_STRUCTURE_ALIGNMENT 
     299#define CPU_STRUCTURE_ALIGNMENT
    297300#endif
    298301
     
    381384    __MIPS_REGISTER_TYPE ra;
    382385    __MIPS_REGISTER_TYPE c0_sr;
    383     __MIPS_REGISTER_TYPE c0_epc;
     386/*    __MIPS_REGISTER_TYPE c0_epc; */
    384387} Context_Control;
    385388
     
    425428} Context_Control_fp;
    426429
    427 typedef struct {
    428     unsigned32 special_interrupt_register;
     430
     431
     432
     433
     434/*
     435 This struct reflects the stack frame employed in ISR_Handler.  Note
     436 that the ISR routine doesn't save all registers to this frame, so
     437 cpu_asm.S should be consulted to see if the registers you're
     438 interested in are actually there.
     439*/
     440
     441typedef struct
     442{
     443#if __mips == 1
     444      unsigned int regs[80];
     445#endif
     446#if  __mips == 3
     447      unsigned int regs[94];
     448#endif
    429449} CPU_Interrupt_frame;
    430450
     
    452472
    453473/*
    454  *  Macros to access required entires in the CPU Table are in 
     474 *  Macros to access required entires in the CPU Table are in
    455475 *  the file rtems/system.h.
    456476 */
     
    644664 *  via the rtems_task_mode directive.
    645665 *
    646  *  On the MIPS, 0 is all on.  Non-zero is all off.  This only 
     666 *  On the MIPS, 0 is all on.  Non-zero is all off.  This only
    647667 *  manipulates the IEC.
    648668 */
     
    686706        (_the_context)->fp = _stack_tmp; \
    687707        (_the_context)->ra = (unsigned64)_entry_point; \
    688         if (_isr) (_the_context)->c0_sr = 0xff00; \
    689         else      (_the_context)->c0_sr = 0xff01; \
     708        (_the_context)->c0_sr = ((_the_context)->c0_sr & 0x0fff0000) | \
     709                                ((_isr)?0xff00:0xff01) | \
     710                                ((_is_fp)?0x20000000:0x10000000); \
    690711  }
    691712
     
    875896 *  _CPU_ISR_install_raw_handler
    876897 *
    877  *  This routine installs a "raw" interrupt handler directly into the 
     898 *  This routine installs a "raw" interrupt handler directly into the
    878899 *  processor's vector table.
    879900 */
    880  
     901
    881902void _CPU_ISR_install_raw_handler(
    882903  unsigned32  vector,
     
    9821003 *  will be fetched incorrectly.
    9831004 */
    984  
     1005
    9851006static inline unsigned int CPU_swap_u32(
    9861007  unsigned int value
     
    9881009{
    9891010  unsigned32 byte1, byte2, byte3, byte4, swapped;
    990  
     1011
    9911012  byte4 = (value >> 24) & 0xff;
    9921013  byte3 = (value >> 16) & 0xff;
    9931014  byte2 = (value >> 8)  & 0xff;
    9941015  byte1 =  value        & 0xff;
    995  
     1016
    9961017  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    9971018  return( swapped );
  • cpukit/score/cpu/mips/rtems/score/mips.h

    rbaf22b9 re2040ba  
    9191  } while (0)
    9292
     93
     94
     95
     96
     97#define mips_get_cause( _x ) \
     98  do { \
     99    asm volatile( "mfc0 %0, $13; nop" : "=r" (_x) : ); \
     100  } while (0)
     101
     102
     103#define mips_set_cause( _x ) \
     104  do { \
     105    register unsigned int __x = (_x); \
     106    asm volatile( "mtc0 %0, $13; nop" : : "r" (__x) ); \
     107  } while (0)
     108
     109
     110
     111
     112
     113#define mips_get_fcr31( _x ) \
     114  do { \
     115    asm volatile( "cfc1 %0, $31; nop" : "=r" (_x) : ); \
     116  } while(0)
     117
     118
     119#define mips_set_fcr31( _x ) \
     120  do { \
     121    register unsigned int __x = (_x); \
     122    asm volatile( "ctc1 %0, $31; nop" : : "r" (__x) ); \
     123  } while(0)
     124
     125
     126
     127
     128
    93129/*
    94130 *  Manipulate interrupt mask
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