Changeset e1ebfebf in rtems

Timestamp:

Feb 11, 2012, 8:15:06 PM (9 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

4.11, 5, master

Children:

002affc

Parents:

14ee5a1e

Message:

Patches for Qemu 1.0.50

Location:

c/src/lib/libbsp/arm/lm3s69xx

Files:

• 0001-Fixed-interrupt-handling-for-ARMv7M.patch (deleted)
• 0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch (moved) (moved from c/src/lib/libbsp/arm/lm3s69xx/0002-Fixed-system-handler-priority-register-access.patch) (8 diffs)
• 0002-target-arm-Disable-priority_mask-feature.patch (moved) (moved from c/src/lib/libbsp/arm/lm3s69xx/0003-Disable-priority_mask-unused-for-NVIC.patch) (2 diffs)
• 0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch (added)
• 0004-Typo.patch (deleted)
• 0004-target-arm-Evil-hack-to-increase-the-RAM-size.patch (added)
• 0005-Evil-hack-for-BASEPRI-BASEPRI_MAX.patch (deleted)
• 0006-Evil-hack-to-increase-the-RAM-size.patch (deleted)
• README (modified) (1 diff)

c/src/lib/libbsp/arm/lm3s69xx/0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch

@@ -1 @@
-From 403b4e0718a815b425a964cfbf7f4117a9278d88 Mon Sep 17 00:00:00 2001
+From 0c8e700376cec0c7b5a70f999b5e286efc321423 Mon Sep 17 00:00:00 2001
 From: Sebastian Huber <sebastian.huber@embedded-brains.de>
-Date: Sun, 19 Jun 2011 15:33:17 +0200
-Subject: [PATCH 2/6] Fixed system handler priority register access.
+Date: Fri, 16 Dec 2011 19:46:40 +0100
+Subject: [PATCH 1/4] target-arm: Fixed ARMv7-M SHPR access
 
 According to "ARMv7-M Architecture Reference Manual" issue D section
@@ -8 +8 @@
 Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy
 Register 3, SHPR3".
+
+Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
 ---
  hw/arm_gic.c     |   16 ++++++++++++++--
@@ -14 +16 @@
 
 diff --git a/hw/arm_gic.c b/hw/arm_gic.c
-index 0e934ec..9f75fcc 100644
+index 9b52119..5139d95 100644
 --- a/hw/arm_gic.c
 +++ b/hw/arm_gic.c
-@@ -341,6 +341,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
+@@ -356,6 +356,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
              if (GIC_TEST_TRIGGER(irq + i))
                  res |= (2 << (i * 2));
@@ -29 +31 @@
      } else if (offset < 0xfe0) {
          goto bad_reg;
-@@ -372,7 +377,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
+@@ -387,7 +392,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
      gic_state *s = (gic_state *)opaque;
      uint32_t addr;
@@ -35 +37 @@
 -    if (addr < 0x100 || addr > 0xd00)
 +    if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
-+        && addr != 0xd20)) {
++        && addr != 0xd20))
          return nvic_readl(s, addr);
  #endif
      val = gic_dist_readw(opaque, offset);
-@@ -507,6 +513,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
+@@ -528,6 +534,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
                  GIC_CLEAR_TRIGGER(irq + i);
              }
@@ -51 +53 @@
      } else {
          /* 0xf00 is only handled for 32-bit writes.  */
-@@ -532,7 +543,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
+@@ -553,7 +564,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
  #ifdef NVIC
      uint32_t addr;
@@ -62 +64 @@
      }
 diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
-index d06eec9..a2d1404 100644
+index bf8c3c5..65b575e 100644
 --- a/hw/armv7m_nvic.c
 +++ b/hw/armv7m_nvic.c
-@@ -194,14 +194,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
+@@ -195,14 +195,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
      case 0xd14: /* Configuration Control.  */
          /* TODO: Implement Configuration Control bits.  */
@@ -80 +82 @@
          val = 0;
          if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
-@@ -334,17 +326,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
+@@ -335,17 +327,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
      case 0xd14: /* Configuration Control.  */
          /* TODO: Implement control registers.  */

c/src/lib/libbsp/arm/lm3s69xx/0002-target-arm-Disable-priority_mask-feature.patch

@@ -1 @@
-From 00cf49e35ff83ca3d90caf98339591452b1100e5 Mon Sep 17 00:00:00 2001
+From 5f562d098d84e12d4688272dcf68a2d0318721a7 Mon Sep 17 00:00:00 2001
 From: Sebastian Huber <sebastian.huber@embedded-brains.de>
-Date: Sun, 17 Jul 2011 15:13:42 +0200
-Subject: [PATCH 3/6] Disable priority_mask (unused for NVIC).
+Date: Fri, 16 Dec 2011 20:00:59 +0100
+Subject: [PATCH 2/4] target-arm: Disable priority_mask feature
 
+This is unused for the ARMv7-M NVIC.
+
+Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
 ---
  hw/arm_gic.c |    4 ++++
@@ -9 +12 @@
 
 diff --git a/hw/arm_gic.c b/hw/arm_gic.c
-index 9f75fcc..a97a318 100644
+index 5139d95..cafcc81 100644
 --- a/hw/arm_gic.c
 +++ b/hw/arm_gic.c
-@@ -642,7 +642,11 @@ static void gic_reset(gic_state *s)
+@@ -707,7 +707,11 @@ static void gic_reset(gic_state *s)
      int i;
      memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));

c/src/lib/libbsp/arm/lm3s69xx/README

@@ -1 +1 @@
 Tested only on Qemu simulator with git (git://git.qemu.org/qemu.git) version
-f9188227a455446b5c10a8f5114f266001c1c801 (Tue May 17 17:08:43 2011).
+1.0.50.
 
 You have to apply the patches:
 
-0001-Fixed-interrupt-handling-for-ARMv7M.patch
-0002-Fixed-system-handler-priority-register-access.patch
-0003-Disable-priority_mask-unused-for-NVIC.patch
-0004-Typo.patch
-0005-Evil-hack-for-BASEPRI-BASEPRI_MAX.patch
-0006-Evil-hack-to-increase-the-RAM-size.patch
+0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch
+0002-target-arm-Disable-priority_mask-feature.patch
+0003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch
+0004-target-arm-Evil-hack-to-increase-the-RAM-size.patch
 
 Command line: