Changeset e1ebfebf in rtems


Ignore:
Timestamp:
Feb 11, 2012, 8:15:06 PM (7 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
002affc
Parents:
14ee5a1e
Message:

Patches for Qemu 1.0.50

Location:
c/src/lib/libbsp/arm/lm3s69xx
Files:
2 added
4 deleted
1 edited
2 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lm3s69xx/0001-target-arm-Fixed-ARMv7-M-SHPR-access.patch

    r14ee5a1e re1ebfebf  
    1 From 403b4e0718a815b425a964cfbf7f4117a9278d88 Mon Sep 17 00:00:00 2001
     1From 0c8e700376cec0c7b5a70f999b5e286efc321423 Mon Sep 17 00:00:00 2001
    22From: Sebastian Huber <sebastian.huber@embedded-brains.de>
    3 Date: Sun, 19 Jun 2011 15:33:17 +0200
    4 Subject: [PATCH 2/6] Fixed system handler priority register access.
     3Date: Fri, 16 Dec 2011 19:46:40 +0100
     4Subject: [PATCH 1/4] target-arm: Fixed ARMv7-M SHPR access
    55
    66According to "ARMv7-M Architecture Reference Manual" issue D section
     
    88Handler Prioriy Register 2, SHPR2", and "B3.2.12 System Handler Prioriy
    99Register 3, SHPR3".
     10
     11Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
    1012---
    1113 hw/arm_gic.c     |   16 ++++++++++++++--
     
    1416
    1517diff --git a/hw/arm_gic.c b/hw/arm_gic.c
    16 index 0e934ec..9f75fcc 100644
     18index 9b52119..5139d95 100644
    1719--- a/hw/arm_gic.c
    1820+++ b/hw/arm_gic.c
    19 @@ -341,6 +341,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
     21@@ -356,6 +356,11 @@ static uint32_t gic_dist_readb(void *opaque, target_phys_addr_t offset)
    2022             if (GIC_TEST_TRIGGER(irq + i))
    2123                 res |= (2 << (i * 2));
     
    2931     } else if (offset < 0xfe0) {
    3032         goto bad_reg;
    31 @@ -372,7 +377,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
     33@@ -387,7 +392,8 @@ static uint32_t gic_dist_readl(void *opaque, target_phys_addr_t offset)
    3234     gic_state *s = (gic_state *)opaque;
    3335     uint32_t addr;
     
    3537-    if (addr < 0x100 || addr > 0xd00)
    3638+    if (addr < 0x100 || (addr > 0xd00 && addr != 0xd18 && addr != 0xd1c
    37 +        && addr != 0xd20)) {
     39+        && addr != 0xd20))
    3840         return nvic_readl(s, addr);
    3941 #endif
    4042     val = gic_dist_readw(opaque, offset);
    41 @@ -507,6 +513,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
     43@@ -528,6 +534,11 @@ static void gic_dist_writeb(void *opaque, target_phys_addr_t offset,
    4244                 GIC_CLEAR_TRIGGER(irq + i);
    4345             }
     
    5153     } else {
    5254         /* 0xf00 is only handled for 32-bit writes.  */
    53 @@ -532,7 +543,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
     55@@ -553,7 +564,8 @@ static void gic_dist_writel(void *opaque, target_phys_addr_t offset,
    5456 #ifdef NVIC
    5557     uint32_t addr;
     
    6264     }
    6365diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
    64 index d06eec9..a2d1404 100644
     66index bf8c3c5..65b575e 100644
    6567--- a/hw/armv7m_nvic.c
    6668+++ b/hw/armv7m_nvic.c
    67 @@ -194,14 +194,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
     69@@ -195,14 +195,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset)
    6870     case 0xd14: /* Configuration Control.  */
    6971         /* TODO: Implement Configuration Control bits.  */
     
    8082         val = 0;
    8183         if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0);
    82 @@ -334,17 +326,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
     84@@ -335,17 +327,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value)
    8385     case 0xd14: /* Configuration Control.  */
    8486         /* TODO: Implement control registers.  */
  • c/src/lib/libbsp/arm/lm3s69xx/0002-target-arm-Disable-priority_mask-feature.patch

    r14ee5a1e re1ebfebf  
    1 From 00cf49e35ff83ca3d90caf98339591452b1100e5 Mon Sep 17 00:00:00 2001
     1From 5f562d098d84e12d4688272dcf68a2d0318721a7 Mon Sep 17 00:00:00 2001
    22From: Sebastian Huber <sebastian.huber@embedded-brains.de>
    3 Date: Sun, 17 Jul 2011 15:13:42 +0200
    4 Subject: [PATCH 3/6] Disable priority_mask (unused for NVIC).
     3Date: Fri, 16 Dec 2011 20:00:59 +0100
     4Subject: [PATCH 2/4] target-arm: Disable priority_mask feature
    55
     6This is unused for the ARMv7-M NVIC.
     7
     8Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
    69---
    710 hw/arm_gic.c |    4 ++++
     
    912
    1013diff --git a/hw/arm_gic.c b/hw/arm_gic.c
    11 index 9f75fcc..a97a318 100644
     14index 5139d95..cafcc81 100644
    1215--- a/hw/arm_gic.c
    1316+++ b/hw/arm_gic.c
    14 @@ -642,7 +642,11 @@ static void gic_reset(gic_state *s)
     17@@ -707,7 +707,11 @@ static void gic_reset(gic_state *s)
    1518     int i;
    1619     memset(s->irq_state, 0, GIC_NIRQ * sizeof(gic_irq_state));
  • c/src/lib/libbsp/arm/lm3s69xx/README

    r14ee5a1e re1ebfebf  
    11Tested only on Qemu simulator with git (git://git.qemu.org/qemu.git) version
    2 f9188227a455446b5c10a8f5114f266001c1c801 (Tue May 17 17:08:43 2011).
     21.0.50.
    33
    44You have to apply the patches:
    55
    6 0001-Fixed-interrupt-handling-for-ARMv7M.patch
    7 0002-Fixed-system-handler-priority-register-access.patch
    8 0003-Disable-priority_mask-unused-for-NVIC.patch
    9 0004-Typo.patch
    10 0005-Evil-hack-for-BASEPRI-BASEPRI_MAX.patch
    11 0006-Evil-hack-to-increase-the-RAM-size.patch
     60001-target-arm-Fixed-ARMv7-M-SHPR-access.patch
     70002-target-arm-Disable-priority_mask-feature.patch
     80003-target-arm-Evil-hack-for-BASEPRI-and-BASEPRI_MAX.patch
     90004-target-arm-Evil-hack-to-increase-the-RAM-size.patch
    1210
    1311Command line:
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