Changeset e1d7bf0 in rtems

Timestamp:

Feb 26, 2014, 10:08:31 AM (6 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

4.11, master

Children:

80186ca8

Parents:

e7549ff4

git-author:

Sebastian Huber <sebastian.huber@…> (02/26/14 10:08:31)

git-committer:

Sebastian Huber <sebastian.huber@…> (02/28/14 08:06:16)

Message:

rtems: Add cache size functions

Add rtems_cache_get_data_cache_size() and
rtems_cache_get_instruction_cache_size().

Files:

• c/src/lib/libcpu/shared/src/cache_manager.c (modified) (2 diffs)
• cpukit/rtems/include/rtems/rtems/cache.h (modified) (1 diff)
• testsuites/sptests/spcache01/init.c (modified) (2 diffs)
• testsuites/sptests/spcache01/spcache01.scn (modified) (2 diffs)

c/src/lib/libcpu/shared/src/cache_manager.c

@@ -161 +161 @@
 
 
+size_t
+rtems_cache_get_data_cache_size( uint32_t level )
+{
+#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS)
+  return _CPU_cache_get_data_cache_size( level );
+#else
+  return 0;
+#endif
+}
+
 /*
  * This function freezes the data cache; cache lines
@@ -276 +286 @@
 
 
+size_t
+rtems_cache_get_instruction_cache_size( uint32_t level )
+{
+#if defined(CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS)
+  return _CPU_cache_get_instruction_cache_size( level );
+#else
+  return 0;
+#endif
+}
+
+
 /*
  * This function freezes the instruction cache; cache lines

cpukit/rtems/include/rtems/rtems/cache.h

@@ -60 +60 @@
  */
 size_t rtems_cache_get_instruction_line_size( void );
+
+/**
+ * @brief Returns the data cache size in bytes.
+ *
+ * @param[in] level The cache level of interest.  The cache level zero
+ * specifies the entire data cache.
+ *
+ * @returns The data cache size in bytes of the specified level.
+ */
+size_t rtems_cache_get_data_cache_size( uint32_t level );
+
+/**
+ * @brief Returns the instruction cache size in bytes.
+ *
+ * @param[in] level The cache level of interest.  The cache level zero
+ * specifies the entire instruction cache.
+ *
+ * @returns The instruction cache size in bytes of the specified level.
+ */
+size_t rtems_cache_get_instruction_cache_size( uint32_t level );
 
 /**

testsuites/sptests/spcache01/init.c

@@ -164 +164 @@
   size_t data_size = sizeof(data);
   uint64_t d[3];
-
-  printf(
-    "data cache line size %zi bytes\n",
-    rtems_cache_get_data_line_size()
-  );
+  uint32_t cache_level;
+  size_t cache_size;
+
+  printf(
+    "data cache line size %zi bytes\n"
+    "data cache size %zi bytes\n",
+    rtems_cache_get_data_line_size(),
+    rtems_cache_get_data_cache_size(0)
+  );
+
+  cache_level = 1;
+  cache_size = rtems_cache_get_data_cache_size(cache_level);
+  while (cache_size > 0) {
+    printf(
+      "data cache level %" PRIu32 " size %zi bytes\n",
+      cache_level,
+      cache_size
+    );
+    ++cache_level;
+    cache_size = rtems_cache_get_data_cache_size(cache_level);
+  }
 
   rtems_interrupt_lock_acquire(&lock, level);
@@ -291 +307 @@
 
   printf(
-    "instruction cache line size %zi bytes\n",
-    rtems_cache_get_instruction_line_size()
-  );
+    "instruction cache line size %zi bytes\n"
+    "instruction cache size %zi bytes\n",
+    rtems_cache_get_instruction_line_size(),
+    rtems_cache_get_instruction_cache_size(0)
+  );
+
+  cache_level = 1;
+  cache_size = rtems_cache_get_instruction_cache_size(cache_level);
+  while (cache_size > 0) {
+    printf(
+      "instruction cache level %" PRIu32 " size %zi bytes\n",
+      cache_level,
+      cache_size
+    );
+    ++cache_level;
+    cache_size = rtems_cache_get_instruction_cache_size(cache_level);
+  }
 
   rtems_interrupt_lock_acquire(&lock, level);

testsuites/sptests/spcache01/spcache01.scn

@@ -4 +4 @@
 data cache operations by line passed the test (copy-back cache detected)
 data cache line size 32 bytes
+data cache size 262144 bytes
+data cache level 1 size 32768 bytes
+data cache level 2 size 262144 bytes
 load 4096 bytes with flush entire data
   duration with normal cache 12660 ns
@@ -29 +32 @@
   duration with invalidated cache 2640 ns
 instruction cache line size 32 bytes
+instruction cache size 262144 bytes
+instruction cache level 1 size 32768 bytes
+instruction cache level 2 size 262144 bytes
 invalidate entire instruction
   duration with normal cache 5780 ns