Changeset e1a06d1b in rtems for c/src/lib/libcpu

Timestamp:

12/02/96 22:47:38 (27 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Branches:

4.10, 4.11, 4.8, 4.9, 5, master

Children:

ffe316d

Parents:

6764c84

Message:

Changes to reflect new revision of erc32 per Jiri Gaisler's suggestions.
This is current as of sis 2.6.

File:

• c/src/lib/libcpu/sparc/include/erc32.h (modified) (8 diffs)

c/src/lib/libcpu/sparc/include/erc32.h

@@ -243 +243 @@
 
 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x001C0000
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4K    ( 0 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8K    ( 1 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16K   ( 2 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_32K   ( 3 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_64K   ( 4 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K  ( 5 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K  ( 6 << 18 )
-#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K  ( 7 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K    ( 0 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K    ( 1 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K   ( 2 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M   ( 3 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M   ( 4 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M  ( 5 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M  ( 6 << 18 )
+#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M  ( 7 << 18 )
  
 /*
@@ -277 +277 @@
  *  The following defines the bits in the UART Control Registers.
  *
- *  NOTE: Same bits in UART channels A and B.
  */
 
 #define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */ 
-#define ERC32_MEC_UART_CONTROL_DR   0x00000100 /* RX Data Ready */
-#define ERC32_MEC_UART_CONTROL_TSE  0x00000200 /* TX Send Empty */
-                                               /*   (i.e. no data to send) */
-#define ERC32_MEC_UART_CONTROL_THE  0x00000400 /* TX Hold Empty */
-                                               /*   (i.e. ready to load) */
  
 /*
@@ -299 +293 @@
 #define ERC32_MEC_UART_STATUS_CU   0x00000080 /* Clear Errors */
 #define ERC32_MEC_UART_STATUS_TXE  0x00000006 /* TX Empty */
+#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
+#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
+#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
+#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
 
 #define ERC32_MEC_UART_STATUS_DRA   (ERC32_MEC_UART_STATUS_DR  << 0)
@@ -350 +348 @@
     sparc_disable_interrupts( _level ); \
     ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
-    sparc_enable_interrupts( _level ); \
     ERC32_MEC.Interrupt_Force = (1 << (_source)); \
+    sparc_enable_interrupts( _level ); \
   } while (0)
  
@@ -470 +468 @@
       _control = _ERC32_MEC_Timer_Control_Mirror; \
       _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
-      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
+      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
       _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
       _control |= __value; \
@@ -480 +478 @@
 #define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
   do { \
-    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
+    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
   } while ( 0 )
 
@@ -499 +497 @@
       _control = _ERC32_MEC_Timer_Control_Mirror; \
       _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
-      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
+      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
       _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
       _control |= __value; \
@@ -509 +507 @@
 #define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
   do { \
-    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
+    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
   } while ( 0 )