Changeset e1a06d1b in rtems


Ignore:
Timestamp:
Dec 2, 1996, 10:47:38 PM (24 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
ffe316d
Parents:
6764c84
Message:

Changes to reflect new revision of erc32 per Jiri Gaisler's suggestions.
This is current as of sis 2.6.

Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/sparc/asm.h

    r6764c84 re1a06d1b  
    106106  mov   _vector, %l3
    107107
     108/*
     109 *  Used for the reset trap for ERC32 to avoid a supervisor instruction
     110 */
     111 
     112#define RTRAP(_vector, _handler)  \
     113  mov   %g0, %l0 ; \
     114  sethi %hi(_handler), %l4 ; \
     115  jmp   %l4+%lo(_handler); \
     116  mov   _vector, %l3
     117
    108118#endif
    109119/* end of include file */
  • c/src/exec/score/cpu/sparc/cpu.c

    r6764c84 re1a06d1b  
    6666{
    6767  void                  *pointer;
     68
     69#ifndef NO_TABLE_MOVE
    6870  unsigned32             trap_table_start;
    6971  unsigned32             tbr_value;
     
    7880   *  install these in the initial trap table.
    7981   */
     82
    8083 
    8184  trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
     
    9396
    9497  sparc_set_tbr( trap_table_start );
     98
     99#endif
    95100
    96101  /*
  • c/src/exec/score/cpu/sparc/cpu.h

    r6764c84 re1a06d1b  
    586586#define SPARC_TRAP_TABLE_ALIGNMENT 4096
    587587 
     588#ifndef NO_TABLE_MOVE
     589
    588590SCORE_EXTERN unsigned8 _CPU_Trap_Table_area[ 8192 ]
    589591           __attribute__ ((aligned (SPARC_TRAP_TABLE_ALIGNMENT)));
     592#endif
    590593 
    591594
  • c/src/exec/score/cpu/sparc/erc32.h

    r6764c84 re1a06d1b  
    243243
    244244#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x001C0000
    245 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4K    ( 0 << 18 )
    246 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8K    ( 1 << 18 )
    247 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16K   ( 2 << 18 )
    248 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_32K   ( 3 << 18 )
    249 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_64K   ( 4 << 18 )
    250 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K  ( 5 << 18 )
    251 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K  ( 6 << 18 )
    252 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K  ( 7 << 18 )
     245#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K    ( 0 << 18 )
     246#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K    ( 1 << 18 )
     247#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K   ( 2 << 18 )
     248#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M   ( 3 << 18 )
     249#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M   ( 4 << 18 )
     250#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M  ( 5 << 18 )
     251#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M  ( 6 << 18 )
     252#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M  ( 7 << 18 )
    253253 
    254254/*
     
    277277 *  The following defines the bits in the UART Control Registers.
    278278 *
    279  *  NOTE: Same bits in UART channels A and B.
    280279 */
    281280
    282281#define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
    283 #define ERC32_MEC_UART_CONTROL_DR   0x00000100 /* RX Data Ready */
    284 #define ERC32_MEC_UART_CONTROL_TSE  0x00000200 /* TX Send Empty */
    285                                                /*   (i.e. no data to send) */
    286 #define ERC32_MEC_UART_CONTROL_THE  0x00000400 /* TX Hold Empty */
    287                                                /*   (i.e. ready to load) */
    288282 
    289283/*
     
    299293#define ERC32_MEC_UART_STATUS_CU   0x00000080 /* Clear Errors */
    300294#define ERC32_MEC_UART_STATUS_TXE  0x00000006 /* TX Empty */
     295#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
     296#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
     297#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
     298#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
    301299
    302300#define ERC32_MEC_UART_STATUS_DRA   (ERC32_MEC_UART_STATUS_DR  << 0)
     
    350348    sparc_disable_interrupts( _level ); \
    351349    ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
    352     sparc_enable_interrupts( _level ); \
    353350    ERC32_MEC.Interrupt_Force = (1 << (_source)); \
     351    sparc_enable_interrupts( _level ); \
    354352  } while (0)
    355353 
     
    470468      _control = _ERC32_MEC_Timer_Control_Mirror; \
    471469      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
    472       _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
     470      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
    473471      _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
    474472      _control |= __value; \
     
    480478#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
    481479  do { \
    482     (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
     480    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
    483481  } while ( 0 )
    484482
     
    499497      _control = _ERC32_MEC_Timer_Control_Mirror; \
    500498      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
    501       _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
     499      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
    502500      _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
    503501      _control |= __value; \
     
    509507#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
    510508  do { \
    511     (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
     509    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
    512510  } while ( 0 )
    513511
  • c/src/lib/libcpu/sparc/include/erc32.h

    r6764c84 re1a06d1b  
    243243
    244244#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_MASK  0x001C0000
    245 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4K    ( 0 << 18 )
    246 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8K    ( 1 << 18 )
    247 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16K   ( 2 << 18 )
    248 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_32K   ( 3 << 18 )
    249 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_64K   ( 4 << 18 )
    250 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K  ( 5 << 18 )
    251 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K  ( 6 << 18 )
    252 #define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K  ( 7 << 18 )
     245#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_128K    ( 0 << 18 )
     246#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_256K    ( 1 << 18 )
     247#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_512K   ( 2 << 18 )
     248#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_1M   ( 3 << 18 )
     249#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_2M   ( 4 << 18 )
     250#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_4M  ( 5 << 18 )
     251#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_8M  ( 6 << 18 )
     252#define ERC32_MEMORY_CONFIGURATION_PROM_SIZE_16M  ( 7 << 18 )
    253253 
    254254/*
     
    277277 *  The following defines the bits in the UART Control Registers.
    278278 *
    279  *  NOTE: Same bits in UART channels A and B.
    280279 */
    281280
    282281#define ERC32_MEC_UART_CONTROL_RTD  0x000000FF /* RX/TX data */
    283 #define ERC32_MEC_UART_CONTROL_DR   0x00000100 /* RX Data Ready */
    284 #define ERC32_MEC_UART_CONTROL_TSE  0x00000200 /* TX Send Empty */
    285                                                /*   (i.e. no data to send) */
    286 #define ERC32_MEC_UART_CONTROL_THE  0x00000400 /* TX Hold Empty */
    287                                                /*   (i.e. ready to load) */
    288282 
    289283/*
     
    299293#define ERC32_MEC_UART_STATUS_CU   0x00000080 /* Clear Errors */
    300294#define ERC32_MEC_UART_STATUS_TXE  0x00000006 /* TX Empty */
     295#define ERC32_MEC_UART_STATUS_CLRA 0x00000080 /* Clear UART A */
     296#define ERC32_MEC_UART_STATUS_CLRB 0x00800000 /* Clear UART B */
     297#define ERC32_MEC_UART_STATUS_ERRA 0x00000070 /* Error in UART A */
     298#define ERC32_MEC_UART_STATUS_ERRB 0x00700000 /* Error in UART B */
    301299
    302300#define ERC32_MEC_UART_STATUS_DRA   (ERC32_MEC_UART_STATUS_DR  << 0)
     
    350348    sparc_disable_interrupts( _level ); \
    351349    ERC32_MEC.Test_Control = ERC32_MEC.Test_Control | 0x80000; \
    352     sparc_enable_interrupts( _level ); \
    353350    ERC32_MEC.Interrupt_Force = (1 << (_source)); \
     351    sparc_enable_interrupts( _level ); \
    354352  } while (0)
    355353 
     
    470468      _control = _ERC32_MEC_Timer_Control_Mirror; \
    471469      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK << 8; \
    472       _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
     470      _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
    473471      _control &= (ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK << 8); \
    474472      _control |= __value; \
     
    480478#define ERC32_MEC_Get_General_Purpose_Timer_Control( _value ) \
    481479  do { \
    482     (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
     480    (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
    483481  } while ( 0 )
    484482
     
    499497      _control = _ERC32_MEC_Timer_Control_Mirror; \
    500498      _control &= ERC32_MEC_TIMER_COUNTER_DEFINED_MASK; \
    501       _ERC32_MEC_Timer_Control_Mirror = _control | _value; \
     499      _ERC32_MEC_Timer_Control_Mirror = _control | __value; \
    502500      _control &= ERC32_MEC_TIMER_COUNTER_CURRENT_MODE_MASK; \
    503501      _control |= __value; \
     
    509507#define ERC32_MEC_Get_Real_Time_Clock_Timer_Control( _value ) \
    510508  do { \
    511     (_value) = _ERC32_MEC_Timer_Control_Mirror & 0xf; \
     509    (_value) = (_ERC32_MEC_Timer_Control_Mirror >> 8) & 0xf; \
    512510  } while ( 0 )
    513511
  • cpukit/score/cpu/sparc/asm.h

    r6764c84 re1a06d1b  
    106106  mov   _vector, %l3
    107107
     108/*
     109 *  Used for the reset trap for ERC32 to avoid a supervisor instruction
     110 */
     111 
     112#define RTRAP(_vector, _handler)  \
     113  mov   %g0, %l0 ; \
     114  sethi %hi(_handler), %l4 ; \
     115  jmp   %l4+%lo(_handler); \
     116  mov   _vector, %l3
     117
    108118#endif
    109119/* end of include file */
  • cpukit/score/cpu/sparc/cpu.c

    r6764c84 re1a06d1b  
    6666{
    6767  void                  *pointer;
     68
     69#ifndef NO_TABLE_MOVE
    6870  unsigned32             trap_table_start;
    6971  unsigned32             tbr_value;
     
    7880   *  install these in the initial trap table.
    7981   */
     82
    8083 
    8184  trap_table_start = (unsigned32) &_CPU_Trap_Table_area;
     
    9396
    9497  sparc_set_tbr( trap_table_start );
     98
     99#endif
    95100
    96101  /*
  • cpukit/score/cpu/sparc/rtems/asm.h

    r6764c84 re1a06d1b  
    106106  mov   _vector, %l3
    107107
     108/*
     109 *  Used for the reset trap for ERC32 to avoid a supervisor instruction
     110 */
     111 
     112#define RTRAP(_vector, _handler)  \
     113  mov   %g0, %l0 ; \
     114  sethi %hi(_handler), %l4 ; \
     115  jmp   %l4+%lo(_handler); \
     116  mov   _vector, %l3
     117
    108118#endif
    109119/* end of include file */
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