Index: bsps/powerpc/gen83xx/start/bsp_specs
===================================================================
--- bsps/powerpc/gen83xx/start/bsp_specs	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/bsp_specs	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: ecrti%O%s rtems_crti%O%s crtbegin.o%s -u __vectors}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s ecrtn.o%s}
Index: bsps/powerpc/gen83xx/start/bspreset.c
===================================================================
--- bsps/powerpc/gen83xx/start/bspreset.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/bspreset.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+
+#include <mpc83xx/mpc83xx.h>
+
+void bsp_reset(void)
+{
+  mpc83xx_reset();
+}
Index: bsps/powerpc/gen83xx/start/bsprestart.c
===================================================================
--- bsps/powerpc/gen83xx/start/bsprestart.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/bsprestart.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2008-2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/u-boot.h>
+
+#include <libcpu/powerpc-utility.h>
+
+void bsp_restart(void *addr)
+{
+  rtems_interrupt_level level;
+  void (*start)(void) = addr;
+  #ifdef HAS_UBOOT
+    const void *mem_begin = (const void *) bsp_uboot_board_info.bi_memstart;
+    size_t mem_size = bsp_uboot_board_info.bi_memsize;
+  #else /* HAS_UBOOT */
+    const void *mem_begin = bsp_ram_start;
+    size_t mem_size = (size_t) bsp_ram_size;
+  #endif /* HAS_UBOOT */
+  uint32_t hid0;
+
+  rtems_interrupt_disable(level);
+  (void) level; /* avoid set but not used warning */
+
+  hid0 = PPC_SPECIAL_PURPOSE_REGISTER(HID0);
+
+  if ((hid0 & HID0_DCE) != 0) {
+    rtems_cache_flush_multiple_data_lines(mem_begin, mem_size);
+  }
+
+  hid0 &= ~(HID0_DCE | HID0_ICE);
+
+  PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0);
+
+  (*start)();
+}
Index: bsps/powerpc/gen83xx/start/bspstart.c
===================================================================
--- bsps/powerpc/gen83xx/start/bspstart.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/bspstart.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,129 @@
+/**
+ * @file
+ *
+ * @ingroup mpc83xx
+ *
+ * @brief Source for BSP startup code.
+ */
+
+/*
+ * Copyright (c) 2008-2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/counter.h>
+
+#include <libchip/ns16550.h>
+
+#include <libcpu/powerpc-utility.h>
+
+#include <bsp.h>
+#include <bsp/vectors.h>
+#include <bsp/bootcard.h>
+#include <bsp/irq-generic.h>
+#include <bsp/linker-symbols.h>
+#include <bsp/u-boot.h>
+#include <bsp/console-termios.h>
+
+/* Configuration parameters for console driver, ... */
+unsigned int BSP_bus_frequency;
+
+/* Configuration parameter for clock driver */
+uint32_t bsp_time_base_frequency;
+
+/* Legacy */
+uint32_t bsp_clicks_per_usec;
+
+/* Default decrementer exception handler */
+static int mpc83xx_decrementer_exception_handler( BSP_Exception_frame *frame, unsigned number)
+{
+  ppc_set_decrementer_register(UINT32_MAX);
+
+  return 0;
+}
+
+void bsp_start( void)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+  unsigned long i = 0;
+
+  /*
+   * Get CPU identification dynamically. Note that the get_ppc_cpu_type() function
+   * store the result in global variables so that it can be used latter...
+   */
+  get_ppc_cpu_type();
+  get_ppc_cpu_revision();
+
+  /* Basic CPU initialization */
+  cpu_init();
+
+  /*
+   * Enable instruction and data caches. Do not force writethrough mode.
+   */
+
+#ifdef BSP_INSTRUCTION_CACHE_ENABLED
+  rtems_cache_enable_instruction();
+#endif
+
+#ifdef BSP_DATA_CACHE_ENABLED
+  rtems_cache_enable_data();
+#endif
+
+  /*
+   * This is evaluated during runtime, so it should be ok to set it
+   * before we initialize the drivers.
+   */
+
+  /* Initialize some device driver parameters */
+
+#ifdef HAS_UBOOT
+  BSP_bus_frequency = bsp_uboot_board_info.bi_busfreq;
+#else /* HAS_UBOOT */
+  BSP_bus_frequency = BSP_CLKIN_FRQ * BSP_SYSPLL_MF / BSP_SYSPLL_CKID;
+#endif /* HAS_UBOOT */
+  bsp_time_base_frequency = BSP_bus_frequency / 4;
+  bsp_clicks_per_usec = bsp_time_base_frequency / 1000000;
+  rtems_counter_initialize_converter(bsp_time_base_frequency);
+
+  /* Initialize some console parameters */
+  for (i = 0; i < console_device_count; ++i) {
+    ns16550_context *ctx = (ns16550_context *) console_device_table[i].context;
+
+    ctx->clock = BSP_bus_frequency;
+
+    #ifdef HAS_UBOOT
+      ctx->initial_baud = bsp_uboot_board_info.bi_baudrate;
+    #endif
+  }
+
+  /* Initialize exception handler */
+#ifndef BSP_DATA_CACHE_ENABLED
+  ppc_exc_cache_wb_check = 0;
+#endif
+  ppc_exc_initialize(
+    (uintptr_t) bsp_section_work_begin,
+    rtems_configuration_get_interrupt_stack_size()
+  );
+
+  /* Install default handler for the decrementer exception */
+  sc = ppc_exc_set_handler( ASM_DEC_VECTOR, mpc83xx_decrementer_exception_handler);
+  if (sc != RTEMS_SUCCESSFUL) {
+    rtems_panic("cannot install decrementer exception handler");
+  }
+
+  /* Initalize interrupt support */
+  bsp_interrupt_initialize();
+
+#ifdef SHOW_MORE_INIT_SETTINGS
+  printk("Exit from bspstart\n");
+#endif
+}
Index: bsps/powerpc/gen83xx/start/cpuinit.c
===================================================================
--- bsps/powerpc/gen83xx/start/cpuinit.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/cpuinit.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,329 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC83xx BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains the code to initialize the cpu               |
+\*===============================================================*/
+
+
+/***********************************************************************/
+/*                                                                     */
+/*   Module:       cpuinit.c                                           */
+/*   Date:         07/17/2003                                          */
+/*   Purpose:      RTEMS MPC5x00 C level startup code                  */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Description:  This file contains additional functions for         */
+/*                 initializing the MPC5x00 CPU                        */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Code                                                              */
+/*   References:   MPC8260ads additional CPU initialization            */
+/*   Module:       cpuinit.c                                           */
+/*   Project:      RTEMS 4.6.0pre1 / MCF8260ads BSP                    */
+/*   Version       1.1                                                 */
+/*   Date:         10/22/2002                                          */
+/*                                                                     */
+/*   Author(s) / Copyright(s):                                         */
+/*                                                                     */
+/*   Written by Jay Monkman (jmonkman@frasca.com)                      */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Partially based on the code references which are named above.     */
+/*   Adaptions, modifications, enhancements and any recent parts of    */
+/*   the code are under the right of                                   */
+/*                                                                     */
+/*         IPR Engineering, Dachauer StraÃe 38, D-80335 MÃŒnchen        */
+/*                        Copyright(C) 2003                            */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   IPR Engineering makes no representation or warranties with        */
+/*   respect to the performance of this computer program, and          */
+/*   specifically disclaims any responsibility for any damages,        */
+/*   special or consequential, connected with the use of this program. */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Version history:  1.0                                             */
+/*                                                                     */
+/***********************************************************************/
+
+#include <stdbool.h>
+#include <string.h>
+
+#include <libcpu/powerpc-utility.h>
+#include <libcpu/mmu.h>
+
+#include <mpc83xx/mpc83xx.h>
+
+#include <bsp.h>
+#include <bsp/u-boot.h>
+
+#define SET_DBAT( n, uv, lv) \
+  do { \
+    PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##L, lv); \
+    PPC_SET_SPECIAL_PURPOSE_REGISTER( DBAT##n##U, uv); \
+  } while (0)
+
+#define SET_IBAT( n, uv, lv) \
+  do { \
+    PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##L, lv); \
+    PPC_SET_SPECIAL_PURPOSE_REGISTER( IBAT##n##U, uv); \
+  } while (0)
+
+static void calc_dbat_regvals(
+  BAT *bat_ptr,
+  uint32_t base_addr,
+  uint32_t size,
+  bool flg_w,
+  bool flg_i,
+  bool flg_m,
+  bool flg_g,
+  uint32_t flg_bpp
+)
+{
+  uint32_t block_mask = 0xffffffff;
+  uint32_t end_addr = base_addr + size - 1;
+
+  /* Determine block mask, that overlaps the whole block */
+  while ((end_addr & block_mask) != (base_addr & block_mask)) {
+    block_mask <<= 1;
+  }
+
+  bat_ptr->batu.bepi = base_addr >> (32 - 15);
+  bat_ptr->batu.bl   = ~(block_mask >> (28 - 11));
+  bat_ptr->batu.vs   = 1;
+  bat_ptr->batu.vp   = 1;
+
+  bat_ptr->batl.brpn = base_addr  >> (32 - 15);
+  bat_ptr->batl.w    = flg_w;
+  bat_ptr->batl.i    = flg_i;
+  bat_ptr->batl.m    = flg_m;
+  bat_ptr->batl.g    = flg_g;
+  bat_ptr->batl.pp   = flg_bpp;
+}
+
+static void clear_mmu_regs( void)
+{
+  uint32_t i;
+
+  /* Clear segment registers */
+  for (i = 0;i < 16;i++) {
+    __asm__ volatile( "mtsrin %0, %1\n" : : "r" (i * 0x1000), "r" (i << (31 - 3)));
+  }
+
+  /* Clear TLBs */
+  for (i = 0;i < 32;i++) {
+    __asm__ volatile( "tlbie %0\n" : : "r" (i << (31 - 19)));
+  }
+}
+
+void cpu_init( void)
+{
+  BAT dbat, ibat;
+  uint32_t msr;
+  uint32_t hid0;
+
+  /* Clear MMU and segment registers */
+  clear_mmu_regs();
+
+  /* Clear caches */
+  hid0 = PPC_SPECIAL_PURPOSE_REGISTER(HID0);
+  if ((hid0 & (HID0_ICE | HID0_DCE)) == 0) {
+    hid0 &= ~(HID0_ILOCK | HID0_DLOCK | HID0_ICE | HID0_DCE);
+    PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0);
+    hid0 |= HID0_ICFI | HID0_DCI;
+    PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0);
+    hid0 &= ~(HID0_ICFI | HID0_DCI);
+    PPC_SET_SPECIAL_PURPOSE_REGISTER(HID0, hid0);
+  }
+
+  /*
+   * Set up IBAT registers in MMU
+   */
+
+  memset(&ibat, 0, sizeof( ibat));
+  SET_IBAT( 2, ibat.batu, ibat.batl);
+  SET_IBAT( 3, ibat.batu, ibat.batl);
+  SET_IBAT( 4, ibat.batu, ibat.batl);
+  SET_IBAT( 5, ibat.batu, ibat.batl);
+  SET_IBAT( 6, ibat.batu, ibat.batl);
+  SET_IBAT( 7, ibat.batu, ibat.batl);
+
+  calc_dbat_regvals(
+    &ibat,
+    #ifdef HAS_UBOOT
+      bsp_uboot_board_info.bi_memstart,
+      bsp_uboot_board_info.bi_memsize,
+    #else /* HAS_UBOOT */
+      (uint32_t) bsp_ram_start,
+      (uint32_t) bsp_ram_size,
+    #endif /* HAS_UBOOT */
+    false,
+    false,
+    false,
+    false,
+    BPP_RX
+  );
+  SET_IBAT( 0, ibat.batu, ibat.batl);
+
+  calc_dbat_regvals(
+    &ibat,
+    #ifdef HAS_UBOOT
+      bsp_uboot_board_info.bi_flashstart,
+      bsp_uboot_board_info.bi_flashsize,
+    #else /* HAS_UBOOT */
+      (uint32_t) bsp_rom_start,
+      (uint32_t) bsp_rom_size,
+    #endif /* HAS_UBOOT */
+    false,
+    false,
+    false,
+    false,
+    BPP_RX
+  );
+  SET_IBAT( 1, ibat.batu, ibat.batl);
+
+  /*
+   * Set up DBAT registers in MMU
+   */
+
+  memset(&dbat, 0, sizeof( dbat));
+  SET_DBAT( 3, dbat.batu, dbat.batl);
+  SET_DBAT( 4, dbat.batu, dbat.batl);
+  SET_DBAT( 5, dbat.batu, dbat.batl);
+  SET_DBAT( 6, dbat.batu, dbat.batl);
+  SET_DBAT( 7, dbat.batu, dbat.batl);
+
+  calc_dbat_regvals(
+    &dbat,
+    #ifdef HAS_UBOOT
+      bsp_uboot_board_info.bi_memstart,
+      bsp_uboot_board_info.bi_memsize,
+    #else /* HAS_UBOOT */
+      (uint32_t) bsp_ram_start,
+      (uint32_t) bsp_ram_size,
+    #endif /* HAS_UBOOT */
+    false,
+    false,
+    false,
+    false,
+    BPP_RW
+  );
+  SET_DBAT( 0, dbat.batu, dbat.batl);
+
+  calc_dbat_regvals(
+    &dbat,
+    #ifdef HAS_UBOOT
+      bsp_uboot_board_info.bi_flashstart,
+      bsp_uboot_board_info.bi_flashsize,
+    #else /* HAS_UBOOT */
+      (uint32_t) bsp_rom_start,
+      (uint32_t) bsp_rom_size,
+    #endif /* HAS_UBOOT */
+    #ifdef MPC83XX_HAS_NAND_LP_FLASH_ON_CS0
+      false,
+      true,
+      false,
+      true,
+      BPP_RW
+    #else
+      true,
+      false,
+      false,
+      false,
+      BPP_RX
+    #endif
+  );
+  SET_DBAT( 1, dbat.batu, dbat.batl);
+
+  calc_dbat_regvals(
+    &dbat,
+    #ifdef HAS_UBOOT
+      bsp_uboot_board_info.bi_immrbar,
+    #else /* HAS_UBOOT */
+      (uint32_t) IMMRBAR,
+    #endif /* HAS_UBOOT */
+    #if MPC83XX_CHIP_TYPE / 10 == 830
+      2 * 1024 * 1024,
+    #else
+      1024 * 1024,
+    #endif
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT( 2, dbat.batu, dbat.batl);
+
+#if defined(MPC83XX_BOARD_HSC_CM01)
+  calc_dbat_regvals(
+    &dbat,
+    FPGA_START,
+    FPGA_SIZE,
+    true,
+    true,
+    true,
+    false,
+    BPP_RW
+  );
+  SET_DBAT(3,dbat.batu,dbat.batl);
+#endif
+
+#ifdef MPC83XX_BOARD_MPC8313ERDB
+  /* Enhanced Local Bus Controller (eLBC) */
+  calc_dbat_regvals(
+    &dbat,
+    0xfa000000,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
+  SET_DBAT( 3, dbat.batu, dbat.batl);
+#endif /* MPC83XX_BOARD_MPC8313ERDB */
+
+  /* Read MSR */
+  msr = ppc_machine_state_register();
+
+  /* Enable data and instruction MMU in MSR */
+  msr |= MSR_DR | MSR_IR;
+
+  /* Enable FPU in MSR */
+  msr |= MSR_FP;
+
+  /* Update MSR */
+  ppc_set_machine_state_register( msr);
+
+  /*
+   * In HID0:
+   *  - Enable dynamic power management
+   *  - Enable machine check interrupts
+   */
+  PPC_SET_SPECIAL_PURPOSE_REGISTER_BITS( HID0, HID0_EMCP | HID0_DPM);
+
+  /* Enable timebase clock */
+  mpc83xx.syscon.spcr |= M83xx_SYSCON_SPCR_TBEN;
+}
Index: bsps/powerpc/gen83xx/start/linkcmds
===================================================================
--- bsps/powerpc/gen83xx/start/linkcmds	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/linkcmds	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,19 @@
+/**
+ * @file 
+ *
+ * Default linker script -- copy of linkcmds.mpc8313erdb
+ * for MPC8313E Reference Design Board.
+ *
+ * This exists simply for consistency so autoconf tests will
+ * be able to compile against this BSP.
+ */
+
+EXTERN (__vectors)
+
+MEMORY {
+	RAM : ORIGIN = 0x0, LENGTH = 128M
+	ROM : ORIGIN = 0xfe000000, LENGTH = 8M
+	MPC83XX_REGS : ORIGIN = 0xe0000000, LENGTH = 256k
+}
+
+INCLUDE linkcmds.base
Index: bsps/powerpc/gen83xx/start/linkcmds.br_uid
===================================================================
--- bsps/powerpc/gen83xx/start/linkcmds.br_uid	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/linkcmds.br_uid	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,10 @@
+MEMORY {
+	RESCONF : ORIGIN = 0x0, LENGTH = 0x100
+	VECTORS : ORIGIN = 0x100, LENGTH = 0x10000 - 0x100
+	WORK : ORIGIN = 0x10000, LENGTH = 256M - 0x10000
+	ROM : ORIGIN = 0xfe000000, LENGTH = 2M
+}
+
+REGION_ALIAS ("START", WORK);
+
+INCLUDE linkcmds.mpc83xx
Index: bsps/powerpc/gen83xx/start/linkcmds.hsc_cm01
===================================================================
--- bsps/powerpc/gen83xx/start/linkcmds.hsc_cm01	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/linkcmds.hsc_cm01	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,10 @@
+MEMORY {
+	RESCONF : ORIGIN = 0x0, LENGTH = 0x100
+	VECTORS : ORIGIN = 0x100, LENGTH = 0x10000 - 0x100
+	WORK : ORIGIN = 0x10000, LENGTH = 256M - 0x10000
+	ROM : ORIGIN = 0xfe000000, LENGTH = 8M
+}
+
+REGION_ALIAS ("START", WORK);
+
+INCLUDE linkcmds.mpc83xx
Index: bsps/powerpc/gen83xx/start/linkcmds.mpc8309som
===================================================================
--- bsps/powerpc/gen83xx/start/linkcmds.mpc8309som	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/linkcmds.mpc8309som	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,10 @@
+MEMORY {
+	RESCONF : ORIGIN = 0x0, LENGTH = 0x100
+	VECTORS : ORIGIN = 0x100, LENGTH = 0x10000 - 0x100
+	WORK : ORIGIN = 0x10000, LENGTH = 256M - 0x10000
+	ROM : ORIGIN = 0xfe000000, LENGTH = 8M
+}
+
+REGION_ALIAS ("START", WORK);
+
+INCLUDE linkcmds.mpc83xx
Index: bsps/powerpc/gen83xx/start/linkcmds.mpc8313erdb
===================================================================
--- bsps/powerpc/gen83xx/start/linkcmds.mpc8313erdb	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/linkcmds.mpc8313erdb	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,10 @@
+MEMORY {
+	RESCONF : ORIGIN = 0x0, LENGTH = 0x100
+	VECTORS : ORIGIN = 0x100, LENGTH = 0x10000 - 0x100
+	WORK : ORIGIN = 0x10000, LENGTH = 128M - 0x10000
+	ROM : ORIGIN = 0xfe000000, LENGTH = 8M
+}
+
+REGION_ALIAS ("START", WORK);
+
+INCLUDE linkcmds.mpc83xx
Index: bsps/powerpc/gen83xx/start/linkcmds.mpc8349eamds
===================================================================
--- bsps/powerpc/gen83xx/start/linkcmds.mpc8349eamds	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/linkcmds.mpc8349eamds	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,10 @@
+MEMORY {
+	RESCONF : ORIGIN = 0x0, LENGTH = 0x100
+	VECTORS : ORIGIN = 0x100, LENGTH = 0x10000 - 0x100
+	WORK : ORIGIN = 0x10000, LENGTH = 256M - 0x10000
+	ROM : ORIGIN = 0xfe000000, LENGTH = 8M
+}
+
+REGION_ALIAS ("START", WORK);
+
+INCLUDE linkcmds.mpc83xx
Index: bsps/powerpc/gen83xx/start/linkcmds.mpc83xx
===================================================================
--- bsps/powerpc/gen83xx/start/linkcmds.mpc83xx	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/linkcmds.mpc83xx	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,47 @@
+bsp_ram_start = ORIGIN (RESCONF);
+bsp_ram_end = ORIGIN (WORK) + LENGTH (WORK);
+bsp_ram_size = bsp_ram_end - bsp_ram_start;
+
+bsp_rom_start = ORIGIN (ROM);
+bsp_rom_size = LENGTH (ROM);
+bsp_rom_end = bsp_rom_start + bsp_rom_size;
+
+IMMRBAR = 0xe0000000;
+mpc83xx = IMMRBAR;
+
+EXTERN (__vectors)
+
+MEMORY {
+	EMPTY : ORIGIN = 0x0, LENGTH = 0
+}
+
+SECTIONS {
+	.resconf : {
+		*(.resconf)
+	} > RESCONF AT > RESCONF
+
+	.vectors : {
+		*(.vectors)
+	} > VECTORS AT > VECTORS
+}
+
+REGION_ALIAS ("REGION_START", START);
+REGION_ALIAS ("REGION_FAST_TEXT", WORK);
+REGION_ALIAS ("REGION_FAST_TEXT_LOAD", WORK);
+REGION_ALIAS ("REGION_TEXT", WORK);
+REGION_ALIAS ("REGION_TEXT_LOAD", WORK);
+REGION_ALIAS ("REGION_RODATA", WORK);
+REGION_ALIAS ("REGION_RODATA_LOAD", WORK);
+REGION_ALIAS ("REGION_FAST_DATA", WORK);
+REGION_ALIAS ("REGION_FAST_DATA_LOAD", WORK);
+REGION_ALIAS ("REGION_DATA", WORK);
+REGION_ALIAS ("REGION_DATA_LOAD", WORK);
+REGION_ALIAS ("REGION_BSS", WORK);
+REGION_ALIAS ("REGION_RWEXTRA", WORK);
+REGION_ALIAS ("REGION_WORK", WORK);
+REGION_ALIAS ("REGION_STACK", WORK);
+REGION_ALIAS ("REGION_NOCACHE", EMPTY);
+REGION_ALIAS ("REGION_NOCACHE_LOAD", EMPTY);
+REGION_ALIAS ("REGION_NVRAM", EMPTY);
+
+INCLUDE linkcmds.base
Index: bsps/powerpc/gen83xx/start/uboot_support.c
===================================================================
--- bsps/powerpc/gen83xx/start/uboot_support.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
+++ bsps/powerpc/gen83xx/start/uboot_support.c	(revision e0dd8a5ad830798bc8082b03b8c42c32fb9660e0)
@@ -0,0 +1,24 @@
+/*
+ *  This file contains variables which assist the shared
+ *  U-Boot code.
+ *
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <stdint.h>
+
+#include <bsp.h>
+
+#if defined(HAS_UBOOT)
+/* XXX TODO fill in with real information */
+/* Base address of U-Boot environment variables */
+const uint8_t *uboot_environment      = (const uint8_t *) 0x00000000;
+
+/* Length of area reserved for U-Boot environment variables */
+const size_t  *uboot_environment_size = (const size_t *) 0x00010000;
+#endif
