Changeset e07b51a7 in rtems


Ignore:
Timestamp:
Jul 2, 2018, 1:21:36 PM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
77fbbd6
Parents:
b36bf5b
Message:

riscv: Fix fcsr initialization

Update #3433.

Location:
cpukit/score/cpu/riscv
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    rb36bf5b re07b51a7  
    287287} RTEMS_ALIGNED( CPU_STACK_ALIGNMENT ) CPU_Interrupt_frame;
    288288
     289static inline uint32_t _RISCV_Read_FCSR( void )
     290{
     291  uint32_t fcsr;
     292
     293  __asm__ volatile ( "frcsr %0" : "=&r" ( fcsr ) );
     294
     295  return fcsr;
     296}
     297
    289298#ifdef RTEMS_SMP
    290299
  • cpukit/score/cpu/riscv/riscv-context-initialize.c

    rb36bf5b re07b51a7  
    3434#endif
    3535
    36 #include <rtems/score/cpu.h>
     36#include <rtems/score/cpuimpl.h>
    3737#include <rtems/score/address.h>
    3838#include <rtems/score/tls.h>
     
    5757  context->isr_dispatch_disable = 0;
    5858
     59#if __riscv_flen > 0
     60  /*
     61   * According to C11 section 7.6 "Floating-point environment <fenv.h>" the
     62   * floating-point environment shall be initialized to the current state of
     63   * the creating thread.
     64   */
     65  context->fcsr = _RISCV_Read_FCSR();
     66#endif
     67
    5968  if ( tls_area != NULL ) {
    6069    void *tls_block;
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