- Timestamp:
- 12/03/14 10:35:52 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- adc1dbeb
- Parents:
- 4081032
- git-author:
- Daniel Hellstrom <daniel@…> (12/03/14 10:35:52)
- git-committer:
- Daniel Hellstrom <daniel@…> (12/04/14 11:51:11)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
doc/cpu_supplement/sparc.t
r4081032 rdff1803 852 852 interrupts are fully enabled. Interrupt requests for interrupts 853 853 with priorities less than or equal to the current interrupt mask 854 level are ignored. 854 level are ignored. Level fifteen (15) is a non-maskable interrupt 855 (NMI), which makes it unsuitable for standard usage since it can 856 affect the real-time behaviour by interrupting critical sections 857 and spinlocks. Disabling traps stops also the NMI interrupt from 858 happening. It can however be used for power-down or other 859 critical events. 855 860 856 861 Although RTEMS supports 256 interrupt levels, the … … 860 865 unpredictable. 861 866 867 Many LEON SPARC v7/v8 systems features an extended interrupt controller 868 which adds an extra step of interrupt decoding to allow handling of 869 interrupt 16-31. When such an extended interrupt is generated the CPU 870 traps into a specific interrupt trap level 1-14 and software reads out from 871 the interrupt controller which extended interrupt source actually caused the 872 interrupt. 873 862 874 @subsection Disabling of Interrupts by RTEMS 863 875 864 876 During the execution of directive calls, critical 865 877 sections of code may be executed. When these sections are 866 encountered, RTEMS disables interrupts to level seven (15)867 before the execution of th issection and restores them to the878 encountered, RTEMS disables interrupts to level fifteen (15) 879 before the execution of the section and restores them to the 868 880 previous level upon completion of the section. RTEMS has been 869 optimized to insure that interrupts are disabled for less than881 optimized to ensure that interrupts are disabled for less than 870 882 RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ 871 883 Mhz ERC32 with zero wait states. … … 887 899 sections. However, ISRs that make no system calls may safely 888 900 execute as non-maskable interrupts. 901 902 Interrupts are disabled or enabled by performing a system call 903 to the Operating System reserved software traps 9 904 (SPARC_SWTRAP_IRQDIS) or 10 (SPARC_SWTRAP_IRQDIS). The trap is 905 generated by the software trap (Ticc) instruction or indirectly 906 by calling sparc_disable_interrupts() or sparc_enable_interrupts() 907 functions. Disabling interrupts return the previous interrupt level 908 (on trap entry) in register G1 and sets PSR.PIL to 15 to disable 909 all maskable interrupts. The interrupt level can be restored by 910 trapping into the enable interrupt handler with G1 containing the 911 new interrupt level. 889 912 890 913 @subsection Interrupt Stack
Note: See TracChangeset
for help on using the changeset viewer.