Changeset dff1803 in rtems for doc


Ignore:
Timestamp:
Dec 3, 2014, 10:35:52 AM (5 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
4.11, master
Children:
adc1dbeb
Parents:
4081032
git-author:
Daniel Hellstrom <daniel@…> (12/03/14 10:35:52)
git-committer:
Daniel Hellstrom <daniel@…> (12/04/14 11:51:11)
Message:

SPARC: optimize IRQ enable & disable

  • Coding style cleanups.
  • Use OS reserved trap 0x89 for IRQ Disable
  • Use OS reserved trap 0x8A for IRQ Enable
  • Add to SPARC CPU supplement documentation

This will result in faster Disable/Enable? code since the
system trap handler does not need to decode which function
the user wants. Besides the IRQ disable/enabled can now
be inline which avoids the caller to take into account that
o0-o7+g1-g4 registers are destroyed by trap handler.

It was also possible to reduce the interrupt trap handler by
five instructions due to this.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • doc/cpu_supplement/sparc.t

    r4081032 rdff1803  
    852852interrupts are fully enabled.  Interrupt requests for interrupts
    853853with priorities less than or equal to the current interrupt mask
    854 level are ignored.
     854level are ignored. Level fifteen (15) is a non-maskable interrupt
     855(NMI), which makes it unsuitable for standard usage since it can
     856affect the real-time behaviour by interrupting critical sections
     857and spinlocks. Disabling traps stops also the NMI interrupt from
     858happening. It can however be used for power-down or other
     859critical events.
    855860
    856861Although RTEMS supports 256 interrupt levels, the
     
    860865unpredictable.
    861866
     867Many LEON SPARC v7/v8 systems features an extended interrupt controller
     868which adds an extra step of interrupt decoding to allow handling of
     869interrupt 16-31. When such an extended interrupt is generated the CPU
     870traps into a specific interrupt trap level 1-14 and software reads out from
     871the interrupt controller which extended interrupt source actually caused the
     872interrupt.
     873
    862874@subsection Disabling of Interrupts by RTEMS
    863875
    864876During the execution of directive calls, critical
    865877sections of code may be executed.  When these sections are
    866 encountered, RTEMS disables interrupts to level seven (15)
    867 before the execution of this section and restores them to the
     878encountered, RTEMS disables interrupts to level fifteen (15)
     879before the execution of the section and restores them to the
    868880previous level upon completion of the section.  RTEMS has been
    869 optimized to insure that interrupts are disabled for less than
     881optimized to ensure that interrupts are disabled for less than
    870882RTEMS_MAXIMUM_DISABLE_PERIOD microseconds on a RTEMS_MAXIMUM_DISABLE_PERIOD_MHZ
    871883Mhz ERC32 with zero wait states.
     
    887899sections.  However, ISRs that make no system calls may safely
    888900execute as non-maskable interrupts.
     901
     902Interrupts are disabled or enabled by performing a system call
     903to the Operating System reserved software traps 9
     904(SPARC_SWTRAP_IRQDIS) or 10 (SPARC_SWTRAP_IRQDIS). The trap is
     905generated by the software trap (Ticc) instruction or indirectly
     906by calling sparc_disable_interrupts() or sparc_enable_interrupts()
     907functions. Disabling interrupts return the previous interrupt level
     908(on trap entry) in register G1 and sets PSR.PIL to 15 to disable
     909all maskable interrupts. The interrupt level can be restored by
     910trapping into the enable interrupt handler with G1 containing the
     911new interrupt level.
    889912
    890913@subsection Interrupt Stack
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