Index: cpukit/score/cpu/no_cpu/Makefile.am
===================================================================
--- cpukit/score/cpu/no_cpu/Makefile.am	(revision bf85b19188f6c4a20cc6cc42a3f32f9ddb92d9ce)
+++ cpukit/score/cpu/no_cpu/Makefile.am	(revision df49c60c9671e4a28e636964d744c1f59fb6cb68)
@@ -1,5 +1,5 @@
-## 
+##
 ## $Id$
-## 
+##
 
 AUTOMAKE_OPTIONS = foreign 1.4
@@ -36,5 +36,6 @@
 TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/rtems$(LIB_VARIANT).o
 
-all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) $(TMPINSTALL_FILES)
+all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \
+    $(TMPINSTALL_FILES)
 
 .PRECIOUS: $(REL)
Index: cpukit/score/cpu/no_cpu/cpu.c
===================================================================
--- cpukit/score/cpu/no_cpu/cpu.c	(revision bf85b19188f6c4a20cc6cc42a3f32f9ddb92d9ce)
+++ cpukit/score/cpu/no_cpu/cpu.c	(revision df49c60c9671e4a28e636964d744c1f59fb6cb68)
@@ -24,4 +24,8 @@
  *    cpu_table       - CPU table to initialize
  *    thread_dispatch - address of disptaching routine
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -60,4 +64,8 @@
  *
  *  _CPU_ISR_Get_level
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
  
@@ -74,4 +82,8 @@
  *
  *  _CPU_ISR_install_raw_handler
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
  
@@ -102,4 +114,8 @@
  *  Output parameters:  NONE
  *
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -131,4 +147,8 @@
  *
  *  _CPU_Install_interrupt_stack
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -152,4 +172,8 @@
  *     also be a problem with other on-chip peripherals.  So use this
  *     hook with caution.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
Index: cpukit/score/cpu/no_cpu/cpu_asm.c
===================================================================
--- cpukit/score/cpu/no_cpu/cpu_asm.c	(revision bf85b19188f6c4a20cc6cc42a3f32f9ddb92d9ce)
+++ cpukit/score/cpu/no_cpu/cpu_asm.c	(revision df49c60c9671e4a28e636964d744c1f59fb6cb68)
@@ -38,4 +38,8 @@
  *  like a (Context_Control_fp *).  The general rule on making this decision
  *  is to avoid writing assembly language.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -57,4 +61,8 @@
  *  like a (Context_Control_fp *).  The general rule on making this decision
  *  is to avoid writing assembly language.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -68,4 +76,8 @@
  *
  *  This routine performs a normal non-FP context switch.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -84,4 +96,8 @@
  *
  *  NOTE: May be unnecessary to reload some registers.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -96,4 +112,7 @@
  *  This routine provides the RTEMS interrupt management.
  *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
Index: cpukit/score/cpu/no_cpu/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/no_cpu/rtems/score/cpu.h	(revision bf85b19188f6c4a20cc6cc42a3f32f9ddb92d9ce)
+++ cpukit/score/cpu/no_cpu/rtems/score/cpu.h	(revision df49c60c9671e4a28e636964d744c1f59fb6cb68)
@@ -43,4 +43,8 @@
  *  _Thread_Dispatch.  If the enable dispatch is inlined, then
  *  one subroutine call is avoided entirely.]
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -63,4 +67,8 @@
  *  code is the longest interrupt disable period in RTEMS.  So it is
  *  necessary to strike a balance when setting this parameter.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -89,4 +97,8 @@
  *  is unclear what that would imply about the interrupt processing
  *  procedure on that CPU.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -106,4 +118,8 @@
  *  is unclear what that would imply about the interrupt processing
  *  procedure on that CPU.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -118,4 +134,8 @@
  *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
  *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -126,4 +146,8 @@
  *  a pointer to the saved interrupt frame (1) or just the vector 
  *  number (0)?
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -144,4 +168,14 @@
  *  which set this to false to indicate that you have an i386 without
  *  an i387 and wish to leave floating point support out of RTEMS.
+ *
+ *  The CPU_SOFTWARE_FP is used to indicate whether or not there
+ *  is software implemented floating point that must be context 
+ *  switched.  The determination of whether or not this applies
+ *  is very tool specific and the state saved/restored is also
+ *  compiler specific.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -151,4 +185,5 @@
 #define CPU_HARDWARE_FP     FALSE
 #endif
+#define CPU_SOFTWARE_FP     FALSE
 
 /*
@@ -166,4 +201,8 @@
  *
  *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -180,4 +219,8 @@
  *  the IDLE task from an interrupt because the floating point context
  *  must be saved as part of the preemption.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -208,4 +251,8 @@
  *  Thus in a system with only one FP task, the FP context will never
  *  be saved or restored.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -231,4 +278,8 @@
  *    2.  CPU dependent (if provided)
  *    3.  generic (if no BSP and no CPU dependent)
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -241,4 +292,8 @@
  *  If TRUE, then the grows upward.
  *  If FALSE, then the grows toward smaller addresses.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -263,4 +318,8 @@
  *         used so it will stay in the cache and used frequently enough
  *         in the executive to justify turning this on.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -270,4 +329,8 @@
  *  Define what is required to specify how the network to host conversion
  *  routines are handled.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -280,4 +343,8 @@
  *  interrupt field of the task mode.  How those bits map to the
  *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -289,4 +356,8 @@
  *  Examples structures include the descriptor tables from the i386
  *  and the processor control structure on the i960ca.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -326,4 +397,8 @@
  *  this is enough information for RTEMS, it is probably not enough for
  *  a debugger such as gdb.  But that is another problem.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -345,4 +420,8 @@
  *  The following table contains the information required to configure
  *  the XXX processor specific parameters.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -365,8 +444,16 @@
  *  Macros to access required entires in the CPU Table are in 
  *  the file rtems/system.h.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
 /*
  *  Macros to access NO_CPU specific additions to the CPU Table
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -378,4 +465,8 @@
  *  _CPU_Initialize and copied into the task's FP context area during
  *  _CPU_Context_Initialize.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -393,4 +484,8 @@
  *  NOTE: These two variables are required if the macro
  *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -406,4 +501,8 @@
  *  can make it easier to invoke that routine at the end of the interrupt
  *  sequence (if a dispatch is necessary).
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -412,4 +511,8 @@
 /*
  *  Nothing prevents the porter from declaring more CPU specific variables.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -421,4 +524,8 @@
  *  area is not defined -- only the size is.  This is usually on
  *  CPUs with a "floating point save context" instruction.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -429,4 +536,8 @@
  *  MPCI receive server thread.  Remember that in a multiprocessor
  *  system this thread must exist and be able to process all directives.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -436,4 +547,8 @@
  *  This defines the number of entries in the ISR_Vector_table managed
  *  by RTEMS.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -444,4 +559,8 @@
  *  Should be large enough to run all RTEMS tests.  This insures
  *  that a "reasonable" small application should not have any problems.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -451,4 +570,8 @@
  *  CPU's worst alignment requirement for data types on a byte boundary.  This
  *  alignment does not take into account the requirements for the stack.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -463,6 +586,18 @@
  *  then this should be set to CPU_ALIGNMENT.
  *
- *  NOTE:  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than CPU_ALIGNMENT.
+ *  NOTE:  This does not have to be a power of 2 although it should be
+ *         a multiple of 2 greater than or equal to 2.  The requirement
+ *         to be a multiple of 2 is because the heap uses the least 
+ *         significant field of the front and back flags to indicate
+ *         that a block is in use or free.  So you do not want any odd
+ *         length blocks really putting length data in that bit.
+ *
+ *         On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
+ *         have to be greater or equal to than CPU_ALIGNMENT to ensure that
+ *         elements allocated from the heap meet all restrictions.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -479,4 +614,8 @@
  *  NOTE:  This does not have to be a power of 2.  It does have to
  *         be greater or equal to than CPU_ALIGNMENT.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -490,4 +629,8 @@
  *
  *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -499,4 +642,8 @@
  *  Disable all interrupts for an RTEMS critical section.  The previous
  *  level is returned in _level.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -510,4 +657,8 @@
  *  This indicates the end of an RTEMS critical section.  The parameter
  *  _level is not modified.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -521,4 +672,8 @@
  *  sections into two or more parts.  The parameter _level is not
  * modified.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -538,4 +693,8 @@
  *
  *  The get routine usually must be implemented as a subroutine.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -569,4 +728,8 @@
  *        FPU may be easily disabled by software such as on the SPARC
  *        where the PSR contains an enable FPU bit.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -584,4 +747,8 @@
  *  not work if restarting self conflicts with the stack frame
  *  assumptions of restoring a context.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -601,4 +768,8 @@
  *  a "dump context" instruction which could fill in from high to low
  *  or low to high based on the whim of the CPU designers.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -616,4 +787,8 @@
  *  Other models include (1) not doing anything, and (2) putting
  *  a "null FP status word" in the correct place in the FP context.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -631,4 +806,8 @@
  *  location or a register, optionally disables interrupts, and
  *  halts/stops the CPU.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -694,4 +873,8 @@
  *    where bit_set_table[ 16 ] has values which indicate the first
  *      bit set
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -714,4 +897,8 @@
  *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
  *  for that routine.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -728,4 +915,8 @@
  *  a major or minor component of a priority.  See the discussion
  *  for that routine.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -745,4 +936,8 @@
  *
  *  This routine performs CPU dependent initialization.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -757,4 +952,8 @@
  *  This routine installs a "raw" interrupt handler directly into the 
  *  processor's vector table.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
  
@@ -769,4 +968,8 @@
  *
  *  This routine installs an interrupt vector.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -784,4 +987,8 @@
  *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
  *         is TRUE.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -795,4 +1002,8 @@
  *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
  *         is TRUE.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -803,4 +1014,8 @@
  *
  *  This routine switches from the run context to the heir context.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -817,4 +1032,8 @@
  *
  *  NOTE: May be unnecessary to reload some registers.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -827,4 +1046,8 @@
  *
  *  This routine saves the floating point context passed to it.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -837,4 +1060,8 @@
  *
  *  This routine restores the floating point context passed to it.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
 
@@ -861,4 +1088,8 @@
  *  endianness for ALL fetches -- both code and data -- so the code
  *  will be fetched incorrectly.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
  */
  
Index: cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h
===================================================================
--- cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h	(revision bf85b19188f6c4a20cc6cc42a3f32f9ddb92d9ce)
+++ cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h	(revision df49c60c9671e4a28e636964d744c1f59fb6cb68)
@@ -1,5 +1,5 @@
 /*  no_cpu.h
  *
- *  This file is an example (i.e. "no CPU") of the file which is
+ *  This file is an example (i.e. no CPU) of the file which is
  *  created for each CPU family port of RTEMS.
  *
@@ -25,14 +25,26 @@
 /*
  *  This file contains the information required to build
- *  RTEMS for a particular member of the "no cpu"
- *  family when executing in protected mode.  It does
- *  this by setting variables to indicate which implementation
- *  dependent features are present in a particular member
- *  of the family.
+ *  RTEMS for a particular member of the no CPU family.
+ *  It does this by setting variables to indicate which
+ *  implementation dependent features are present in a particular
+ *  member of the family.
+ *
+ *  This is a good place to list all the known CPU models
+ *  that this port supports and which RTEMS CPU model they correspond
+ *  to.
  */
  
-#if defined(no_cpu)
+#if defined(rtems_multilib)
+/*
+ *  Figure out all CPU Model Feature Flags based upon compiler 
+ *  predefines. 
+ */
+
+#define CPU_MODEL_NAME  "rtems_multilib"
+#define NOCPU_HAS_FPU     1
+
+#elif defined(no_cpu)
  
-#define CPU_MODEL_NAME  "no_cpu"
+#define CPU_MODEL_NAME  "no_cpu_model"
 #define NOCPU_HAS_FPU     1
  
