Changeset df49c60 in rtems for cpukit/score/cpu/no_cpu


Ignore:
Timestamp:
Jun 12, 2000, 3:00:15 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
edeed26
Parents:
0ab65474
Message:

Merged from 4.5.0-beta3a

Location:
cpukit/score/cpu/no_cpu
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/no_cpu/Makefile.am

    r0ab65474 rdf49c60  
    1 ## 
     1##
    22## $Id$
    3 ## 
     3##
    44
    55AUTOMAKE_OPTIONS = foreign 1.4
     
    3636TMPINSTALL_FILES += $(PROJECT_RELEASE)/lib/rtems$(LIB_VARIANT).o
    3737
    38 all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) $(TMPINSTALL_FILES)
     38all-local: $(ARCH) $(PREINSTALL_FILES) $(rtems_cpu_rel_OBJECTS) $(REL) \
     39    $(TMPINSTALL_FILES)
    3940
    4041.PRECIOUS: $(REL)
  • cpukit/score/cpu/no_cpu/cpu.c

    r0ab65474 rdf49c60  
    2424 *    cpu_table       - CPU table to initialize
    2525 *    thread_dispatch - address of disptaching routine
     26 *
     27 *  NO_CPU Specific Information:
     28 *
     29 *  XXX document implementation including references if appropriate
    2630 */
    2731
     
    6064 *
    6165 *  _CPU_ISR_Get_level
     66 *
     67 *  NO_CPU Specific Information:
     68 *
     69 *  XXX document implementation including references if appropriate
    6270 */
    6371 
     
    7482 *
    7583 *  _CPU_ISR_install_raw_handler
     84 *
     85 *  NO_CPU Specific Information:
     86 *
     87 *  XXX document implementation including references if appropriate
    7688 */
    7789 
     
    102114 *  Output parameters:  NONE
    103115 *
     116 *
     117 *  NO_CPU Specific Information:
     118 *
     119 *  XXX document implementation including references if appropriate
    104120 */
    105121
     
    131147 *
    132148 *  _CPU_Install_interrupt_stack
     149 *
     150 *  NO_CPU Specific Information:
     151 *
     152 *  XXX document implementation including references if appropriate
    133153 */
    134154
     
    152172 *     also be a problem with other on-chip peripherals.  So use this
    153173 *     hook with caution.
     174 *
     175 *  NO_CPU Specific Information:
     176 *
     177 *  XXX document implementation including references if appropriate
    154178 */
    155179
  • cpukit/score/cpu/no_cpu/cpu_asm.c

    r0ab65474 rdf49c60  
    3838 *  like a (Context_Control_fp *).  The general rule on making this decision
    3939 *  is to avoid writing assembly language.
     40 *
     41 *  NO_CPU Specific Information:
     42 *
     43 *  XXX document implementation including references if appropriate
    4044 */
    4145
     
    5761 *  like a (Context_Control_fp *).  The general rule on making this decision
    5862 *  is to avoid writing assembly language.
     63 *
     64 *  NO_CPU Specific Information:
     65 *
     66 *  XXX document implementation including references if appropriate
    5967 */
    6068
     
    6876 *
    6977 *  This routine performs a normal non-FP context switch.
     78 *
     79 *  NO_CPU Specific Information:
     80 *
     81 *  XXX document implementation including references if appropriate
    7082 */
    7183
     
    8496 *
    8597 *  NOTE: May be unnecessary to reload some registers.
     98 *
     99 *  NO_CPU Specific Information:
     100 *
     101 *  XXX document implementation including references if appropriate
    86102 */
    87103
     
    96112 *  This routine provides the RTEMS interrupt management.
    97113 *
     114 *  NO_CPU Specific Information:
     115 *
     116 *  XXX document implementation including references if appropriate
    98117 */
    99118
  • cpukit/score/cpu/no_cpu/rtems/score/cpu.h

    r0ab65474 rdf49c60  
    4343 *  _Thread_Dispatch.  If the enable dispatch is inlined, then
    4444 *  one subroutine call is avoided entirely.]
     45 *
     46 *  NO_CPU Specific Information:
     47 *
     48 *  XXX document implementation including references if appropriate
    4549 */
    4650
     
    6367 *  code is the longest interrupt disable period in RTEMS.  So it is
    6468 *  necessary to strike a balance when setting this parameter.
     69 *
     70 *  NO_CPU Specific Information:
     71 *
     72 *  XXX document implementation including references if appropriate
    6573 */
    6674
     
    8997 *  is unclear what that would imply about the interrupt processing
    9098 *  procedure on that CPU.
     99 *
     100 *  NO_CPU Specific Information:
     101 *
     102 *  XXX document implementation including references if appropriate
    91103 */
    92104
     
    106118 *  is unclear what that would imply about the interrupt processing
    107119 *  procedure on that CPU.
     120 *
     121 *  NO_CPU Specific Information:
     122 *
     123 *  XXX document implementation including references if appropriate
    108124 */
    109125
     
    118134 *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE
    119135 *  or CPU_INSTALL_HARDWARE_INTERRUPT_STACK is TRUE.
     136 *
     137 *  NO_CPU Specific Information:
     138 *
     139 *  XXX document implementation including references if appropriate
    120140 */
    121141
     
    126146 *  a pointer to the saved interrupt frame (1) or just the vector
    127147 *  number (0)?
     148 *
     149 *  NO_CPU Specific Information:
     150 *
     151 *  XXX document implementation including references if appropriate
    128152 */
    129153
     
    144168 *  which set this to false to indicate that you have an i386 without
    145169 *  an i387 and wish to leave floating point support out of RTEMS.
     170 *
     171 *  The CPU_SOFTWARE_FP is used to indicate whether or not there
     172 *  is software implemented floating point that must be context
     173 *  switched.  The determination of whether or not this applies
     174 *  is very tool specific and the state saved/restored is also
     175 *  compiler specific.
     176 *
     177 *  NO_CPU Specific Information:
     178 *
     179 *  XXX document implementation including references if appropriate
    146180 */
    147181
     
    151185#define CPU_HARDWARE_FP     FALSE
    152186#endif
     187#define CPU_SOFTWARE_FP     FALSE
    153188
    154189/*
     
    166201 *
    167202 *  If CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
     203 *
     204 *  NO_CPU Specific Information:
     205 *
     206 *  XXX document implementation including references if appropriate
    168207 */
    169208
     
    180219 *  the IDLE task from an interrupt because the floating point context
    181220 *  must be saved as part of the preemption.
     221 *
     222 *  NO_CPU Specific Information:
     223 *
     224 *  XXX document implementation including references if appropriate
    182225 */
    183226
     
    208251 *  Thus in a system with only one FP task, the FP context will never
    209252 *  be saved or restored.
     253 *
     254 *  NO_CPU Specific Information:
     255 *
     256 *  XXX document implementation including references if appropriate
    210257 */
    211258
     
    231278 *    2.  CPU dependent (if provided)
    232279 *    3.  generic (if no BSP and no CPU dependent)
     280 *
     281 *  NO_CPU Specific Information:
     282 *
     283 *  XXX document implementation including references if appropriate
    233284 */
    234285
     
    241292 *  If TRUE, then the grows upward.
    242293 *  If FALSE, then the grows toward smaller addresses.
     294 *
     295 *  NO_CPU Specific Information:
     296 *
     297 *  XXX document implementation including references if appropriate
    243298 */
    244299
     
    263318 *         used so it will stay in the cache and used frequently enough
    264319 *         in the executive to justify turning this on.
     320 *
     321 *  NO_CPU Specific Information:
     322 *
     323 *  XXX document implementation including references if appropriate
    265324 */
    266325
     
    270329 *  Define what is required to specify how the network to host conversion
    271330 *  routines are handled.
     331 *
     332 *  NO_CPU Specific Information:
     333 *
     334 *  XXX document implementation including references if appropriate
    272335 */
    273336
     
    280343 *  interrupt field of the task mode.  How those bits map to the
    281344 *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
     345 *
     346 *  NO_CPU Specific Information:
     347 *
     348 *  XXX document implementation including references if appropriate
    282349 */
    283350
     
    289356 *  Examples structures include the descriptor tables from the i386
    290357 *  and the processor control structure on the i960ca.
     358 *
     359 *  NO_CPU Specific Information:
     360 *
     361 *  XXX document implementation including references if appropriate
    291362 */
    292363
     
    326397 *  this is enough information for RTEMS, it is probably not enough for
    327398 *  a debugger such as gdb.  But that is another problem.
     399 *
     400 *  NO_CPU Specific Information:
     401 *
     402 *  XXX document implementation including references if appropriate
    328403 */
    329404
     
    345420 *  The following table contains the information required to configure
    346421 *  the XXX processor specific parameters.
     422 *
     423 *  NO_CPU Specific Information:
     424 *
     425 *  XXX document implementation including references if appropriate
    347426 */
    348427
     
    365444 *  Macros to access required entires in the CPU Table are in
    366445 *  the file rtems/system.h.
     446 *
     447 *  NO_CPU Specific Information:
     448 *
     449 *  XXX document implementation including references if appropriate
    367450 */
    368451
    369452/*
    370453 *  Macros to access NO_CPU specific additions to the CPU Table
     454 *
     455 *  NO_CPU Specific Information:
     456 *
     457 *  XXX document implementation including references if appropriate
    371458 */
    372459
     
    378465 *  _CPU_Initialize and copied into the task's FP context area during
    379466 *  _CPU_Context_Initialize.
     467 *
     468 *  NO_CPU Specific Information:
     469 *
     470 *  XXX document implementation including references if appropriate
    380471 */
    381472
     
    393484 *  NOTE: These two variables are required if the macro
    394485 *        CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
     486 *
     487 *  NO_CPU Specific Information:
     488 *
     489 *  XXX document implementation including references if appropriate
    395490 */
    396491
     
    406501 *  can make it easier to invoke that routine at the end of the interrupt
    407502 *  sequence (if a dispatch is necessary).
     503 *
     504 *  NO_CPU Specific Information:
     505 *
     506 *  XXX document implementation including references if appropriate
    408507 */
    409508
     
    412511/*
    413512 *  Nothing prevents the porter from declaring more CPU specific variables.
     513 *
     514 *  NO_CPU Specific Information:
     515 *
     516 *  XXX document implementation including references if appropriate
    414517 */
    415518
     
    421524 *  area is not defined -- only the size is.  This is usually on
    422525 *  CPUs with a "floating point save context" instruction.
     526 *
     527 *  NO_CPU Specific Information:
     528 *
     529 *  XXX document implementation including references if appropriate
    423530 */
    424531
     
    429536 *  MPCI receive server thread.  Remember that in a multiprocessor
    430537 *  system this thread must exist and be able to process all directives.
     538 *
     539 *  NO_CPU Specific Information:
     540 *
     541 *  XXX document implementation including references if appropriate
    431542 */
    432543
     
    436547 *  This defines the number of entries in the ISR_Vector_table managed
    437548 *  by RTEMS.
     549 *
     550 *  NO_CPU Specific Information:
     551 *
     552 *  XXX document implementation including references if appropriate
    438553 */
    439554
     
    444559 *  Should be large enough to run all RTEMS tests.  This insures
    445560 *  that a "reasonable" small application should not have any problems.
     561 *
     562 *  NO_CPU Specific Information:
     563 *
     564 *  XXX document implementation including references if appropriate
    446565 */
    447566
     
    451570 *  CPU's worst alignment requirement for data types on a byte boundary.  This
    452571 *  alignment does not take into account the requirements for the stack.
     572 *
     573 *  NO_CPU Specific Information:
     574 *
     575 *  XXX document implementation including references if appropriate
    453576 */
    454577
     
    463586 *  then this should be set to CPU_ALIGNMENT.
    464587 *
    465  *  NOTE:  This does not have to be a power of 2.  It does have to
    466  *         be greater or equal to than CPU_ALIGNMENT.
     588 *  NOTE:  This does not have to be a power of 2 although it should be
     589 *         a multiple of 2 greater than or equal to 2.  The requirement
     590 *         to be a multiple of 2 is because the heap uses the least
     591 *         significant field of the front and back flags to indicate
     592 *         that a block is in use or free.  So you do not want any odd
     593 *         length blocks really putting length data in that bit.
     594 *
     595 *         On byte oriented architectures, CPU_HEAP_ALIGNMENT normally will
     596 *         have to be greater or equal to than CPU_ALIGNMENT to ensure that
     597 *         elements allocated from the heap meet all restrictions.
     598 *
     599 *  NO_CPU Specific Information:
     600 *
     601 *  XXX document implementation including references if appropriate
    467602 */
    468603
     
    479614 *  NOTE:  This does not have to be a power of 2.  It does have to
    480615 *         be greater or equal to than CPU_ALIGNMENT.
     616 *
     617 *  NO_CPU Specific Information:
     618 *
     619 *  XXX document implementation including references if appropriate
    481620 */
    482621
     
    490629 *
    491630 *  NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
     631 *
     632 *  NO_CPU Specific Information:
     633 *
     634 *  XXX document implementation including references if appropriate
    492635 */
    493636
     
    499642 *  Disable all interrupts for an RTEMS critical section.  The previous
    500643 *  level is returned in _level.
     644 *
     645 *  NO_CPU Specific Information:
     646 *
     647 *  XXX document implementation including references if appropriate
    501648 */
    502649
     
    510657 *  This indicates the end of an RTEMS critical section.  The parameter
    511658 *  _level is not modified.
     659 *
     660 *  NO_CPU Specific Information:
     661 *
     662 *  XXX document implementation including references if appropriate
    512663 */
    513664
     
    521672 *  sections into two or more parts.  The parameter _level is not
    522673 * modified.
     674 *
     675 *  NO_CPU Specific Information:
     676 *
     677 *  XXX document implementation including references if appropriate
    523678 */
    524679
     
    538693 *
    539694 *  The get routine usually must be implemented as a subroutine.
     695 *
     696 *  NO_CPU Specific Information:
     697 *
     698 *  XXX document implementation including references if appropriate
    540699 */
    541700
     
    569728 *        FPU may be easily disabled by software such as on the SPARC
    570729 *        where the PSR contains an enable FPU bit.
     730 *
     731 *  NO_CPU Specific Information:
     732 *
     733 *  XXX document implementation including references if appropriate
    571734 */
    572735
     
    584747 *  not work if restarting self conflicts with the stack frame
    585748 *  assumptions of restoring a context.
     749 *
     750 *  NO_CPU Specific Information:
     751 *
     752 *  XXX document implementation including references if appropriate
    586753 */
    587754
     
    601768 *  a "dump context" instruction which could fill in from high to low
    602769 *  or low to high based on the whim of the CPU designers.
     770 *
     771 *  NO_CPU Specific Information:
     772 *
     773 *  XXX document implementation including references if appropriate
    603774 */
    604775
     
    616787 *  Other models include (1) not doing anything, and (2) putting
    617788 *  a "null FP status word" in the correct place in the FP context.
     789 *
     790 *  NO_CPU Specific Information:
     791 *
     792 *  XXX document implementation including references if appropriate
    618793 */
    619794
     
    631806 *  location or a register, optionally disables interrupts, and
    632807 *  halts/stops the CPU.
     808 *
     809 *  NO_CPU Specific Information:
     810 *
     811 *  XXX document implementation including references if appropriate
    633812 */
    634813
     
    694873 *    where bit_set_table[ 16 ] has values which indicate the first
    695874 *      bit set
     875 *
     876 *  NO_CPU Specific Information:
     877 *
     878 *  XXX document implementation including references if appropriate
    696879 */
    697880
     
    714897 *  as searched by _CPU_Bitfield_Find_first_bit().  See the discussion
    715898 *  for that routine.
     899 *
     900 *  NO_CPU Specific Information:
     901 *
     902 *  XXX document implementation including references if appropriate
    716903 */
    717904
     
    728915 *  a major or minor component of a priority.  See the discussion
    729916 *  for that routine.
     917 *
     918 *  NO_CPU Specific Information:
     919 *
     920 *  XXX document implementation including references if appropriate
    730921 */
    731922
     
    745936 *
    746937 *  This routine performs CPU dependent initialization.
     938 *
     939 *  NO_CPU Specific Information:
     940 *
     941 *  XXX document implementation including references if appropriate
    747942 */
    748943
     
    757952 *  This routine installs a "raw" interrupt handler directly into the
    758953 *  processor's vector table.
     954 *
     955 *  NO_CPU Specific Information:
     956 *
     957 *  XXX document implementation including references if appropriate
    759958 */
    760959 
     
    769968 *
    770969 *  This routine installs an interrupt vector.
     970 *
     971 *  NO_CPU Specific Information:
     972 *
     973 *  XXX document implementation including references if appropriate
    771974 */
    772975
     
    784987 *  NOTE:  It need only be provided if CPU_HAS_HARDWARE_INTERRUPT_STACK
    785988 *         is TRUE.
     989 *
     990 *  NO_CPU Specific Information:
     991 *
     992 *  XXX document implementation including references if appropriate
    786993 */
    787994
     
    7951002 *  NOTE:  It need only be provided if CPU_PROVIDES_IDLE_THREAD_BODY
    7961003 *         is TRUE.
     1004 *
     1005 *  NO_CPU Specific Information:
     1006 *
     1007 *  XXX document implementation including references if appropriate
    7971008 */
    7981009
     
    8031014 *
    8041015 *  This routine switches from the run context to the heir context.
     1016 *
     1017 *  NO_CPU Specific Information:
     1018 *
     1019 *  XXX document implementation including references if appropriate
    8051020 */
    8061021
     
    8171032 *
    8181033 *  NOTE: May be unnecessary to reload some registers.
     1034 *
     1035 *  NO_CPU Specific Information:
     1036 *
     1037 *  XXX document implementation including references if appropriate
    8191038 */
    8201039
     
    8271046 *
    8281047 *  This routine saves the floating point context passed to it.
     1048 *
     1049 *  NO_CPU Specific Information:
     1050 *
     1051 *  XXX document implementation including references if appropriate
    8291052 */
    8301053
     
    8371060 *
    8381061 *  This routine restores the floating point context passed to it.
     1062 *
     1063 *  NO_CPU Specific Information:
     1064 *
     1065 *  XXX document implementation including references if appropriate
    8391066 */
    8401067
     
    8611088 *  endianness for ALL fetches -- both code and data -- so the code
    8621089 *  will be fetched incorrectly.
     1090 *
     1091 *  NO_CPU Specific Information:
     1092 *
     1093 *  XXX document implementation including references if appropriate
    8631094 */
    8641095 
  • cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h

    r0ab65474 rdf49c60  
    11/*  no_cpu.h
    22 *
    3  *  This file is an example (i.e. "no CPU") of the file which is
     3 *  This file is an example (i.e. no CPU) of the file which is
    44 *  created for each CPU family port of RTEMS.
    55 *
     
    2525/*
    2626 *  This file contains the information required to build
    27  *  RTEMS for a particular member of the "no cpu"
    28  *  family when executing in protected mode.  It does
    29  *  this by setting variables to indicate which implementation
    30  *  dependent features are present in a particular member
    31  *  of the family.
     27 *  RTEMS for a particular member of the no CPU family.
     28 *  It does this by setting variables to indicate which
     29 *  implementation dependent features are present in a particular
     30 *  member of the family.
     31 *
     32 *  This is a good place to list all the known CPU models
     33 *  that this port supports and which RTEMS CPU model they correspond
     34 *  to.
    3235 */
    3336 
    34 #if defined(no_cpu)
     37#if defined(rtems_multilib)
     38/*
     39 *  Figure out all CPU Model Feature Flags based upon compiler
     40 *  predefines.
     41 */
     42
     43#define CPU_MODEL_NAME  "rtems_multilib"
     44#define NOCPU_HAS_FPU     1
     45
     46#elif defined(no_cpu)
    3547 
    36 #define CPU_MODEL_NAME  "no_cpu"
     48#define CPU_MODEL_NAME  "no_cpu_model"
    3749#define NOCPU_HAS_FPU     1
    3850 
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