Changeset de62e5d8 in rtems


Ignore:
Timestamp:
Aug 18, 2014, 9:06:46 PM (6 years ago)
Author:
Hesham ALMatary <heshamelmatary@…>
Branches:
4.11, 5, master
Children:
3654667f
Parents:
1a2d349
git-author:
Hesham ALMatary <heshamelmatary@…> (08/18/14 21:06:46)
git-committer:
Joel Sherrill <joel.sherrill@…> (08/18/14 22:10:00)
Message:

Add or1k tick timer register definitions

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/or1k/rtems/score/or1k-utility.h

    r1a2d349 rde62e5d8  
    259259#define CPU_OR1K_SPR_SR_CID   (F << CPU_OR1K_SPR_SR_SHAMT_CID)
    260260
     261/* Tick timer configuration bits */
     262#define CPU_OR1K_SPR_TTMR_SHAMT_IP    28
     263#define CPU_OR1K_SPR_TTMR_SHAMT_IE    29
     264#define CPU_OR1K_SPR_TTMR_SHAMT_MODE  30
     265
     266#define CPU_OR1K_SPR_TTMR_TP_MASK       (0x0FFFFFFF)
     267#define CPU_OR1K_SPR_TTMR_IP            (1 << CPU_OR1K_SPR_TTMR_SHAMT_IP)
     268#define CPU_OR1K_SPR_TTMR_IE            (1 << CPU_OR1K_SPR_TTMR_SHAMT_IE)
     269#define CPU_OR1K_SPR_TTMR_MODE_RESTART  (1 << CPU_OR1K_SPR_TTMR_SHAMT_MODE)
     270#define CPU_OR1K_SPR_TTMR_MODE_ONE_SHOT (2 << CPU_OR1K_SPR_TTMR_SHAMT_MODE)
     271#define CPU_OR1K_SPR_TTMR_MODE_CONT     (3 << CPU_OR1K_SPR_TTMR_SHAMT_MODE)
     272
    261273/* Power management register bits */
     274
     275/* Shift amount macros for bit positions in Power Management register */
    262276#define CPU_OR1K_SPR_PMR_SHAMT_SDF  0
    263277#define CPU_OR1K_SPR_PMR_SHAMT_DME  4
     
    271285#define CPU_OR1K_SPR_PMR_DCGE (1 << CPU_OR1K_SPR_PMR_SHAMT_DCGE)
    272286#define CPU_OR1K_SPR_PMR_SUME (1 << CPU_OR1K_SPR_PMR_SHAMT_SUME)
    273 
    274 /* Shift amount macros for bit positions in Power Management register */
    275287
    276288#ifndef ASM
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