Changeset ddc95ab0 in rtems


Ignore:
Timestamp:
Jun 15, 2018, 10:54:32 AM (18 months ago)
Author:
Martin Aberg <maberg@…>
Branches:
master
Children:
0aae151
Parents:
56a7540
git-author:
Martin Aberg <maberg@…> (06/15/18 10:54:32)
git-committer:
Daniel Hellstrom <daniel@…> (09/20/18 10:48:32)
Message:

leon, l2cache: workaround for scrubber

This is a workaround for a L2CACHE scrubber corner case described in GR740
User's Manual, Version 1.10, section 43.2.30.

The issue affects some version of the L2CACHE. However, since the performance
impact of the workaround is marginal, special device probing logic has been
avoided. In addition, this update does not affect users who enable the L2CACHE
and scrubber before RTEMS is started.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • bsps/sparc/shared/l2c/l2c.c

    r56a7540 rddc95ab0  
    242242 * L2CACHE ACCESS CONTROL register fields
    243243 */
     244#define L2C_ACCCTRL_DSC (0x1 << L2C_ACCCTRL_DSC_BIT)
     245#define L2C_ACCCTRL_SH (0x1 << L2C_ACCCTRL_SH_BIT)
    244246#define L2C_ACCCTRL_SPLITQ (0x1 << L2C_ACCCTRL_SPLITQ_BIT)
    245247#define L2C_ACCCTRL_NHM (0x1 << L2C_ACCCTRL_NHM_BIT)
     
    252254#define L2C_ACCCTRL_SPLIT (0x1 << L2C_ACCCTRL_SPLIT_BIT)
    253255
     256#define L2C_ACCCTRL_DSC_BIT 14
     257#define L2C_ACCCTRL_SH_BIT 13
    254258#define L2C_ACCCTRL_SPLITQ_BIT 10
    255259#define L2C_ACCCTRL_NHM_BIT 9
     
    673677        struct l2cache_priv *priv = l2cachepriv;
    674678
     679        unsigned int accc = REG_READ(&priv->regs->access_control);
     680        REG_WRITE(&priv->regs->access_control,
     681                        accc | L2C_ACCCTRL_DSC | L2C_ACCCTRL_SH);
     682
    675683        unsigned int ctrl = REG_READ(&priv->regs->scrub_control_status);
    676684        REG_WRITE(&priv->regs->scrub_delay,
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