Changeset dda78f43 in rtems


Ignore:
Timestamp:
May 28, 2014, 12:47:01 PM (5 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
32c8960
Parents:
5fd4e35f
git-author:
Ralf Kirchner <ralf.kirchner@…> (05/28/14 12:47:01)
git-committer:
Sebastian Huber <sebastian.huber@…> (05/28/14 12:59:01)
Message:

bsp/altera-vyclone-v: Broadcast cache maintenances

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/altera-cyclone-v/startup/bspstarthooks.c

    r5fd4e35f rdda78f43  
    133133    /* Enable cache coherency support for this processor */
    134134    uint32_t actlr = arm_cp15_get_auxiliary_control();
    135     actlr |= ARM_CORTEX_A9_ACTL_SMP;
     135    actlr |= ARM_CORTEX_A9_ACTL_SMP | ARM_CORTEX_A9_ACTL_FW;
    136136    arm_cp15_set_auxiliary_control(actlr);
    137137#endif
     
    140140      arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xF);
    141141    }
    142    
     142
    143143    setup_mmu_and_cache( cpu_id );
    144    
     144
    145145#ifdef RTEMS_SMP
    146146    if (cpu_id != 0) {
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