Changeset dcaea71 in rtems


Ignore:
Timestamp:
Aug 15, 2018, 10:26:13 AM (2 years ago)
Author:
Christian Mauderer <christian.mauderer@…>
Branches:
5, master
Children:
2cd3716
Parents:
da8b12b
git-author:
Christian Mauderer <christian.mauderer@…> (08/15/18 10:26:13)
git-committer:
Joel Sherrill <joel@…> (08/15/18 14:48:31)
Message:

dev/sc16is752: Add name space for field names.

The field names for the registers generated a name collision (MSR_RI on
the power pc). This patch adds a SC16IS752_ prefix for all field names.

Closes #3501.

Location:
cpukit/dev/serial
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • cpukit/dev/serial/sc16is752-regs.h

    rda8b12b rdcaea71  
    5353
    5454/* FCR */
    55 #define FCR_FIFO_EN        0x01
    56 #define FCR_RX_FIFO_RST    0x02
    57 #define FCR_TX_FIFO_RST    0x04
    58 #define FCR_TX_FIFO_TRG_8  0x00
    59 #define FCR_TX_FIFO_TRG_16 0x10
    60 #define FCR_TX_FIFO_TRG_32 0x20
    61 #define FCR_TX_FIFO_TRG_56 0x30
    62 #define FCR_RX_FIFO_TRG_8  0x00
    63 #define FCR_RX_FIFO_TRG_16 0x40
    64 #define FCR_RX_FIFO_TRG_56 0x80
    65 #define FCR_RX_FIFO_TRG_60 0xc0
     55#define SC16IS752_FCR_FIFO_EN        0x01
     56#define SC16IS752_FCR_RX_FIFO_RST    0x02
     57#define SC16IS752_FCR_TX_FIFO_RST    0x04
     58#define SC16IS752_FCR_TX_FIFO_TRG_8  0x00
     59#define SC16IS752_FCR_TX_FIFO_TRG_16 0x10
     60#define SC16IS752_FCR_TX_FIFO_TRG_32 0x20
     61#define SC16IS752_FCR_TX_FIFO_TRG_56 0x30
     62#define SC16IS752_FCR_RX_FIFO_TRG_8  0x00
     63#define SC16IS752_FCR_RX_FIFO_TRG_16 0x40
     64#define SC16IS752_FCR_RX_FIFO_TRG_56 0x80
     65#define SC16IS752_FCR_RX_FIFO_TRG_60 0xc0
    6666
    6767/* EFCR */
    68 #define EFCR_RS485_ENABLE (1u << 0)
    69 #define EFCR_RX_DISABLE (1u << 1)
    70 #define EFCR_TX_DISABLE (1u << 2)
     68#define SC16IS752_EFCR_RS485_ENABLE (1u << 0)
     69#define SC16IS752_EFCR_RX_DISABLE (1u << 1)
     70#define SC16IS752_EFCR_TX_DISABLE (1u << 2)
    7171
    7272/* IER */
    73 #define IER_RHR (1u << 0)
    74 #define IER_THR (1u << 1)
    75 #define IER_RECEIVE_LINE_STATUS (1u << 2)
    76 #define IER_MODEM_STATUS (1u << 3)
    77 #define IER_SLEEP_MODE (1u << 4)
    78 #define IER_XOFF (1u << 5)
    79 #define IER_RTS (1u << 6)
    80 #define IER_CTS (1u << 7)
     73#define SC16IS752_IER_RHR (1u << 0)
     74#define SC16IS752_IER_THR (1u << 1)
     75#define SC16IS752_IER_RECEIVE_LINE_STATUS (1u << 2)
     76#define SC16IS752_IER_MODEM_STATUS (1u << 3)
     77#define SC16IS752_IER_SLEEP_MODE (1u << 4)
     78#define SC16IS752_IER_XOFF (1u << 5)
     79#define SC16IS752_IER_RTS (1u << 6)
     80#define SC16IS752_IER_CTS (1u << 7)
    8181
    8282/* IIR */
    83 #define IIR_TX_INTERRUPT (1u << 1)
    84 #define IIR_RX_INTERRUPT (1u << 2)
     83#define SC16IS752_IIR_TX_INTERRUPT (1u << 1)
     84#define SC16IS752_IIR_RX_INTERRUPT (1u << 2)
    8585
    8686/* LCR */
    87 #define LCR_CHRL_5_BIT (0u << 1) | (0u << 0)
    88 #define LCR_CHRL_6_BIT (0u << 1) | (1u << 0)
    89 #define LCR_CHRL_7_BIT (1u << 1) | (0u << 0)
    90 #define LCR_CHRL_8_BIT (1u << 1) | (1u << 0)
    91 #define LCR_2_STOP_BIT (1u << 2)
    92 #define LCR_SET_PARITY (1u << 3)
    93 #define LCR_EVEN_PARITY (1u << 4)
    94 #define LCR_ENABLE_DIVISOR (1u << 7)
     87#define SC16IS752_LCR_CHRL_5_BIT (0u << 1) | (0u << 0)
     88#define SC16IS752_LCR_CHRL_6_BIT (0u << 1) | (1u << 0)
     89#define SC16IS752_LCR_CHRL_7_BIT (1u << 1) | (0u << 0)
     90#define SC16IS752_LCR_CHRL_8_BIT (1u << 1) | (1u << 0)
     91#define SC16IS752_LCR_2_STOP_BIT (1u << 2)
     92#define SC16IS752_LCR_SET_PARITY (1u << 3)
     93#define SC16IS752_LCR_EVEN_PARITY (1u << 4)
     94#define SC16IS752_LCR_ENABLE_DIVISOR (1u << 7)
    9595
    9696/* LSR */
    97 #define LSR_TXEMPTY (1u << 5)
    98 #define LSR_RXRDY (1u << 0)
    99 #define LSR_ERROR_BITS (7u << 2)
     97#define SC16IS752_LSR_TXEMPTY (1u << 5)
     98#define SC16IS752_LSR_RXRDY (1u << 0)
     99#define SC16IS752_LSR_ERROR_BITS (7u << 2)
    100100
    101101/* MCR */
    102 #define MCR_DTR             (1u << 0)
    103 #define MCR_RTS             (1u << 1)
    104 #define MCR_TCR_TLR         (1u << 2)
    105 #define MCR_LOOPBACK        (1u << 4)
    106 #define MCR_XON_ANY         (1u << 5)
    107 #define MCR_IRDA_ENABLE     (1u << 6)
    108 #define MCR_PRESCALE_NEEDED (1u << 7)
     102#define SC16IS752_MCR_DTR             (1u << 0)
     103#define SC16IS752_MCR_RTS             (1u << 1)
     104#define SC16IS752_MCR_TCR_TLR         (1u << 2)
     105#define SC16IS752_MCR_LOOPBACK        (1u << 4)
     106#define SC16IS752_MCR_XON_ANY         (1u << 5)
     107#define SC16IS752_MCR_IRDA_ENABLE     (1u << 6)
     108#define SC16IS752_MCR_PRESCALE_NEEDED (1u << 7)
    109109
    110110/* MSR */
    111 #define MSR_dCTS (1u << 0)
    112 #define MSR_dDSR (1u << 1)
    113 #define MSR_dRI  (1u << 2)
    114 #define MSR_dCD  (1u << 3)
    115 #define MSR_CTS  (1u << 4)
    116 #define MSR_DSR  (1u << 5)
    117 #define MSR_RI   (1u << 6)
    118 #define MSR_CD   (1u << 7)
     111#define SC16IS752_MSR_dCTS (1u << 0)
     112#define SC16IS752_MSR_dDSR (1u << 1)
     113#define SC16IS752_MSR_dRI  (1u << 2)
     114#define SC16IS752_MSR_dCD  (1u << 3)
     115#define SC16IS752_MSR_CTS  (1u << 4)
     116#define SC16IS752_MSR_DSR  (1u << 5)
     117#define SC16IS752_MSR_RI   (1u << 6)
     118#define SC16IS752_MSR_CD   (1u << 7)
    119119
    120120/* EFR */
    121 #define EFR_ENHANCED_FUNC_ENABLE (1u << 4)
    122 #define EFR_SPECIAL_CHAR_DETECT (1u << 5)
    123 #define EFR_RTS_FLOW_CTRL_EN (1u << 6)
    124 #define EFR_CTS_FLOW_CTRL_EN (1u << 7)
     121#define SC16IS752_EFR_ENHANCED_FUNC_ENABLE (1u << 4)
     122#define SC16IS752_EFR_SPECIAL_CHAR_DETECT (1u << 5)
     123#define SC16IS752_EFR_RTS_FLOW_CTRL_EN (1u << 6)
     124#define SC16IS752_EFR_CTS_FLOW_CTRL_EN (1u << 7)
    125125
    126126/* IOCONTROL: User accessible. Therefore see sc16is752.h for the defines. */

  • cpukit/dev/serial/sc16is752.c

    rda8b12b rdcaea71  
    5858static bool is_sleep_mode_enabled(sc16is752_context *ctx)
    5959{
    60   return (ctx->ier & IER_SLEEP_MODE) != 0;
     60  return (ctx->ier & SC16IS752_IER_SLEEP_MODE) != 0;
    6161}
    6262
    … …  
    6464{
    6565  if (enable) {
    66     ctx->ier |= IER_SLEEP_MODE;
    67   } else {
    68     ctx->ier &= ~IER_SLEEP_MODE;
     66    ctx->ier |= SC16IS752_IER_SLEEP_MODE;
     67  } else {
     68    ctx->ier &= ~SC16IS752_IER_SLEEP_MODE;
    6969  }
    7070
    … …  
    8686  }
    8787
    88   ctx->lcr |= LCR_ENABLE_DIVISOR;
     88  ctx->lcr |= SC16IS752_LCR_ENABLE_DIVISOR;
    8989  write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);
    9090
    … …  
    9393  write_reg(ctx, SC16IS752_DLL, &dll, 1);
    9494
    95   ctx->lcr &= ~LCR_ENABLE_DIVISOR;
     95  ctx->lcr &= ~SC16IS752_LCR_ENABLE_DIVISOR;
    9696  write_reg(ctx, SC16IS752_LCR, &ctx->lcr, 1);
    9797
    … …  
    128128      return false;
    129129    } else {
    130       mcr |= MCR_PRESCALE_NEEDED;
     130      mcr |= SC16IS752_MCR_PRESCALE_NEEDED;
    131131    }
    132132  } else {
    133     mcr &= ~MCR_PRESCALE_NEEDED;
     133    mcr &= ~SC16IS752_MCR_PRESCALE_NEEDED;
    134134  }
    135135
    … …  
    156156
    157157  if ((term->c_cflag & CREAD) == 0){
    158     ctx->efcr |= EFCR_RX_DISABLE;
    159   } else {
    160     ctx->efcr &= ~EFCR_RX_DISABLE;
     158    ctx->efcr |= SC16IS752_EFCR_RX_DISABLE;
     159  } else {
     160    ctx->efcr &= ~SC16IS752_EFCR_RX_DISABLE;
    161161  }
    162162
    … …  
    165165  switch (term->c_cflag & CSIZE) {
    166166    case CS5:
    167       ctx->lcr |= LCR_CHRL_5_BIT;
     167      ctx->lcr |= SC16IS752_LCR_CHRL_5_BIT;
    168168      break;
    169169    case CS6:
    170       ctx->lcr |= LCR_CHRL_6_BIT;
     170      ctx->lcr |= SC16IS752_LCR_CHRL_6_BIT;
    171171      break;
    172172    case CS7:
    173       ctx->lcr |= LCR_CHRL_7_BIT;
     173      ctx->lcr |= SC16IS752_LCR_CHRL_7_BIT;
    174174      break;
    175175    case CS8:
    176       ctx->lcr |= LCR_CHRL_8_BIT;
     176      ctx->lcr |= SC16IS752_LCR_CHRL_8_BIT;
    177177      break;
    178178  }
    … …  
    180180  if ((term->c_cflag & PARENB) != 0){
    181181    if ((term->c_cflag & PARODD) != 0) {
    182       ctx->lcr &= ~LCR_EVEN_PARITY;
     182      ctx->lcr &= ~SC16IS752_LCR_EVEN_PARITY;
    183183    } else {
    184       ctx->lcr |= LCR_EVEN_PARITY;
     184      ctx->lcr |= SC16IS752_LCR_EVEN_PARITY;
    185185    }
    186186  } else {
    187     ctx->lcr &= ~LCR_SET_PARITY;
     187    ctx->lcr &= ~SC16IS752_LCR_SET_PARITY;
    188188  }
    189189
    190190  if ((term->c_cflag & CSTOPB) != 0) {
    191     ctx->lcr |= LCR_2_STOP_BIT;
    192   } else {
    193     ctx->lcr &= ~LCR_2_STOP_BIT;
     191    ctx->lcr |= SC16IS752_LCR_2_STOP_BIT;
     192  } else {
     193    ctx->lcr &= ~SC16IS752_LCR_2_STOP_BIT;
    194194  }
    195195
    … …  
    219219
    220220  if (ctx->mode == SC16IS752_MODE_RS485) {
    221     ctx->efcr = EFCR_RS485_ENABLE;
     221    ctx->efcr = SC16IS752_EFCR_RS485_ENABLE;
    222222  } else {
    223223    ctx->efcr = 0;
    … …  
    226226  write_reg(ctx, SC16IS752_FCR, &ctx->efcr, 1);
    227227
    228   fcr = FCR_FIFO_EN | FCR_RX_FIFO_RST | FCR_TX_FIFO_RST
    229     | FCR_RX_FIFO_TRG_16 | FCR_TX_FIFO_TRG_32;
     228  fcr = SC16IS752_FCR_FIFO_EN
     229    | SC16IS752_FCR_RX_FIFO_RST
     230    | SC16IS752_FCR_TX_FIFO_RST
     231    | SC16IS752_FCR_RX_FIFO_TRG_16
     232    | SC16IS752_FCR_TX_FIFO_TRG_32;
    230233  write_reg(ctx, SC16IS752_FCR, &fcr, 1);
    231234
    232   ctx->ier = IER_RHR;
     235  ctx->ier = SC16IS752_IER_RHR;
    233236  write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);
    234   set_efr(ctx, EFR_ENHANCED_FUNC_ENABLE);
     237  set_efr(ctx, SC16IS752_EFR_ENHANCED_FUNC_ENABLE);
    235238
    236239  rtems_termios_set_initial_baud(tty, 115200);
    … …  
    266269
    267270  if (len > 0) {
    268     ctx->ier |= IER_THR;
     271    ctx->ier |= SC16IS752_IER_THR;
    269272    len = MIN(len, 32);
    270273    ctx->tx_in_progress = (uint8_t)len;
    … …  
    273276  } else {
    274277    ctx->tx_in_progress = 0;
    275     ctx->ier &= ~IER_THR;
     278    ctx->ier &= ~SC16IS752_IER_THR;
    276279    write_reg(ctx, SC16IS752_IER, &ctx->ier, 1);
    277280  }
    … …  
    287290  read_reg(ctx, SC16IS752_MCR, &mcr, 1);
    288291
    289   if (msr & MSR_CTS) {
     292  if (msr & SC16IS752_MSR_CTS) {
    290293    *bits |= TIOCM_CTS;
    291294  }
    292   if (msr & MSR_DSR) {
     295  if (msr & SC16IS752_MSR_DSR) {
    293296    *bits |= TIOCM_DSR;
    294297  }
    295   if (msr & MSR_RI) {
     298  if (msr & SC16IS752_MSR_RI) {
    296299    *bits |= TIOCM_RI;
    297300  }
    298   if (msr & MSR_CD) {
     301  if (msr & SC16IS752_MSR_CD) {
    299302    *bits |= TIOCM_CD;
    300303  }
    301   if ((mcr & MCR_DTR) == 0) {
     304  if ((mcr & SC16IS752_MCR_DTR) == 0) {
    302305    *bits |= TIOCM_DTR;
    303306  }
    304   if ((mcr & MCR_RTS) == 0) {
     307  if ((mcr & SC16IS752_MCR_RTS) == 0) {
    305308    *bits |= TIOCM_RTS;
    306309  }
    … …  
    317320  if (bits != NULL) {
    318321    if ((*bits & TIOCM_DTR) == 0) {
    319       mcr |= MCR_DTR;
     322      mcr |= SC16IS752_MCR_DTR;
    320323    } else {
    321       mcr &= ~MCR_DTR;
     324      mcr &= ~SC16IS752_MCR_DTR;
    322325    }
    323326
    324327    if ((*bits & TIOCM_RTS) == 0) {
    325       mcr |= MCR_RTS;
     328      mcr |= SC16IS752_MCR_RTS;
    326329    } else {
    327       mcr &= ~MCR_RTS;
     330      mcr &= ~SC16IS752_MCR_RTS;
    328331    }
    329332  }
    330333
    331334  if ((set & TIOCM_DTR) != 0) {
    332     mcr &= ~MCR_DTR;
     335    mcr &= ~SC16IS752_MCR_DTR;
    333336  }
    334337  if ((set & TIOCM_RTS) != 0) {
    335     mcr &= ~MCR_RTS;
     338    mcr &= ~SC16IS752_MCR_RTS;
    336339  }
    337340  if ((clear & TIOCM_DTR) != 0) {
    338     mcr |= MCR_DTR;
     341    mcr |= SC16IS752_MCR_DTR;
    339342  }
    340343  if ((clear & TIOCM_RTS) != 0) {
    341     mcr |= MCR_RTS;
     344    mcr |= SC16IS752_MCR_RTS;
    342345  }
    343346
    … …  
    417420  iir = data[0];
    418421
    419   if ((iir & IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) {
     422  if ((iir & SC16IS752_IIR_TX_INTERRUPT) != 0 && ctx->tx_in_progress > 0) {
    420423    rtems_termios_dequeue_characters(ctx->tty, ctx->tx_in_progress);
    421424  }
    422425
    423   if ((iir & IIR_RX_INTERRUPT) != 0) {
     426  if ((iir & SC16IS752_IIR_RX_INTERRUPT) != 0) {
    424427    uint8_t buf[SC16IS752_FIFO_DEPTH];
    425428    uint8_t rxlvl = data[1];
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