Changeset dc581f2 in rtems


Ignore:
Timestamp:
Jun 21, 2019, 4:58:19 AM (5 weeks ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
54ac945
Parents:
d9fcb22
git-author:
Sebastian Huber <sebastian.huber@…> (06/21/19 04:58:19)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/21/19 04:58:48)
Message:

bsp/atsam: Enable configuration of SDRAMC_LPR

Location:
bsps/arm/atsam
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • bsps/arm/atsam/contrib/libraries/libboard/source/board_memories.c

    rd9fcb22 rdc581f2  
    289289        SDRAMC->SDRAMC_TR = BOARD_Sdram_Config.sdramc_tr;
    290290        SDRAMC->SDRAMC_CFR1 = BOARD_Sdram_Config.sdramc_cfr1;
     291        SDRAMC->SDRAMC_LPR = BOARD_Sdram_Config.sdramc_lpr;
    291292#endif /* __rtems__ */
    292293        /* After initialization, the SDRAM devices are fully functional. */
  • bsps/arm/atsam/include/bsp/atsam-clock-config.h

    rd9fcb22 rdc581f2  
    4646#define BOARD_MCK (atsam_clock_config.mck_freq)
    4747
    48 struct BOARD_Sdram_Config {
     48typedef struct BOARD_Sdram_Config {
    4949  uint32_t sdramc_tr;
    5050  uint32_t sdramc_cr;
    5151  uint32_t sdramc_mdr;
    5252  uint32_t sdramc_cfr1;
    53 };
     53  uint32_t sdramc_lpr;
     54} atsam_sdram_config;
    5455
    5556ATSAM_START_SRAM_SECTION
    56 extern const struct BOARD_Sdram_Config BOARD_Sdram_Config;
     57extern const atsam_sdram_config BOARD_Sdram_Config;
    5758
    5859#ifdef __cplusplus
  • bsps/arm/atsam/start/sdram-config.c

    rd9fcb22 rdc581f2  
    3939    | SDRAMC_CR_TXSR(15U),   /* Exit self-refresh to active time  70ns Min */
    4040  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
    41   .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2)
     41  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED | SDRAMC_CFR1_TMRD(2),
     42  .sdramc_lpr = 0
    4243};
    4344
     
    7273  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
    7374  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
    74       SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14))
     75      SDRAMC_CFR1_TMRD(CLOCK_CYCLES_FROM_NS_MIN(14)),
     76  .sdramc_lpr = 0
    7577};
    7678
     
    105107  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
    106108  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
    107       SDRAMC_CFR1_TMRD(2)
     109      SDRAMC_CFR1_TMRD(2),
     110  .sdramc_lpr = 0
    108111};
    109112
     
    125128  .sdramc_mdr = SDRAMC_MDR_MD_SDRAM,
    126129  .sdramc_cfr1 = SDRAMC_CFR1_UNAL_SUPPORTED |
    127       SDRAMC_CFR1_TMRD(2)
     130      SDRAMC_CFR1_TMRD(2),
     131  .sdramc_lpr = 0
    128132};
    129133
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