Changeset dc0f537b in rtems

Timestamp:

Jul 19, 2016, 4:43:10 AM (5 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

4.11

Children:

7b24946

Parents:

c6c4fce9

git-author:

Sebastian Huber <sebastian.huber@…> (07/19/16 04:43:10)

git-committer:

Sebastian Huber <sebastian.huber@…> (07/19/16 06:15:01)

Message:

bsps/powerpc: Fix AtliVec? context switch

Properly pass the stack aligned context to _CPU_Context_switch_altivec()
since _CPU_altivec_ctxt_off defined via ppc_context.

Update #2761.

Location:

c/src/lib/libcpu/powerpc

Files:

• mpc6xx/altivec/vec_sup.c (modified) (1 diff)
• new-exceptions/cpu_asm.S (modified) (6 diffs)

c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c

@@ -235 +235 @@
          */
         _CPU_altivec_ctxt_off  = offsetof(ppc_context, altivec);
+
+        /*
+         * See ppc_get_context() and PPC_CONTEXT_OFFSET_GPR1
+         */
+        _CPU_altivec_ctxt_off += PPC_DEFAULT_CACHE_LINE_SIZE;
+
         /* 
          * Add space possibly needed for alignment

c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S

@@ -24 +24 @@
  *  On-Line Applications Research Corporation (OAR).
  *
- *  Copyright (c) 2011-2015 embedded brains GmbH
+ *  Copyright (c) 2011, 2016 embedded brains GmbH
  *
  *  The license and distribution terms for this file may in
@@ -256 +256 @@
         /* Align to a cache line */
         clrrwi  r3, r3, PPC_DEFAULT_CACHE_LINE_POWER
-        clrrwi  r5, r4, PPC_DEFAULT_CACHE_LINE_POWER
+        clrrwi  r4, r4, PPC_DEFAULT_CACHE_LINE_POWER
 
         DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_0)
@@ -411 +411 @@
 
         /* Check the is executing indicator of the heir context */
-        addi    r6, r5, PPC_CONTEXT_OFFSET_IS_EXECUTING
+        addi    r6, r4, PPC_CONTEXT_OFFSET_IS_EXECUTING
         lwarx   r7, r0, r6
         cmpwi   r7, 0
@@ -423 +423 @@
 #endif
 
-        /* Restore context from r5 */
+        /* Restore context from r4 */
 restore_context:
 
 #if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC)
-        mr      r14, r5
+        mr      r14, r4
         .extern _CPU_Context_switch_altivec
         bl      _CPU_Context_switch_altivec
-        mr      r5, r14
-#endif
-
-        lwz     r1, PPC_CONTEXT_OFFSET_GPR1(r5)
-        lwz     r6, PPC_CONTEXT_OFFSET_MSR(r5)
-        lwz     r7, PPC_CONTEXT_OFFSET_LR(r5)
-        lwz     r8, PPC_CONTEXT_OFFSET_CR(r5)
-
-        PPC_GPR_LOAD    r14, PPC_CONTEXT_OFFSET_GPR14(r5)
-        PPC_GPR_LOAD    r15, PPC_CONTEXT_OFFSET_GPR15(r5)
+        mr      r4, r14
+#endif
+
+        lwz     r1, PPC_CONTEXT_OFFSET_GPR1(r4)
+        lwz     r6, PPC_CONTEXT_OFFSET_MSR(r4)
+        lwz     r7, PPC_CONTEXT_OFFSET_LR(r4)
+        lwz     r8, PPC_CONTEXT_OFFSET_CR(r4)
+
+        PPC_GPR_LOAD    r14, PPC_CONTEXT_OFFSET_GPR14(r4)
+        PPC_GPR_LOAD    r15, PPC_CONTEXT_OFFSET_GPR15(r4)
 
         DATA_CACHE_TOUCH(r0, r1)
 
-        PPC_GPR_LOAD    r16, PPC_CONTEXT_OFFSET_GPR16(r5)
-        PPC_GPR_LOAD    r17, PPC_CONTEXT_OFFSET_GPR17(r5)
-        PPC_GPR_LOAD    r18, PPC_CONTEXT_OFFSET_GPR18(r5)
-        PPC_GPR_LOAD    r19, PPC_CONTEXT_OFFSET_GPR19(r5)
-
-        PPC_GPR_LOAD    r20, PPC_CONTEXT_OFFSET_GPR20(r5)
-        PPC_GPR_LOAD    r21, PPC_CONTEXT_OFFSET_GPR21(r5)
-        PPC_GPR_LOAD    r22, PPC_CONTEXT_OFFSET_GPR22(r5)
-        PPC_GPR_LOAD    r23, PPC_CONTEXT_OFFSET_GPR23(r5)
-
-        PPC_GPR_LOAD    r24, PPC_CONTEXT_OFFSET_GPR24(r5)
-        PPC_GPR_LOAD    r25, PPC_CONTEXT_OFFSET_GPR25(r5)
-        PPC_GPR_LOAD    r26, PPC_CONTEXT_OFFSET_GPR26(r5)
-        PPC_GPR_LOAD    r27, PPC_CONTEXT_OFFSET_GPR27(r5)
-
-        PPC_GPR_LOAD    r28, PPC_CONTEXT_OFFSET_GPR28(r5)
-        PPC_GPR_LOAD    r29, PPC_CONTEXT_OFFSET_GPR29(r5)
-        PPC_GPR_LOAD    r30, PPC_CONTEXT_OFFSET_GPR30(r5)
-        PPC_GPR_LOAD    r31, PPC_CONTEXT_OFFSET_GPR31(r5)
-
-        lwz     r2, PPC_CONTEXT_OFFSET_GPR2(r5)
+        PPC_GPR_LOAD    r16, PPC_CONTEXT_OFFSET_GPR16(r4)
+        PPC_GPR_LOAD    r17, PPC_CONTEXT_OFFSET_GPR17(r4)
+        PPC_GPR_LOAD    r18, PPC_CONTEXT_OFFSET_GPR18(r4)
+        PPC_GPR_LOAD    r19, PPC_CONTEXT_OFFSET_GPR19(r4)
+
+        PPC_GPR_LOAD    r20, PPC_CONTEXT_OFFSET_GPR20(r4)
+        PPC_GPR_LOAD    r21, PPC_CONTEXT_OFFSET_GPR21(r4)
+        PPC_GPR_LOAD    r22, PPC_CONTEXT_OFFSET_GPR22(r4)
+        PPC_GPR_LOAD    r23, PPC_CONTEXT_OFFSET_GPR23(r4)
+
+        PPC_GPR_LOAD    r24, PPC_CONTEXT_OFFSET_GPR24(r4)
+        PPC_GPR_LOAD    r25, PPC_CONTEXT_OFFSET_GPR25(r4)
+        PPC_GPR_LOAD    r26, PPC_CONTEXT_OFFSET_GPR26(r4)
+        PPC_GPR_LOAD    r27, PPC_CONTEXT_OFFSET_GPR27(r4)
+
+        PPC_GPR_LOAD    r28, PPC_CONTEXT_OFFSET_GPR28(r4)
+        PPC_GPR_LOAD    r29, PPC_CONTEXT_OFFSET_GPR29(r4)
+        PPC_GPR_LOAD    r30, PPC_CONTEXT_OFFSET_GPR30(r4)
+        PPC_GPR_LOAD    r31, PPC_CONTEXT_OFFSET_GPR31(r4)
+
+        lwz     r2, PPC_CONTEXT_OFFSET_GPR2(r4)
 
 #ifdef PPC_MULTILIB_ALTIVEC
         li      r9, PPC_CONTEXT_OFFSET_V20
-        lvx     v20, r5, r9
+        lvx     v20, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V21
-        lvx     v21, r5, r9
+        lvx     v21, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V22
-        lvx     v22, r5, r9
+        lvx     v22, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V23
-        lvx     v23, r5, r9
+        lvx     v23, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V24
-        lvx     v24, r5, r9
+        lvx     v24, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V25
-        lvx     v25, r5, r9
+        lvx     v25, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V26
-        lvx     v26, r5, r9
+        lvx     v26, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V27
-        lvx     v27, r5, r9
+        lvx     v27, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V28
-        lvx     v28, r5, r9
+        lvx     v28, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V29
-        lvx     v29, r5, r9
+        lvx     v29, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V30
-        lvx     v30, r5, r9
+        lvx     v30, r4, r9
         li      r9, PPC_CONTEXT_OFFSET_V31
-        lvx     v31, r5, r9
-        lwz     r9, PPC_CONTEXT_OFFSET_VRSAVE(r5)
+        lvx     v31, r4, r9
+        lwz     r9, PPC_CONTEXT_OFFSET_VRSAVE(r4)
         mtvrsave        r9
 #endif
 
 #ifdef PPC_MULTILIB_FPU
-        lfd     f14, PPC_CONTEXT_OFFSET_F14(r5)
-        lfd     f15, PPC_CONTEXT_OFFSET_F15(r5)
-        lfd     f16, PPC_CONTEXT_OFFSET_F16(r5)
-        lfd     f17, PPC_CONTEXT_OFFSET_F17(r5)
-        lfd     f18, PPC_CONTEXT_OFFSET_F18(r5)
-        lfd     f19, PPC_CONTEXT_OFFSET_F19(r5)
-        lfd     f20, PPC_CONTEXT_OFFSET_F20(r5)
-        lfd     f21, PPC_CONTEXT_OFFSET_F21(r5)
-        lfd     f22, PPC_CONTEXT_OFFSET_F22(r5)
-        lfd     f23, PPC_CONTEXT_OFFSET_F23(r5)
-        lfd     f24, PPC_CONTEXT_OFFSET_F24(r5)
-        lfd     f25, PPC_CONTEXT_OFFSET_F25(r5)
-        lfd     f26, PPC_CONTEXT_OFFSET_F26(r5)
-        lfd     f27, PPC_CONTEXT_OFFSET_F27(r5)
-        lfd     f28, PPC_CONTEXT_OFFSET_F28(r5)
-        lfd     f29, PPC_CONTEXT_OFFSET_F29(r5)
-        lfd     f30, PPC_CONTEXT_OFFSET_F30(r5)
-        lfd     f31, PPC_CONTEXT_OFFSET_F31(r5)
+        lfd     f14, PPC_CONTEXT_OFFSET_F14(r4)
+        lfd     f15, PPC_CONTEXT_OFFSET_F15(r4)
+        lfd     f16, PPC_CONTEXT_OFFSET_F16(r4)
+        lfd     f17, PPC_CONTEXT_OFFSET_F17(r4)
+        lfd     f18, PPC_CONTEXT_OFFSET_F18(r4)
+        lfd     f19, PPC_CONTEXT_OFFSET_F19(r4)
+        lfd     f20, PPC_CONTEXT_OFFSET_F20(r4)
+        lfd     f21, PPC_CONTEXT_OFFSET_F21(r4)
+        lfd     f22, PPC_CONTEXT_OFFSET_F22(r4)
+        lfd     f23, PPC_CONTEXT_OFFSET_F23(r4)
+        lfd     f24, PPC_CONTEXT_OFFSET_F24(r4)
+        lfd     f25, PPC_CONTEXT_OFFSET_F25(r4)
+        lfd     f26, PPC_CONTEXT_OFFSET_F26(r4)
+        lfd     f27, PPC_CONTEXT_OFFSET_F27(r4)
+        lfd     f28, PPC_CONTEXT_OFFSET_F28(r4)
+        lfd     f29, PPC_CONTEXT_OFFSET_F29(r4)
+        lfd     f30, PPC_CONTEXT_OFFSET_F30(r4)
+        lfd     f31, PPC_CONTEXT_OFFSET_F31(r4)
 #endif
 
@@ -528 +528 @@
 PROC (_CPU_Context_restore):
         /* Align to a cache line */
-        clrrwi  r5, r3, PPC_DEFAULT_CACHE_LINE_POWER
+        clrrwi  r4, r3, PPC_DEFAULT_CACHE_LINE_POWER
 
 #if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC)
@@ -560 +560 @@
         sub     r7, r4, r7
         add     r4, r8, r7
-        clrrwi  r5, r4, PPC_DEFAULT_CACHE_LINE_POWER
+        clrrwi  r4, r4, PPC_DEFAULT_CACHE_LINE_POWER
 
         /* Update the executing */