Changeset dc0f537b in rtems
- Timestamp:
- Jul 19, 2016, 4:43:10 AM (5 years ago)
- Branches:
- 4.11
- Children:
- 7b24946
- Parents:
- c6c4fce9
- git-author:
- Sebastian Huber <sebastian.huber@…> (07/19/16 04:43:10)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (07/19/16 06:15:01)
- Location:
- c/src/lib/libcpu/powerpc
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/powerpc/mpc6xx/altivec/vec_sup.c
rc6c4fce9 rdc0f537b 235 235 */ 236 236 _CPU_altivec_ctxt_off = offsetof(ppc_context, altivec); 237 238 /* 239 * See ppc_get_context() and PPC_CONTEXT_OFFSET_GPR1 240 */ 241 _CPU_altivec_ctxt_off += PPC_DEFAULT_CACHE_LINE_SIZE; 242 237 243 /* 238 244 * Add space possibly needed for alignment -
c/src/lib/libcpu/powerpc/new-exceptions/cpu_asm.S
rc6c4fce9 rdc0f537b 24 24 * On-Line Applications Research Corporation (OAR). 25 25 * 26 * Copyright (c) 2011 -2015embedded brains GmbH26 * Copyright (c) 2011, 2016 embedded brains GmbH 27 27 * 28 28 * The license and distribution terms for this file may in … … 256 256 /* Align to a cache line */ 257 257 clrrwi r3, r3, PPC_DEFAULT_CACHE_LINE_POWER 258 clrrwi r 5, r4, PPC_DEFAULT_CACHE_LINE_POWER258 clrrwi r4, r4, PPC_DEFAULT_CACHE_LINE_POWER 259 259 260 260 DATA_CACHE_ZERO_AND_TOUCH(r10, PPC_CONTEXT_CACHE_LINE_0) … … 411 411 412 412 /* Check the is executing indicator of the heir context */ 413 addi r6, r 5, PPC_CONTEXT_OFFSET_IS_EXECUTING413 addi r6, r4, PPC_CONTEXT_OFFSET_IS_EXECUTING 414 414 lwarx r7, r0, r6 415 415 cmpwi r7, 0 … … 423 423 #endif 424 424 425 /* Restore context from r 5*/425 /* Restore context from r4 */ 426 426 restore_context: 427 427 428 428 #if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) 429 mr r14, r 5429 mr r14, r4 430 430 .extern _CPU_Context_switch_altivec 431 431 bl _CPU_Context_switch_altivec 432 mr r 5, r14433 #endif 434 435 lwz r1, PPC_CONTEXT_OFFSET_GPR1(r 5)436 lwz r6, PPC_CONTEXT_OFFSET_MSR(r 5)437 lwz r7, PPC_CONTEXT_OFFSET_LR(r 5)438 lwz r8, PPC_CONTEXT_OFFSET_CR(r 5)439 440 PPC_GPR_LOAD r14, PPC_CONTEXT_OFFSET_GPR14(r 5)441 PPC_GPR_LOAD r15, PPC_CONTEXT_OFFSET_GPR15(r 5)432 mr r4, r14 433 #endif 434 435 lwz r1, PPC_CONTEXT_OFFSET_GPR1(r4) 436 lwz r6, PPC_CONTEXT_OFFSET_MSR(r4) 437 lwz r7, PPC_CONTEXT_OFFSET_LR(r4) 438 lwz r8, PPC_CONTEXT_OFFSET_CR(r4) 439 440 PPC_GPR_LOAD r14, PPC_CONTEXT_OFFSET_GPR14(r4) 441 PPC_GPR_LOAD r15, PPC_CONTEXT_OFFSET_GPR15(r4) 442 442 443 443 DATA_CACHE_TOUCH(r0, r1) 444 444 445 PPC_GPR_LOAD r16, PPC_CONTEXT_OFFSET_GPR16(r 5)446 PPC_GPR_LOAD r17, PPC_CONTEXT_OFFSET_GPR17(r 5)447 PPC_GPR_LOAD r18, PPC_CONTEXT_OFFSET_GPR18(r 5)448 PPC_GPR_LOAD r19, PPC_CONTEXT_OFFSET_GPR19(r 5)449 450 PPC_GPR_LOAD r20, PPC_CONTEXT_OFFSET_GPR20(r 5)451 PPC_GPR_LOAD r21, PPC_CONTEXT_OFFSET_GPR21(r 5)452 PPC_GPR_LOAD r22, PPC_CONTEXT_OFFSET_GPR22(r 5)453 PPC_GPR_LOAD r23, PPC_CONTEXT_OFFSET_GPR23(r 5)454 455 PPC_GPR_LOAD r24, PPC_CONTEXT_OFFSET_GPR24(r 5)456 PPC_GPR_LOAD r25, PPC_CONTEXT_OFFSET_GPR25(r 5)457 PPC_GPR_LOAD r26, PPC_CONTEXT_OFFSET_GPR26(r 5)458 PPC_GPR_LOAD r27, PPC_CONTEXT_OFFSET_GPR27(r 5)459 460 PPC_GPR_LOAD r28, PPC_CONTEXT_OFFSET_GPR28(r 5)461 PPC_GPR_LOAD r29, PPC_CONTEXT_OFFSET_GPR29(r 5)462 PPC_GPR_LOAD r30, PPC_CONTEXT_OFFSET_GPR30(r 5)463 PPC_GPR_LOAD r31, PPC_CONTEXT_OFFSET_GPR31(r 5)464 465 lwz r2, PPC_CONTEXT_OFFSET_GPR2(r 5)445 PPC_GPR_LOAD r16, PPC_CONTEXT_OFFSET_GPR16(r4) 446 PPC_GPR_LOAD r17, PPC_CONTEXT_OFFSET_GPR17(r4) 447 PPC_GPR_LOAD r18, PPC_CONTEXT_OFFSET_GPR18(r4) 448 PPC_GPR_LOAD r19, PPC_CONTEXT_OFFSET_GPR19(r4) 449 450 PPC_GPR_LOAD r20, PPC_CONTEXT_OFFSET_GPR20(r4) 451 PPC_GPR_LOAD r21, PPC_CONTEXT_OFFSET_GPR21(r4) 452 PPC_GPR_LOAD r22, PPC_CONTEXT_OFFSET_GPR22(r4) 453 PPC_GPR_LOAD r23, PPC_CONTEXT_OFFSET_GPR23(r4) 454 455 PPC_GPR_LOAD r24, PPC_CONTEXT_OFFSET_GPR24(r4) 456 PPC_GPR_LOAD r25, PPC_CONTEXT_OFFSET_GPR25(r4) 457 PPC_GPR_LOAD r26, PPC_CONTEXT_OFFSET_GPR26(r4) 458 PPC_GPR_LOAD r27, PPC_CONTEXT_OFFSET_GPR27(r4) 459 460 PPC_GPR_LOAD r28, PPC_CONTEXT_OFFSET_GPR28(r4) 461 PPC_GPR_LOAD r29, PPC_CONTEXT_OFFSET_GPR29(r4) 462 PPC_GPR_LOAD r30, PPC_CONTEXT_OFFSET_GPR30(r4) 463 PPC_GPR_LOAD r31, PPC_CONTEXT_OFFSET_GPR31(r4) 464 465 lwz r2, PPC_CONTEXT_OFFSET_GPR2(r4) 466 466 467 467 #ifdef PPC_MULTILIB_ALTIVEC 468 468 li r9, PPC_CONTEXT_OFFSET_V20 469 lvx v20, r 5, r9469 lvx v20, r4, r9 470 470 li r9, PPC_CONTEXT_OFFSET_V21 471 lvx v21, r 5, r9471 lvx v21, r4, r9 472 472 li r9, PPC_CONTEXT_OFFSET_V22 473 lvx v22, r 5, r9473 lvx v22, r4, r9 474 474 li r9, PPC_CONTEXT_OFFSET_V23 475 lvx v23, r 5, r9475 lvx v23, r4, r9 476 476 li r9, PPC_CONTEXT_OFFSET_V24 477 lvx v24, r 5, r9477 lvx v24, r4, r9 478 478 li r9, PPC_CONTEXT_OFFSET_V25 479 lvx v25, r 5, r9479 lvx v25, r4, r9 480 480 li r9, PPC_CONTEXT_OFFSET_V26 481 lvx v26, r 5, r9481 lvx v26, r4, r9 482 482 li r9, PPC_CONTEXT_OFFSET_V27 483 lvx v27, r 5, r9483 lvx v27, r4, r9 484 484 li r9, PPC_CONTEXT_OFFSET_V28 485 lvx v28, r 5, r9485 lvx v28, r4, r9 486 486 li r9, PPC_CONTEXT_OFFSET_V29 487 lvx v29, r 5, r9487 lvx v29, r4, r9 488 488 li r9, PPC_CONTEXT_OFFSET_V30 489 lvx v30, r 5, r9489 lvx v30, r4, r9 490 490 li r9, PPC_CONTEXT_OFFSET_V31 491 lvx v31, r 5, r9492 lwz r9, PPC_CONTEXT_OFFSET_VRSAVE(r 5)491 lvx v31, r4, r9 492 lwz r9, PPC_CONTEXT_OFFSET_VRSAVE(r4) 493 493 mtvrsave r9 494 494 #endif 495 495 496 496 #ifdef PPC_MULTILIB_FPU 497 lfd f14, PPC_CONTEXT_OFFSET_F14(r 5)498 lfd f15, PPC_CONTEXT_OFFSET_F15(r 5)499 lfd f16, PPC_CONTEXT_OFFSET_F16(r 5)500 lfd f17, PPC_CONTEXT_OFFSET_F17(r 5)501 lfd f18, PPC_CONTEXT_OFFSET_F18(r 5)502 lfd f19, PPC_CONTEXT_OFFSET_F19(r 5)503 lfd f20, PPC_CONTEXT_OFFSET_F20(r 5)504 lfd f21, PPC_CONTEXT_OFFSET_F21(r 5)505 lfd f22, PPC_CONTEXT_OFFSET_F22(r 5)506 lfd f23, PPC_CONTEXT_OFFSET_F23(r 5)507 lfd f24, PPC_CONTEXT_OFFSET_F24(r 5)508 lfd f25, PPC_CONTEXT_OFFSET_F25(r 5)509 lfd f26, PPC_CONTEXT_OFFSET_F26(r 5)510 lfd f27, PPC_CONTEXT_OFFSET_F27(r 5)511 lfd f28, PPC_CONTEXT_OFFSET_F28(r 5)512 lfd f29, PPC_CONTEXT_OFFSET_F29(r 5)513 lfd f30, PPC_CONTEXT_OFFSET_F30(r 5)514 lfd f31, PPC_CONTEXT_OFFSET_F31(r 5)497 lfd f14, PPC_CONTEXT_OFFSET_F14(r4) 498 lfd f15, PPC_CONTEXT_OFFSET_F15(r4) 499 lfd f16, PPC_CONTEXT_OFFSET_F16(r4) 500 lfd f17, PPC_CONTEXT_OFFSET_F17(r4) 501 lfd f18, PPC_CONTEXT_OFFSET_F18(r4) 502 lfd f19, PPC_CONTEXT_OFFSET_F19(r4) 503 lfd f20, PPC_CONTEXT_OFFSET_F20(r4) 504 lfd f21, PPC_CONTEXT_OFFSET_F21(r4) 505 lfd f22, PPC_CONTEXT_OFFSET_F22(r4) 506 lfd f23, PPC_CONTEXT_OFFSET_F23(r4) 507 lfd f24, PPC_CONTEXT_OFFSET_F24(r4) 508 lfd f25, PPC_CONTEXT_OFFSET_F25(r4) 509 lfd f26, PPC_CONTEXT_OFFSET_F26(r4) 510 lfd f27, PPC_CONTEXT_OFFSET_F27(r4) 511 lfd f28, PPC_CONTEXT_OFFSET_F28(r4) 512 lfd f29, PPC_CONTEXT_OFFSET_F29(r4) 513 lfd f30, PPC_CONTEXT_OFFSET_F30(r4) 514 lfd f31, PPC_CONTEXT_OFFSET_F31(r4) 515 515 #endif 516 516 … … 528 528 PROC (_CPU_Context_restore): 529 529 /* Align to a cache line */ 530 clrrwi r 5, r3, PPC_DEFAULT_CACHE_LINE_POWER530 clrrwi r4, r3, PPC_DEFAULT_CACHE_LINE_POWER 531 531 532 532 #if defined(__ALTIVEC__) && !defined(PPC_MULTILIB_ALTIVEC) … … 560 560 sub r7, r4, r7 561 561 add r4, r8, r7 562 clrrwi r 5, r4, PPC_DEFAULT_CACHE_LINE_POWER562 clrrwi r4, r4, PPC_DEFAULT_CACHE_LINE_POWER 563 563 564 564 /* Update the executing */
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