Index: c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
===================================================================
--- c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h	(revision 92e2757b0bd6b6e2a3452bc64cc6119d6fe47cb7)
+++ c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h	(revision db5a84d0ad4186e8875cdad9db15c7516364921f)
@@ -1121,20 +1121,15 @@
 
 static inline void
-cache_l2c_310_invalidate_range( const void *addr, size_t n_bytes )
-{
-  if ( n_bytes != 0 ) {
-    uint32_t       adx  = (uint32_t) addr
-                         & ~CACHE_L2C_310_INSTRUCTION_LINE_MASK;
-    const uint32_t end  =
-      ( adx + n_bytes ) & ~CACHE_L2C_310_INSTRUCTION_LINE_MASK;
+cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST )
+{
     volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
 
     /* Back starting address up to start of a line and invalidate until end */
-    for (;
-         adx < end;
-         adx += CPU_INSTRUCTION_CACHE_ALIGNMENT ) {
-      /* Invalidate L2 cache line */
-      l2cc->inv_pa = adx;
-    }
+  for (;
+       adx <= ADDR_LAST;
+       adx += CPU_INSTRUCTION_CACHE_ALIGNMENT ) {
+    /* Invalidate L2 cache line */
+    l2cc->inv_pa = adx;
+  }
     cache_l2c_310_sync();
   }
@@ -1408,17 +1403,39 @@
 {
   if ( n_bytes > 0 ) {
+    /* Back starting address up to start of a line and invalidate until ADDR_LAST */
+    uint32_t       adx       = (uint32_t) addr_first
+      & ~CACHE_L2C_310_DATA_LINE_MASK;
+    const uint32_t ADDR_LAST =
+      (uint32_t)( (size_t)addr_first + n_bytes - 1 );
+    uint32_t       block_end =
+      CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
     
-    cache_l2c_310_invalidate_range(
-      addr_first,
-      n_bytes
-    );
+    /* We have to apply a lock. Thus we will operate only CACHE_MAX_LOCKING_BYTES
+     * at a time */
+    for (;
+         adx      <= ADDR_LAST;
+         adx       = block_end + 1,
+         block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
+      cache_l2c_310_invalidate_range(
+        adx,
+        block_end
+      );
+    }
     arm_cache_l1_invalidate_data_range(
       addr_first,
       n_bytes
     );
-    cache_l2c_310_invalidate_range(
-      addr_first,
-      n_bytes
-    );
+
+    adx       = (uint32_t)addr_first & ~CACHE_L2C_310_DATA_LINE_MASK;
+    block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
+    for (;
+         adx      <= ADDR_LAST;
+         adx       = block_end + 1,
+         block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
+      cache_l2c_310_invalidate_range(
+        adx,
+        block_end
+      );
+    }
     arm_cache_l1_invalidate_data_range(
       addr_first,
@@ -1472,11 +1489,22 @@
 {
   if ( n_bytes != 0 ) {
-    
+    uint32_t       adx       = (uint32_t) i_addr
+      & ~CACHE_L2C_310_DATA_LINE_MASK;
+    const uint32_t ADDR_LAST =
+    (uint32_t)( (size_t)i_addr + n_bytes - 1 );
+    uint32_t       block_end =
+      CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
+
     /* Invalidate L2 cache lines */
-    cache_l2c_310_invalidate_range(
-      i_addr,
-      n_bytes
-    );
-    
+    for (;
+         adx      <= ADDR_LAST;
+         adx       = block_end + 1,
+         block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
+      cache_l2c_310_invalidate_range(
+        adx,
+        block_end
+      );
+    }
+
     arm_cache_l1_invalidate_instruction_range(
       i_addr,
Index: c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
===================================================================
--- c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h	(revision 92e2757b0bd6b6e2a3452bc64cc6119d6fe47cb7)
+++ c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h	(revision db5a84d0ad4186e8875cdad9db15c7516364921f)
@@ -248,6 +248,6 @@
                                & ~ARM_CACHE_L1_DATA_LINE_MASK;
     const uint32_t ADDR_LAST =
-      ( (uint32_t) d_addr + n_bytes - 1 ) & ~ARM_CACHE_L1_DATA_LINE_MASK;
-      
+      (uint32_t)( (size_t) d_addr + n_bytes - 1 );
+
     ARM_CACHE_L1_ERRATA_764369_HANDLER();
 
@@ -301,5 +301,5 @@
                          & ~ARM_CACHE_L1_DATA_LINE_MASK;
     const uint32_t end =
-      ( adx + n_bytes ) & ~ARM_CACHE_L1_DATA_LINE_MASK;
+      (uint32_t)( (size_t)d_addr + n_bytes -1);
 
     ARM_CACHE_L1_ERRATA_764369_HANDLER();
@@ -307,5 +307,5 @@
     /* Back starting address up to start of a line and invalidate until end */
     for (;
-         adx < end;
+         adx <= end;
          adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
         /* Invalidate the Instruction cache line */
@@ -326,5 +326,5 @@
                          & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
     const uint32_t end =
-      ( adx + n_bytes ) & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
+      (uint32_t)( (size_t)i_addr + n_bytes -1);
 
     arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
@@ -334,5 +334,5 @@
     /* Back starting address up to start of a line and invalidate until end */
     for (;
-         adx < end;
+         adx <= end;
          adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) {
         /* Invalidate the Instruction cache line */
