Changeset db5a84d in rtems


Ignore:
Timestamp:
Apr 17, 2014, 8:59:47 AM (6 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
bebcfa57
Parents:
92e2757
git-author:
Ralf Kirchner <ralf.kirchner@…> (04/17/14 08:59:47)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/17/14 11:25:11)
Message:

bsp/arm: Correct cache misalignment handling

Correct misalignment handling and prepare for locking.

Location:
c/src/lib/libbsp/arm/shared
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r92e2757 rdb5a84d  
    11211121
    11221122static inline void
    1123 cache_l2c_310_invalidate_range( const void *addr, size_t n_bytes )
    1124 {
    1125   if ( n_bytes != 0 ) {
    1126     uint32_t       adx  = (uint32_t) addr
    1127                          & ~CACHE_L2C_310_INSTRUCTION_LINE_MASK;
    1128     const uint32_t end  =
    1129       ( adx + n_bytes ) & ~CACHE_L2C_310_INSTRUCTION_LINE_MASK;
     1123cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST )
     1124{
    11301125    volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2CC_BASE;
    11311126
    11321127    /* Back starting address up to start of a line and invalidate until end */
    1133     for (;
    1134          adx < end;
    1135          adx += CPU_INSTRUCTION_CACHE_ALIGNMENT ) {
    1136       /* Invalidate L2 cache line */
    1137       l2cc->inv_pa = adx;
    1138     }
     1128  for (;
     1129       adx <= ADDR_LAST;
     1130       adx += CPU_INSTRUCTION_CACHE_ALIGNMENT ) {
     1131    /* Invalidate L2 cache line */
     1132    l2cc->inv_pa = adx;
     1133  }
    11391134    cache_l2c_310_sync();
    11401135  }
     
    14081403{
    14091404  if ( n_bytes > 0 ) {
     1405    /* Back starting address up to start of a line and invalidate until ADDR_LAST */
     1406    uint32_t       adx       = (uint32_t) addr_first
     1407      & ~CACHE_L2C_310_DATA_LINE_MASK;
     1408    const uint32_t ADDR_LAST =
     1409      (uint32_t)( (size_t)addr_first + n_bytes - 1 );
     1410    uint32_t       block_end =
     1411      CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
    14101412   
    1411     cache_l2c_310_invalidate_range(
    1412       addr_first,
    1413       n_bytes
    1414     );
     1413    /* We have to apply a lock. Thus we will operate only CACHE_MAX_LOCKING_BYTES
     1414     * at a time */
     1415    for (;
     1416         adx      <= ADDR_LAST;
     1417         adx       = block_end + 1,
     1418         block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
     1419      cache_l2c_310_invalidate_range(
     1420        adx,
     1421        block_end
     1422      );
     1423    }
    14151424    arm_cache_l1_invalidate_data_range(
    14161425      addr_first,
    14171426      n_bytes
    14181427    );
    1419     cache_l2c_310_invalidate_range(
    1420       addr_first,
    1421       n_bytes
    1422     );
     1428
     1429    adx       = (uint32_t)addr_first & ~CACHE_L2C_310_DATA_LINE_MASK;
     1430    block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
     1431    for (;
     1432         adx      <= ADDR_LAST;
     1433         adx       = block_end + 1,
     1434         block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
     1435      cache_l2c_310_invalidate_range(
     1436        adx,
     1437        block_end
     1438      );
     1439    }
    14231440    arm_cache_l1_invalidate_data_range(
    14241441      addr_first,
     
    14721489{
    14731490  if ( n_bytes != 0 ) {
    1474    
     1491    uint32_t       adx       = (uint32_t) i_addr
     1492      & ~CACHE_L2C_310_DATA_LINE_MASK;
     1493    const uint32_t ADDR_LAST =
     1494    (uint32_t)( (size_t)i_addr + n_bytes - 1 );
     1495    uint32_t       block_end =
     1496      CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
     1497
    14751498    /* Invalidate L2 cache lines */
    1476     cache_l2c_310_invalidate_range(
    1477       i_addr,
    1478       n_bytes
    1479     );
    1480    
     1499    for (;
     1500         adx      <= ADDR_LAST;
     1501         adx       = block_end + 1,
     1502         block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
     1503      cache_l2c_310_invalidate_range(
     1504        adx,
     1505        block_end
     1506      );
     1507    }
     1508
    14811509    arm_cache_l1_invalidate_instruction_range(
    14821510      i_addr,
  • c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h

    r92e2757 rdb5a84d  
    248248                               & ~ARM_CACHE_L1_DATA_LINE_MASK;
    249249    const uint32_t ADDR_LAST =
    250       ( (uint32_t) d_addr + n_bytes - 1 ) & ~ARM_CACHE_L1_DATA_LINE_MASK;
    251      
     250      (uint32_t)( (size_t) d_addr + n_bytes - 1 );
     251
    252252    ARM_CACHE_L1_ERRATA_764369_HANDLER();
    253253
     
    301301                         & ~ARM_CACHE_L1_DATA_LINE_MASK;
    302302    const uint32_t end =
    303       ( adx + n_bytes ) & ~ARM_CACHE_L1_DATA_LINE_MASK;
     303      (uint32_t)( (size_t)d_addr + n_bytes -1);
    304304
    305305    ARM_CACHE_L1_ERRATA_764369_HANDLER();
     
    307307    /* Back starting address up to start of a line and invalidate until end */
    308308    for (;
    309          adx < end;
     309         adx <= end;
    310310         adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) {
    311311        /* Invalidate the Instruction cache line */
     
    326326                         & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
    327327    const uint32_t end =
    328       ( adx + n_bytes ) & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK;
     328      (uint32_t)( (size_t)i_addr + n_bytes -1);
    329329
    330330    arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION );
     
    334334    /* Back starting address up to start of a line and invalidate until end */
    335335    for (;
    336          adx < end;
     336         adx <= end;
    337337         adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) {
    338338        /* Invalidate the Instruction cache line */
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