Changeset db42c079 in rtems


Ignore:
Timestamp:
May 31, 2013, 11:59:47 AM (7 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
94c17af
Parents:
f2f211c5
git-author:
Sebastian Huber <sebastian.huber@…> (05/31/13 11:59:47)
git-committer:
Sebastian Huber <sebastian.huber@…> (05/31/13 13:20:33)
Message:

bsps/arm: Add SMP support

Location:
c/src/lib
Files:
6 added
20 edited
2 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/realview-pbx-a9/Makefile.am

    rf2f211c5 rdb42c079  
    3636include_bsp_HEADERS += ../shared/include/arm-a9mpcore-irq.h
    3737include_bsp_HEADERS += ../shared/include/arm-a9mpcore-regs.h
     38include_bsp_HEADERS += ../shared/include/arm-a9mpcore-start.h
    3839include_bsp_HEADERS += ../shared/include/arm-cp15-start.h
    3940include_bsp_HEADERS += ../shared/include/arm-gic.h
     
    6061
    6162EXTRA_DIST =
     63EXTRA_DIST += startup/linkcmds.realview_pbx_a9_qemu
     64EXTRA_DIST += startup/linkcmds.realview_pbx_a9_qemu_smp
    6265
    6366###############################################################################
     
    122125libbsp_a_SOURCES += startup/bspstarthooks.c
    123126
     127if HAS_SMP
     128libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
     129endif
     130
    124131###############################################################################
    125132#                  Special Rules                                              #
  • c/src/lib/libbsp/arm/realview-pbx-a9/README

    rf2f211c5 rdb42c079  
    1212
    1313qemu-system-arm -S -s -no-reboot -net none -nographic -M realview-pbx-a9 -m 256M -kernel ticker.exe
     14
     15qemu-system-arm -S -s -no-reboot -net none -nographic -smp 2 -icount auto -M realview-pbx-a9 -m 256M -kernel ticker.exe
  • c/src/lib/libbsp/arm/realview-pbx-a9/configure.ac

    rf2f211c5 rdb42c079  
    3434simulation times.])
    3535
     36RTEMS_CHECK_SMP
     37AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
     38
    3639RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
    3740RTEMS_BSP_LINKCMDS
  • c/src/lib/libbsp/arm/realview-pbx-a9/include/bsp.h

    rf2f211c5 rdb42c079  
    3232#endif /* __cplusplus */
    3333
     34#define BSP_ARM_A9MPCORE_SCU_BASE 0x1f000000
     35
     36#define BSP_ARM_GIC_CPUIF_BASE 0x1f000100
     37
    3438#define BSP_ARM_A9MPCORE_PT_BASE 0x1f000600
     39
     40#define BSP_ARM_GIC_DIST_BASE 0x1f001000
    3541
    3642typedef enum {
  • c/src/lib/libbsp/arm/realview-pbx-a9/include/irq.h

    rf2f211c5 rdb42c079  
    7878#define BSP_INTERRUPT_VECTOR_MAX 89
    7979
    80 #define BSP_ARM_GIC_CPUIF_BASE 0x1f000100
    81 
    82 #define BSP_ARM_GIC_DIST_BASE 0x1f001000
    83 
    8480#ifdef __cplusplus
    8581}
  • c/src/lib/libbsp/arm/realview-pbx-a9/preinstall.am

    rf2f211c5 rdb42c079  
    9595PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-regs.h
    9696
     97$(PROJECT_INCLUDE)/bsp/arm-a9mpcore-start.h: ../shared/include/arm-a9mpcore-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     98        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-start.h
     99PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-start.h
     100
    97101$(PROJECT_INCLUDE)/bsp/arm-cp15-start.h: ../shared/include/arm-cp15-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    98102        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-cp15-start.h
  • c/src/lib/libbsp/arm/realview-pbx-a9/startup/bspstarthooks.c

    rf2f211c5 rdb42c079  
    1616#include <bsp/start.h>
    1717#include <bsp/arm-cp15-start.h>
     18#include <bsp/arm-a9mpcore-start.h>
    1819#include <bsp/linker-symbols.h>
    1920
    20 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
    21 {
    22   /* Do nothing */
    23 }
     21#ifdef RTEMS_SMP
     22  #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_SHAREABLE
     23#else
     24  #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_CACHED
     25#endif
    2426
    2527BSP_START_DATA_SECTION static const arm_cp15_start_section_config
     
    3234    .begin = (uint32_t) bsp_section_fast_data_begin,
    3335    .end = (uint32_t) bsp_section_fast_data_end,
    34     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     36    .flags = MMU_DATA_READ_WRITE
    3537  }, {
    3638    .begin = (uint32_t) bsp_section_start_begin,
     
    4042    .begin = (uint32_t) bsp_section_vector_begin,
    4143    .end = (uint32_t) bsp_section_vector_end,
    42     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     44    .flags = MMU_DATA_READ_WRITE
    4345  }, {
    4446    .begin = (uint32_t) bsp_section_text_begin,
     
    5254    .begin = (uint32_t) bsp_section_data_begin,
    5355    .end = (uint32_t) bsp_section_data_end,
    54     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     56    .flags = MMU_DATA_READ_WRITE
    5557  }, {
    5658    .begin = (uint32_t) bsp_section_bss_begin,
    5759    .end = (uint32_t) bsp_section_bss_end,
    58     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     60    .flags = MMU_DATA_READ_WRITE
    5961  }, {
    6062    .begin = (uint32_t) bsp_section_work_begin,
    6163    .end = (uint32_t) bsp_section_work_end,
    62     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     64    .flags = MMU_DATA_READ_WRITE
    6365  }, {
    6466    .begin = (uint32_t) bsp_section_stack_begin,
    6567    .end = (uint32_t) bsp_section_stack_end,
    66     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     68    .flags = MMU_DATA_READ_WRITE
    6769  }, {
    6870    .begin = 0x10000000U,
     
    9294}
    9395
     96BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
     97{
     98  arm_a9mpcore_start_hook_0();
     99}
     100
    94101BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
    95102{
  • c/src/lib/libbsp/arm/shared/arm-gic-irq.c

    rf2f211c5 rdb42c079  
    1919#include <libcpu/arm-cp15.h>
    2020
    21 #include <bsp.h>
    2221#include <bsp/irq.h>
    2322#include <bsp/irq-generic.h>
     23#include <bsp/start.h>
    2424
    2525#define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE)
    26 
    27 #define GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
    2826
    2927#define PRIORITY_DEFAULT 128
     
    5250
    5351  if (bsp_interrupt_is_valid_vector(vector)) {
    54     volatile gic_dist *dist = GIC_DIST;
     52    volatile gic_dist *dist = ARM_GIC_DIST;
    5553
    5654    gic_id_enable(dist, vector);
     
    6765
    6866  if (bsp_interrupt_is_valid_vector(vector)) {
    69     volatile gic_dist *dist = GIC_DIST;
     67    volatile gic_dist *dist = ARM_GIC_DIST;
    7068
    7169    gic_id_disable(dist, vector);
     
    9088{
    9189  volatile gic_cpuif *cpuif = GIC_CPUIF;
    92   volatile gic_dist *dist = GIC_DIST;
     90  volatile gic_dist *dist = ARM_GIC_DIST;
    9391  uint32_t id_count = get_id_count(dist);
    9492  uint32_t id;
     93
     94  arm_cp15_set_exception_handler(
     95    ARM_EXCEPTION_IRQ,
     96    _ARMV4_Exception_interrupt
     97  );
    9598
    9699  for (id = 0; id < id_count; ++id) {
     
    108111  dist->icddcr = GIC_DIST_ICDDCR_ENABLE;
    109112
    110   arm_cp15_set_exception_handler(
    111     ARM_EXCEPTION_IRQ,
    112     _ARMV4_Exception_interrupt
    113   );
    114 
    115113  return RTEMS_SUCCESSFUL;
    116114}
     115
     116#ifdef RTEMS_SMP
     117BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
     118{
     119  volatile gic_cpuif *cpuif = GIC_CPUIF;
     120  volatile gic_dist *dist = ARM_GIC_DIST;
     121
     122  while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) {
     123    /* Wait */
     124  }
     125
     126  cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff);
     127  cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0);
     128  cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE;
     129}
     130#endif
    117131
    118132rtems_status_code arm_gic_irq_set_priority(
     
    124138
    125139  if (bsp_interrupt_is_valid_vector(vector)) {
    126     volatile gic_dist *dist = GIC_DIST;
     140    volatile gic_dist *dist = ARM_GIC_DIST;
    127141
    128142    gic_id_set_priority(dist, vector, priority);
     
    142156
    143157  if (bsp_interrupt_is_valid_vector(vector)) {
    144     volatile gic_dist *dist = GIC_DIST;
     158    volatile gic_dist *dist = ARM_GIC_DIST;
    145159
    146160    *priority = gic_id_get_priority(dist, vector);
     
    151165  return sc;
    152166}
    153 
    154 rtems_status_code arm_gic_irq_generate_software_irq(
    155   rtems_vector_number vector,
    156   arm_gic_irq_software_irq_target_filter filter,
    157   uint8_t targets
    158 )
    159 {
    160   rtems_status_code sc = RTEMS_SUCCESSFUL;
    161 
    162   if (vector < 16) {
    163     volatile gic_dist *dist = GIC_DIST;
    164 
    165     dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
    166       | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
    167       | GIC_DIST_ICDSGIR_SGIINTID(vector);
    168   } else {
    169     sc = RTEMS_INVALID_ID;
    170   }
    171 
    172   return sc;
    173 }
  • c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h

    rf2f211c5 rdb42c079  
    2020typedef struct {
    2121  uint32_t ctrl;
     22#define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0)
     23#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1)
     24#define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2)
     25#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3)
     26#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4)
     27#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5)
     28#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6)
    2229  uint32_t cfg;
     30#define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1)
     31#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1)
     32#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
     33#define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7)
     34#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7)
     35#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
     36#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15)
     37#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15)
     38#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
    2339  uint32_t pwrst;
    2440  uint32_t invss;
  • c/src/lib/libbsp/arm/shared/include/arm-cp15-start.h

    rf2f211c5 rdb42c079  
    4141BSP_START_TEXT_SECTION static inline void
    4242arm_cp15_tlb_invalidate(void);
     43
     44BSP_START_TEXT_SECTION static inline uint32_t
     45arm_cp15_get_multiprocessor_affinity(void);
     46
     47BSP_START_TEXT_SECTION static inline uint32_t
     48arm_cortex_a9_get_multiprocessor_cpu_id(void);
    4349
    4450typedef struct {
  • c/src/lib/libbsp/arm/shared/include/arm-gic-irq.h

    rf2f211c5 rdb42c079  
    1616#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
    1717
    18 #include <rtems.h>
     18#include <bsp.h>
     19#include <bsp/arm-gic.h>
    1920
    2021#ifdef __cplusplus
     
    3839#define ARM_GIC_IRQ_SGI_15 15
    3940
     41#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
     42
    4043rtems_status_code arm_gic_irq_set_priority(
    4144  rtems_vector_number vector,
     
    5457} arm_gic_irq_software_irq_target_filter;
    5558
    56 rtems_status_code arm_gic_irq_generate_software_irq(
     59static inline rtems_status_code arm_gic_irq_generate_software_irq(
    5760  rtems_vector_number vector,
    5861  arm_gic_irq_software_irq_target_filter filter,
    5962  uint8_t targets
    60 );
     63)
     64{
     65  rtems_status_code sc = RTEMS_SUCCESSFUL;
     66
     67  if (vector <= ARM_GIC_IRQ_SGI_15) {
     68    volatile gic_dist *dist = ARM_GIC_DIST;
     69
     70    dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
     71      | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
     72      | GIC_DIST_ICDSGIR_SGIINTID(vector);
     73  } else {
     74    sc = RTEMS_INVALID_ID;
     75  }
     76
     77  return sc;
     78}
     79
     80static inline uint32_t arm_gic_irq_processor_count(void)
     81{
     82  volatile gic_dist *dist = ARM_GIC_DIST;
     83
     84  return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
     85}
     86
     87void arm_gic_irq_initialize_secondary_cpu(void);
    6188
    6289#ifdef __cplusplus
  • c/src/lib/libbsp/arm/shared/start/start.S

    rf2f211c5 rdb42c079  
    3232        .extern bsp_start_hook_0
    3333        .extern bsp_start_hook_1
     34        .extern bsp_stack_irq_end
     35        .extern bsp_stack_fiq_end
     36        .extern bsp_stack_abt_end
     37        .extern bsp_stack_und_end
     38        .extern bsp_stack_svc_end
     39#ifdef RTEMS_SMP
     40        .extern bsp_stack_all_size
     41#endif
    3442        .extern _ARMV4_Exception_undef_default
    3543        .extern _ARMV4_Exception_swi_default
     
    120128         */
    121129
     130#ifdef RTEMS_SMP
     131        /* Read MPIDR */
     132        mrc     p15, 0, r0, c0, c0, 5
     133
     134        /* Calculate stack offset */
     135        and     r0, #0xff
     136        ldr     r1, =bsp_stack_all_size
     137        mul     r1, r0
     138#endif
     139
    122140        /*
    123141         * Set SVC mode, disable interrupts and enable ARM instructions.
     
    132150        msr     cpsr, r0
    133151        ldr     sp, =bsp_stack_irq_end
     152#ifdef RTEMS_SMP
     153        add     sp, r1
     154#endif
    134155
    135156        /* Enter FIQ mode and set up the FIQ stack pointer */
     
    137158        msr     cpsr, r0
    138159        ldr     sp, =bsp_stack_fiq_end
     160#ifdef RTEMS_SMP
     161        add     sp, r1
     162#endif
    139163
    140164        /* Enter ABT mode and set up the ABT stack pointer */
     
    142166        msr     cpsr, r0
    143167        ldr     sp, =bsp_stack_abt_end
     168#ifdef RTEMS_SMP
     169        add     sp, r1
     170#endif
    144171
    145172        /* Enter UND mode and set up the UND stack pointer */
     
    147174        msr     cpsr, r0
    148175        ldr     sp, =bsp_stack_und_end
     176#ifdef RTEMS_SMP
     177        add     sp, r1
     178#endif
    149179
    150180        /* Enter SVC mode and set up the SVC stack pointer */
     
    152182        msr     cpsr, r0
    153183        ldr     sp, =bsp_stack_svc_end
     184#ifdef RTEMS_SMP
     185        add     sp, r1
     186#endif
    154187
    155188        /* Stay in SVC mode */
  • c/src/lib/libbsp/arm/shared/startup/linkcmds.base

    rf2f211c5 rdb42c079  
    5656bsp_stack_main_size = DEFINED (bsp_stack_main_size) ? bsp_stack_main_size : 0;
    5757bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
     58
     59bsp_stack_all_size = bsp_stack_abt_size + bsp_stack_fiq_size + bsp_stack_irq_size + bsp_stack_svc_size + bsp_stack_und_size + bsp_stack_main_size;
     60
     61bsp_processor_count = DEFINED (bsp_processor_count) ? bsp_processor_count : 1;
    5862
    5963MEMORY {
     
    324328                . = . + bsp_stack_main_size;
    325329                bsp_stack_main_end = .;
     330
     331                bsp_stack_secondary_processors_begin = .;
     332                . = . + (bsp_processor_count - 1) * bsp_stack_all_size;
     333                bsp_stack_secondary_processors_end = .;
    326334
    327335                *(.bsp_vector)
  • c/src/lib/libbsp/arm/xilinx-zynq/Makefile.am

    rf2f211c5 rdb42c079  
    3636include_bsp_HEADERS += ../shared/include/arm-a9mpcore-irq.h
    3737include_bsp_HEADERS += ../shared/include/arm-a9mpcore-regs.h
     38include_bsp_HEADERS += ../shared/include/arm-a9mpcore-start.h
    3839include_bsp_HEADERS += ../shared/include/arm-cp15-start.h
    3940include_bsp_HEADERS += ../shared/include/arm-gic.h
     
    6061
    6162EXTRA_DIST =
     63EXTRA_DIST += startup/linkcmds.xilinx_zynq_a9_qemu
     64EXTRA_DIST += startup/linkcmds.xilinx_zynq_a9_qemu_smp
    6265
    6366###############################################################################
     
    122125libbsp_a_SOURCES += startup/bspstarthooks.c
    123126
     127if HAS_SMP
     128libbsp_a_SOURCES += ../shared/arm-a9mpcore-smp.c
     129endif
     130
    124131###############################################################################
    125132#                  Special Rules                                              #
  • c/src/lib/libbsp/arm/xilinx-zynq/configure.ac

    rf2f211c5 rdb42c079  
    3434simulation times.])
    3535
     36RTEMS_CHECK_SMP
     37AM_CONDITIONAL(HAS_SMP,[test "$rtems_cv_HAS_SMP" = "yes"])
     38
    3639RTEMS_BSP_CLEANUP_OPTIONS(0, 1)
    3740RTEMS_BSP_LINKCMDS
  • c/src/lib/libbsp/arm/xilinx-zynq/include/bsp.h

    rf2f211c5 rdb42c079  
    3232#endif /* __cplusplus */
    3333
     34#define BSP_ARM_A9MPCORE_SCU_BASE 0xf8f00000
     35
     36#define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100
     37
    3438#define BSP_ARM_A9MPCORE_PT_BASE 0xf8f00600
     39
     40#define BSP_ARM_GIC_DIST_BASE 0xf8f01000
    3541
    3642typedef enum {
  • c/src/lib/libbsp/arm/xilinx-zynq/include/irq.h

    rf2f211c5 rdb42c079  
    9292#define BSP_INTERRUPT_VECTOR_MAX 92
    9393
    94 #define BSP_ARM_GIC_CPUIF_BASE 0xf8f00100
    95 
    96 #define BSP_ARM_GIC_DIST_BASE 0xf8f01000
    97 
    9894#ifdef __cplusplus
    9995}
  • c/src/lib/libbsp/arm/xilinx-zynq/preinstall.am

    rf2f211c5 rdb42c079  
    9595PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-regs.h
    9696
     97$(PROJECT_INCLUDE)/bsp/arm-a9mpcore-start.h: ../shared/include/arm-a9mpcore-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     98        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-start.h
     99PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/arm-a9mpcore-start.h
     100
    97101$(PROJECT_INCLUDE)/bsp/arm-cp15-start.h: ../shared/include/arm-cp15-start.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    98102        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/arm-cp15-start.h
  • c/src/lib/libbsp/arm/xilinx-zynq/startup/bspstarthooks.c

    rf2f211c5 rdb42c079  
    1616#include <bsp/start.h>
    1717#include <bsp/arm-cp15-start.h>
     18#include <bsp/arm-a9mpcore-start.h>
    1819#include <bsp/linker-symbols.h>
    1920
    20 BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
    21 {
    22   /* Do nothing */
    23 }
     21#ifdef RTEMS_SMP
     22  #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_SHAREABLE
     23#else
     24  #define MMU_DATA_READ_WRITE ARMV7_MMU_DATA_READ_WRITE_CACHED
     25#endif
    2426
    2527BSP_START_DATA_SECTION static const arm_cp15_start_section_config
     
    3234    .begin = (uint32_t) bsp_section_fast_data_begin,
    3335    .end = (uint32_t) bsp_section_fast_data_end,
    34     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     36    .flags = MMU_DATA_READ_WRITE
    3537  }, {
    3638    .begin = (uint32_t) bsp_section_start_begin,
     
    4042    .begin = (uint32_t) bsp_section_vector_begin,
    4143    .end = (uint32_t) bsp_section_vector_end,
    42     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     44    .flags = MMU_DATA_READ_WRITE
    4345  }, {
    4446    .begin = (uint32_t) bsp_section_text_begin,
     
    5254    .begin = (uint32_t) bsp_section_data_begin,
    5355    .end = (uint32_t) bsp_section_data_end,
    54     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     56    .flags = MMU_DATA_READ_WRITE
    5557  }, {
    5658    .begin = (uint32_t) bsp_section_bss_begin,
    5759    .end = (uint32_t) bsp_section_bss_end,
    58     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     60    .flags = MMU_DATA_READ_WRITE
    5961  }, {
    6062    .begin = (uint32_t) bsp_section_work_begin,
    6163    .end = (uint32_t) bsp_section_work_end,
    62     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     64    .flags = MMU_DATA_READ_WRITE
    6365  }, {
    6466    .begin = (uint32_t) bsp_section_stack_begin,
    6567    .end = (uint32_t) bsp_section_stack_end,
    66     .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED
     68    .flags = MMU_DATA_READ_WRITE
    6769  }, {
    6870    .begin = 0xe0000000U,
     
    9294}
    9395
     96BSP_START_TEXT_SECTION void bsp_start_hook_0(void)
     97{
     98  arm_a9mpcore_start_hook_0();
     99}
     100
    94101BSP_START_TEXT_SECTION void bsp_start_hook_1(void)
    95102{
  • c/src/lib/libcpu/arm/shared/include/arm-cp15.h

    rf2f211c5 rdb42c079  
    843843}
    844844
     845static inline uint32_t arm_cp15_get_multiprocessor_affinity(void)
     846{
     847  ARM_SWITCH_REGISTERS;
     848  uint32_t mpidr;
     849
     850  __asm__ volatile (
     851    ARM_SWITCH_TO_ARM
     852          "mrc p15, 0, %[mpidr], c0, c0, 5\n"
     853    ARM_SWITCH_BACK
     854    : [mpidr] "=&r" (mpidr) ARM_SWITCH_ADDITIONAL_OUTPUT
     855  );
     856
     857  return mpidr & 0xff;
     858}
     859
     860static inline uint32_t arm_cortex_a9_get_multiprocessor_cpu_id(void)
     861{
     862  return arm_cp15_get_multiprocessor_affinity() & 0xff;
     863}
     864
     865#define ARM_CORTEX_A9_ACTL_FW (1U << 0)
     866#define ARM_CORTEX_A9_ACTL_L2_PREFETCH_HINT_ENABLE (1U << 1)
     867#define ARM_CORTEX_A9_ACTL_L1_PREFETCH_ENABLE (1U << 2)
     868#define ARM_CORTEX_A9_ACTL_WRITE_FULL_LINE_OF_ZEROS_MODE (1U << 3)
     869#define ARM_CORTEX_A9_ACTL_SMP (1U << 6)
     870#define ARM_CORTEX_A9_ACTL_EXCL (1U << 7)
     871#define ARM_CORTEX_A9_ACTL_ALLOC_IN_ONE_WAY (1U << 8)
     872#define ARM_CORTEX_A9_ACTL_PARITY_ON (1U << 9)
     873
     874static inline uint32_t arm_cp15_get_auxiliary_control(void)
     875{
     876  ARM_SWITCH_REGISTERS;
     877  uint32_t val;
     878
     879  __asm__ volatile (
     880    ARM_SWITCH_TO_ARM
     881    "mrc p15, 0, %[val], c1, c0, 1\n"
     882    ARM_SWITCH_BACK
     883    : [val] "=&r" (val) ARM_SWITCH_ADDITIONAL_OUTPUT
     884  );
     885
     886  return val;
     887}
     888
     889static inline void arm_cp15_set_auxiliary_control(uint32_t val)
     890{
     891  ARM_SWITCH_REGISTERS;
     892
     893  __asm__ volatile (
     894    ARM_SWITCH_TO_ARM
     895    "mcr p15, 0, %[val], c1, c0, 1\n"
     896    ARM_SWITCH_BACK
     897    : ARM_SWITCH_OUTPUT
     898    : [val] "r" (val)
     899  );
     900}
     901
    845902/**
    846903 * @brief Sets the @a section_flags for the address range [@a begin, @a end).
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