Changeset db01d0c in rtems
- Timestamp:
- 07/16/15 18:15:10 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- e5a79e54
- Parents:
- 7e14385
- git-author:
- Joel Sherrill <joel.sherrill@…> (07/16/15 18:15:10)
- git-committer:
- Joel Sherrill <joel.sherrill@…> (07/16/15 18:15:53)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/sparc64/rtems/score/cpu.h
r7e14385 rdb01d0c 550 550 551 551 /* 552 * This stack is allocated by the Interrupt Manager and the switch553 * is performed in _ISR_Handler. These variables contain pointers554 * to the lowest and highest addresses in the chunk of memory allocated555 * for the interrupt stack. Since it is unknown whether the stack556 * grows up or down (in general), this give the CPU dependent557 * code the option of picking the version it wants to use. Thus558 * both must be present if either is.559 *560 * The SPARC supports a software based interrupt stack and these561 * are required.562 */563 /*564 SCORE_EXTERN void *_CPU_Interrupt_stack_low;565 SCORE_EXTERN void *_CPU_Interrupt_stack_high;566 */567 /*568 552 * This flag is context switched with each thread. It indicates 569 553 * that THIS thread has an _ISR_Dispatch stack frame on its stack.
Note: See TracChangeset
for help on using the changeset viewer.