Changeset dad36c52 in rtems


Ignore:
Timestamp:
Aug 22, 2011, 6:26:08 PM (8 years ago)
Author:
Jennifer Averett <Jennifer.Averett@…>
Branches:
4.11, master
Children:
61860b57
Parents:
3f1545b
Message:

2011-08-22 Jennifer Averett <Jennifer.Averett@…>

PR 1876

  • score/Makefile.am, score/include/rtems/score/isr.h, score/src/isr.c, score/src/smp.c, score/src/smplock.c, score/src/threaddispatch.c, score/src/threaddispatchdisablelevel.c: Add smp isr support.
  • score/src/isrsmp.c: New file.
Location:
cpukit
Files:
1 added
8 edited

Legend:

Unmodified
Added
Removed
  • cpukit/ChangeLog

    r3f1545b rdad36c52  
     12011-08-22      Jennifer Averett <Jennifer.Averett@OARcorp.com>
     2
     3        PR 1876
     4        * score/Makefile.am, score/include/rtems/score/isr.h, score/src/isr.c,
     5        score/src/smp.c, score/src/smplock.c, score/src/threaddispatch.c,
     6        score/src/threaddispatchdisablelevel.c: Add smp isr support.
     7        * score/src/isrsmp.c: New file.
     8
    192011-08-21      Petr Benes <benesp16@fel.cvut.cz>
    210
  • cpukit/score/Makefile.am

    r3f1545b rdad36c52  
    134134
    135135if HAS_SMP
    136 libscore_a_SOURCES += src/smp.c src/smplock.c \
     136libscore_a_SOURCES += src/isrsmp.c src/smp.c src/smplock.c \
    137137    src/schedulersimplesmpblock.c src/schedulersimplesmpschedule.c \
    138138    src/schedulersimplesmpunblock.c src/schedulersimplesmptick.c
  • cpukit/score/include/rtems/score/isr.h

    r3f1545b rdad36c52  
    9191
    9292/**
    93  *  @brief Disable Interrupts
     93 *  @brief Disable Interrupts on This Core
    9494 *
    9595 *  This routine disables all interrupts so that a critical section
     
    9999 *          mask level.
    100100 */
    101 #define _ISR_Disable( _level ) \
     101#define _ISR_Disable_on_this_core( _level ) \
    102102  do { \
    103103    _CPU_ISR_Disable( _level ); \
     
    106106
    107107/**
    108  *  @brief Enable Interrupts
     108 *  @brief Enable Interrupts on This Core
    109109 *
    110110 *  This routine enables interrupts to the previous interrupt mask
     
    113113 *
    114114 *  @param[in] level contains the interrupt level mask level
    115  *             previously returned by @ref _ISR_Disable_on_core.
    116  */
    117 #define _ISR_Enable( _level ) \
     115 *             previously returned by @ref _ISR_Disable_on_this_core.
     116 */
     117#define _ISR_Enable_on_this_core( _level ) \
    118118  do { \
    119119    RTEMS_COMPILER_MEMORY_BARRIER(); \
     
    122122
    123123/**
    124  *  @brief Temporarily Enable Interrupts
     124 *  @brief Temporarily Enable Interrupts on This Core
    125125 *
    126126 *  This routine temporarily enables interrupts to the previous
     
    138138 *
    139139 *  @param[in] level contains the interrupt level mask level
    140  *             previously returned by @ref _ISR_Disable_on_core.
    141  */
    142 #define _ISR_Flash( _level ) \
     140 *             previously returned by @ref _ISR_Disable_on_this_core.
     141 */
     142#define _ISR_Flash_on_this_core( _level ) \
    143143  do { \
    144144    RTEMS_COMPILER_MEMORY_BARRIER(); \
     
    146146    RTEMS_COMPILER_MEMORY_BARRIER(); \
    147147  } while (0)
     148
     149#if defined(RTEMS_SMP)
     150
     151/**
     152 *  @brief Initialize SMP Interrupt Critical Section Support
     153 *
     154 *  This method initializes the variables required by the SMP implementation
     155 *  of interrupt critical section management.
     156 */
     157void _ISR_SMP_Initialize(void);
     158
     159/**
     160 *  @brief Enter Interrupt Critical Section on SMP System
     161 *
     162 *  This method is used to enter an interrupt critical section that
     163 *  is honored across all cores in an SMP system.
     164 *
     165 *  @return This method returns the previous interrupt mask level.
     166 */
     167ISR_Level _ISR_SMP_Disable(void);
     168
     169/**
     170 *  @brief Exit Interrupt Critical Section on SMP System
     171 *
     172 *  This method is used to exit an interrupt critical section that
     173 *  is honored across all cores in an SMP system.
     174 *
     175 *  @param[in] level contains the interrupt level mask level
     176 *             previously returned by @ref _ISR_SMP_Disable.
     177 */
     178void _ISR_SMP_Enable(ISR_Level level);
     179
     180/**
     181 *  @brief Temporarily Exit Interrupt Critical Section on SMP System
     182 *
     183 *  This method is used to temporarily exit an interrupt critical section
     184 *  that is honored across all cores in an SMP system.
     185 *
     186 *  @param[in] level contains the interrupt level mask level
     187 *             previously returned by @ref _ISR_SMP_Disable.
     188 */
     189void _ISR_SMP_Flash(ISR_Level level);
     190
     191/**
     192 *  @brief Enter SMP interrupt code
     193 *
     194 *  This method is used to enter the SMP interrupt section.
     195 *
     196 *  @return This method returns the isr level.
     197 */
     198int _ISR_SMP_Enter(void);
     199
     200/**
     201 *  @brief Exit SMP interrupt code
     202 *
     203 *  This method is used to exit the SMP interrupt.
     204 *
     205 *  @return This method returns 0 on a simple return and returns 1 on a
     206 *  dispatching return.
     207 */
     208int _ISR_SMP_Exit(void);
     209
     210#endif
     211
     212/**
     213 *  @brief Enter Interrupt Disable Critical Section
     214 *
     215 *  This routine enters an interrupt disable critical section.  When
     216 *  in an SMP configuration, this involves obtaining a spinlock to ensure
     217 *  that only one core is inside an interrupt disable critical section.
     218 *  When on a single core system, this only involves disabling local
     219 *  CPU interrupts.
     220 *
     221 *  @return The argument @a _level will contain the previous interrupt
     222 *          mask level.
     223 */
     224#if defined(RTEMS_SMP)
     225  #define _ISR_Disable( _level ) \
     226    _level = _ISR_SMP_Disable();
     227#else
     228  #define _ISR_Disable( _level ) \
     229    _ISR_Disable_on_this_core( _level );
     230#endif
     231 
     232/**
     233 *  @brief Exits Interrupt Disable Critical Section
     234 *
     235 *  This routine exits an interrupt disable critical section.  When
     236 *  in an SMP configuration, this involves releasing a spinlock.
     237 *  When on a single core system, this only involves disabling local
     238 *  CPU interrupts.
     239 *
     240 *  @return The argument @a _level will contain the previous interrupt
     241 *          mask level.
     242 */
     243#if defined(RTEMS_SMP)
     244  #define _ISR_Enable( _level ) \
     245    _ISR_SMP_Enable( _level );
     246#else
     247  #define _ISR_Enable( _level ) \
     248    _ISR_Enable_on_this_core( _level );
     249#endif
     250
     251/**
     252 *  @brief Temporarily Exit Interrupt Disable Critical Section
     253 *
     254 *  This routine is used to temporarily enable interrupts
     255 *  during a long critical section.  It is used in long sections of
     256 *  critical code when a point is reached at which interrupts can
     257 *  be temporarily enabled.  Deciding where to flash interrupts
     258 *  in a long critical section is often difficult and the point
     259 *  must be selected with care to ensure that the critical section
     260 *  properly protects itself.
     261 *
     262 *  @return The argument @a _level will contain the previous interrupt
     263 *          mask level.
     264 */
     265#if defined(RTEMS_SMP)
     266  #define _ISR_Flash( _level ) \
     267    _ISR_SMP_Flash( _level );
     268#else
     269  #define _ISR_Flash( _level ) \
     270    _ISR_Flash_on_this_core( _level );
     271#endif
    148272
    149273/**
     
    202326 *  performed when the outermost interrupt service routine exits.
    203327 *
    204  *  @note  Implemented in assembly language.
     328 *  @note  Typically implemented in assembly language.
    205329 */
    206330void _ISR_Handler( void );
  • cpukit/score/src/isr.c

    r3f1545b rdad36c52  
    8181#endif
    8282
     83#if defined(RTEMS_SMP)
     84  _ISR_SMP_Initialize();
     85#endif
    8386}
  • cpukit/score/src/smp.c

    r3f1545b rdad36c52  
    1919#include <rtems/score/thread.h>
    2020
    21 #if defined(RTEMS_SMP)
    22   #define RTEMS_DEBUG
    23 #endif
    24 
    2521#if defined(RTEMS_DEBUG)
    2622  #include <rtems/bspIo.h>
     
    3329{
    3430  Thread_Control *heir;
     31  ISR_Level       level;
     32
     33  _ISR_Disable_on_this_core( level );
    3534
    3635  /*
     
    5150void rtems_smp_secondary_cpu_initialize(void)
    5251{
    53   int cpu;
    54 
    55   cpu = bsp_smp_processor_id();
    56 
     52  int       cpu;
     53  ISR_Level level;
     54
     55  cpu = bsp_smp_processor_id();
     56
     57  _ISR_Disable_on_this_core( level );
    5758  bsp_smp_secondary_cpu_initialize(cpu);
    58 
    59   #if defined(RTEMS_DEBUG)
    60     printk( "Made it to %d -- ", cpu );
    61   #endif
    6259
    6360  /*
     
    6865  _Per_CPU_Information[cpu].state = RTEMS_BSP_SMP_CPU_INITIALIZED;
    6966
     67  #if defined(RTEMS_DEBUG)
     68    printk( "Made it to %d -- ", cpu );
     69  #endif
     70
    7071  /*
    7172   *  With this secondary core out of reset, we can wait for the
    7273   *  request to switch to the first task.
    73    *
    74    *  XXX When SMP ISR code is complete, do we want interrupts on
    75    *  XXX or off at this point?
    7674   */
    77   _ISR_Set_level( 0 );
    7875  while(1) {
     76    uint32_t   message;
     77
    7978    bsp_smp_wait_for(
    8079      (volatile unsigned int *)&_Per_CPU_Information[cpu].message,
     
    8281      10000
    8382    );
     83
     84    level = _SMP_lock_spinlock_simple_Obtain( &_Per_CPU_Information[cpu].lock );
     85      message = _Per_CPU_Information[cpu].message;
     86      if ( message & RTEMS_BSP_SMP_FIRST_TASK ) {
     87        _SMP_lock_spinlock_simple_Release( &_Per_CPU_Information[cpu].lock, level );
     88        _ISR_Set_level( 0 );
     89      }
     90     
     91    _SMP_lock_spinlock_simple_Release( &_Per_CPU_Information[cpu].lock, level );
    8492  }
    8593}
     
    120128
    121129  if ( message & RTEMS_BSP_SMP_FIRST_TASK ) {
    122     /*
    123      * XXX Thread dispatch disable level at this point will have to be
    124      * XXX revisited when Interrupts on SMP is addressed.
    125      */
    126     _Thread_Dispatch_disable_level--; /* undo ISR code */
    127130    _Per_CPU_Information[cpu].isr_nest_level = 0;
    128131    _Per_CPU_Information[cpu].message &= ~message;
     
    130133
    131134    _SMP_lock_spinlock_simple_Release( &_Per_CPU_Information[cpu].lock, level );
    132     _Thread_Disable_dispatch();
     135
    133136    rtems_smp_run_first_task(cpu);
    134137    /* does not return */
     
    136139
    137140  if ( message & RTEMS_BSP_SMP_SHUTDOWN ) {
    138     /*
    139      * XXX Thread dispatch disable level at this point will have to be
    140      * XXX revisited when Interrupts on SMP is addressed.
    141      */
    142141    _Per_CPU_Information[cpu].message &= ~message;
    143     _SMP_lock_spinlock_simple_Release( &_Per_CPU_Information[cpu].lock, level );
    144 
    145     _Thread_Dispatch_disable_level--; /* undo ISR code */
     142
    146143    _Per_CPU_Information[cpu].isr_nest_level = 0;
    147144    _Per_CPU_Information[cpu].state = RTEMS_BSP_SMP_CPU_SHUTDOWN;
    148     _ISR_Disable( level );
     145    _SMP_lock_spinlock_simple_Release( &_Per_CPU_Information[cpu].lock, level );
     146
     147    _Thread_Enable_dispatch();       /* undo ISR code */
     148    _ISR_Disable_on_this_core( level );
    149149    while(1)
    150150      ;
     
    156156      printk( "switch needed\n" );
    157157    #endif
    158     /*
    159      * XXX Thread dispatch disable level at this point will have to be
    160      * XXX revisited when Interrupts on SMP is addressed.
    161      */
    162158    _Per_CPU_Information[cpu].message &= ~message;
    163159    _SMP_lock_spinlock_simple_Release( &_Per_CPU_Information[cpu].lock, level );
     
    175171  ISR_Level level;
    176172
     173  #if defined(RTEMS_DEBUG)
     174    if ( message & RTEMS_BSP_SMP_SIGNAL_TO_SELF )
     175      printk( "Send 0x%x to %d\n", message, cpu );
     176  #endif
     177
    177178  level = _SMP_lock_spinlock_simple_Obtain( &_Per_CPU_Information[cpu].lock );
    178179    _Per_CPU_Information[cpu].message |= message;
     
    211212  int    cpu;
    212213
     214  _Per_CPU_Information[cpu].state = RTEMS_BSP_SMP_CPU_UP;
    213215  for (cpu=1 ; cpu < _SMP_Processor_count ; cpu++ ) {
    214216    _SMP_Send_message( cpu, RTEMS_BSP_SMP_FIRST_TASK );
    215     while (_Per_CPU_Information[cpu].state != RTEMS_BSP_SMP_CPU_UP ) {
    216       bsp_smp_wait_for(
    217         (volatile unsigned int *)&_Per_CPU_Information[cpu].state,
    218         RTEMS_BSP_SMP_CPU_UP,
    219         10000
    220       );
    221     }
    222217  }
    223218}
     
    244239      continue;
    245240    _SMP_Send_message( i, RTEMS_BSP_SMP_CONTEXT_SWITCH_NECESSARY );
    246     bsp_smp_wait_for(
    247       (volatile unsigned int *)&_Per_CPU_Information[i].message,
    248       0,
    249       10000
    250     );
    251241  }
    252242}
     
    257247void _SMP_Request_other_cores_to_shutdown(void)
    258248{
    259   bool allDown;
    260   int  ncpus;
    261   int  cpu;
    262 
     249  bool   allDown;
     250  int    ncpus;
     251  int    n;
     252  int    cpu;
     253
     254  cpu   = bsp_smp_processor_id();
    263255  ncpus = _SMP_Processor_count;
    264256
     
    266258
    267259  allDown = true;
    268   for (cpu=1 ; cpu<ncpus ; cpu++ ) {
     260  for (n=0 ; n<ncpus ; n++ ) {
     261     if ( n == cpu )
     262       continue;
    269263     bsp_smp_wait_for(
    270        (unsigned int *)&_Per_CPU_Information[cpu].state,
     264       (unsigned int *)&_Per_CPU_Information[n].state,
    271265       RTEMS_BSP_SMP_CPU_SHUTDOWN,
    272266       10000
    273267    );
    274     if ( _Per_CPU_Information[cpu].state != RTEMS_BSP_SMP_CPU_SHUTDOWN )
     268    if ( _Per_CPU_Information[n].state != RTEMS_BSP_SMP_CPU_SHUTDOWN )
    275269      allDown = false;
    276270  }
    277271  if ( !allDown )
    278     printk( "All CPUs not successfully shutdown -- timed out\n" );
    279   #if defined(RTEMS_DEBUG)
    280     else 
     272    printk( "not all down -- timed out\n" );
     273  #if defined(RTEMS_DEBUG)
     274    else
    281275      printk( "All CPUs shutdown successfully\n" );
    282276  #endif
  • cpukit/score/src/smplock.c

    r3f1545b rdad36c52  
    1717#include <rtems/score/smplock.h>
    1818#include <rtems/score/smp.h>
    19 
    20 #if defined (RTEMS_DEBUG)
     19#include <rtems/score/isr.h>
     20
     21/*
     22 * Some debug stuff that is being left in, but disabled.  This will keep
     23 * a log of lock/unlock sequences that can be printed out when the
     24 * lockcount appears to have gotten off track.
     25 */
     26/* #define SMPLOCK_DEBUG */
     27#if defined (SMPLOCK_DEBUG)
     28  #include <rtems/score/thread.h>
    2129  #include <rtems/bspIo.h>
    22 #endif
    23 
     30  #include <rtems/score/percpu.h>
     31  #if (0)
     32    #define  ENABLE_ONESHOT_DEBUG_LOGGING
     33  #else
     34    #define ENABLE_LOOPED_DEBUG_LOGGING
     35  #endif
     36  #define ENABLE_DEBUG_LOGGING
     37#endif
     38
     39/*
     40 * Prototypes and structures used in the debug lock/unlock error log.
     41 */
     42#if defined(ENABLE_DEBUG_LOGGING)
     43  typedef struct {
     44    char      action;
     45    char      lock;
     46    char      cpu;
     47    char      count;
     48    uint32_t  nest_level;
     49    void      *ret1;
     50    void      *ret2;
     51    void      *ret3;
     52    void      *ret4;
     53  } debug_spinlog_t;
     54
     55  extern void start(void);
     56  extern void _fini(void);
     57
     58  #define DEBUG_SPINLOG_MAX 1024
     59  debug_spinlog_t DEBUG_SPINLOG[DEBUG_SPINLOG_MAX];
     60  int DEBUG_SPINLOG_INDEX = 0;
     61
     62  static void debug_logit(
     63    char                             act,
     64    SMP_lock_spinlock_nested_Control *lock
     65  );
     66  static void debug_dump_log(void);
     67#else
     68  #define debug_logit( _act, _lock )
     69  #define debug_dump_log()
     70#endif
     71
     72/*
     73 * SMP spinlock simple methods
     74 */
    2475void _SMP_lock_spinlock_simple_Initialize(
    2576  SMP_lock_spinlock_simple_Control *lock
     
    3384)
    3485{
    35    ISR_Level  level;
     86   ISR_Level  level = 0;
    3687   uint32_t   value = 1;
    3788   uint32_t   previous;
    3889
    3990   /* Note: Disable provides an implicit memory barrier. */
    40   _ISR_Disable( level );
     91  _ISR_Disable_on_this_core( level );
    4192   do {
     93     RTEMS_COMPILER_MEMORY_BARRIER();
    4294     SMP_CPU_SWAP( lock, value, previous );
     95     RTEMS_COMPILER_MEMORY_BARRIER();
    4396   } while (previous == 1);
    4497
     
    52105{
    53106   *lock = 0;
    54    _ISR_Enable( level );
    55 }
    56 
     107   _ISR_Enable_on_this_core( level );
     108}
     109
     110/*
     111 * SMP spinlock nested methods.
     112 */
    57113void _SMP_lock_spinlock_nested_Initialize(
    58114  SMP_lock_spinlock_nested_Control *lock
     
    60116{
    61117  lock->count = 0;
    62   lock->cpu_id = 0;
     118  lock->cpu_id = -1;
     119}
     120
     121void _SMP_lock_spinlock_nested_Release(
     122  SMP_lock_spinlock_nested_Control *lock,
     123  ISR_Level                        level
     124)
     125{
     126  #if defined (RTEMS_DEBUG) || defined(SMPLOCK_DEBUG)
     127    if ( lock->count == 0 ) {
     128      printk(
     129        "\ncpu %d lock %d Releasing spinlock when count is already "
     130        "zero (%p from %p,%p)?!?!\n",
     131        bsp_smp_processor_id(), 
     132        lock->cpu_id,
     133        lock,
     134        __builtin_return_address(0),
     135        __builtin_return_address(1)
     136      );
     137      debug_dump_log();
     138      return;
     139    }
     140  #endif
     141
     142  /* assume we actually have it */
     143  if (lock->count == 1) {
     144    lock->cpu_id = -1;
     145    debug_logit( 'U', lock );
     146    RTEMS_COMPILER_MEMORY_BARRIER();
     147    lock->count  = 0;
     148  } else {
     149    debug_logit( 'u', lock );
     150    lock->count--;
     151  }
     152
     153  _ISR_Enable_on_this_core( level );
    63154}
    64155
     
    73164
    74165  /* Note: Disable provides an implicit memory barrier. */
    75   _ISR_Disable( level );
     166  _ISR_Disable_on_this_core( level );
    76167
    77168  cpu_id = bsp_smp_processor_id();
    78169
    79   /* Deal with nested calls from one cpu */
    80   if ( (lock->count > 0) && (cpu_id == lock->cpu_id) ) {
    81     lock->count++;
    82     return level;
    83   }
    84 
    85   do {
    86     SMP_CPU_SWAP( lock, value, previous );
    87   } while (previous == 1);
    88 
    89   lock->count++;
     170  /*
     171   *  Attempt to obtain the lock.  If we do not get it immediately, then
     172   *  do a single "monitor" iteration.  This should allow the loop to back
     173   *  off the bus a bit and allow the other core to finish sooner.
     174   */
     175  while (1) {
     176    RTEMS_COMPILER_MEMORY_BARRIER();
     177    SMP_CPU_SWAP( &lock->count, value, previous );
     178    RTEMS_COMPILER_MEMORY_BARRIER();
     179    if ( previous == 0 ) {
     180      /* was not locked */
     181      break;
     182    }
     183
     184    /* Deal with nested calls from one cpu */
     185    if (cpu_id == lock->cpu_id) {
     186      lock->count++;
     187      debug_logit( 'l', lock );
     188      return level;
     189    }
     190  }
     191
    90192  lock->cpu_id = cpu_id;
     193  debug_logit( 'L', lock );
    91194
    92195  return level;
    93196}
    94197
    95 void _SMP_lock_spinlock_nested_Release(
    96   SMP_lock_spinlock_nested_Control *lock,
    97   ISR_Level                        level
    98 )
    99 {
    100 #if defined(RTEMS_DEBUG)
    101   if ( lock->count == 0 )
    102     printk ("Releasing spinlock when count is already zero?!?!\n");
    103 #endif
    104   lock->count--;
    105 
    106   _ISR_Enable( level );
    107 }
     198/*
     199 * Debug log for debugging nested lock/unlock problems.
     200 */
     201#if defined(ENABLE_DEBUG_LOGGING)
     202  static void debug_logit(
     203    char                             act,
     204    SMP_lock_spinlock_nested_Control *lock
     205  )
     206  {
     207    debug_debug_spinlog_t *sp;
     208    if ( DEBUG_SPINLOG_INDEX == DEBUG_SPINLOG_MAX )
     209      #if defined (ENABLE_LOOPED_DEBUG_LOGGING)
     210        DEBUG_SPINLOG_INDEX = 0;
     211      #else
     212        return;
     213      #endif
     214
     215    sp = &DEBUG_SPINLOG[ DEBUG_SPINLOG_INDEX++ ];
     216    sp->action = act;
     217
     218    #if 0
     219      if ( lock == &_ISR_SMP_Lock )
     220        sp->lock = 'I';
     221      else
     222    #endif
     223    if ( lock == &_Thread_Dispatch_disable_level_lock )
     224      sp->lock   = 'D';
     225    sp->cpu    = bsp_smp_processor_id() + '0';
     226    sp->count  = lock->count;
     227    #if 0
     228      if ( sp->lock == 'I' ) {
     229        if ( _Thread_Dispatch_smp_spin_lock.id == 0 )
     230          printk( "not nested %p from %p %p %p %p\n", sp,
     231          __builtin_return_address(0), __builtin_return_address(1),
     232          __builtin_return_address(2), __builtin_return_address(3)
     233        );
     234      }
     235    #endif
     236    sp->nest_level =  _ISR_Nest_level;
     237    sp->ret1 = 0;
     238    sp->ret2 = 0;
     239    sp->ret3 = 0;
     240    sp->ret4 = 0;
     241    sp->ret1 = __builtin_return_address(0);
     242    if ( sp->ret1 >= start && sp->ret1 <= _fini ) {
     243      sp->ret2   = __builtin_return_address(1);
     244      if ( sp->ret2 >= start && sp->ret2 <= _fini ) {
     245        sp->ret3   = __builtin_return_address(2);
     246        if ( sp->ret3 >= start && sp->ret3 <= _fini ) {
     247          sp->ret4   = __builtin_return_address(3);
     248        }
     249      }
     250    }
     251  }
     252 
     253  static void debug_dump_log(void)
     254  {
     255    debug_debug_spinlog_t *sp;
     256    int       index;
     257    bool      done =false;
     258   
     259    #if defined (ENABLE_ONESHOT_DEBUG_LOGGING)
     260      index = 0;
     261    #else
     262      if (DEBUG_SPINLOG_INDEX >= DEBUG_SPINLOG_MAX)
     263        index = 0;
     264      else
     265        index = DEBUG_SPINLOG_INDEX;
     266    #endif
     267
     268
     269    do {
     270      sp = &DEBUG_SPINLOG[ index ];
     271      printk("%d) act %c lock %c cpu %c count=%d nest %d (%p, %p, %p, %p)\n",
     272        index, sp->action, sp->lock, sp->cpu, sp->count, sp->nest_level,
     273        sp->ret1, sp->ret2, sp->ret3, sp->ret4
     274      );
     275
     276      index++;
     277      if (index == DEBUG_SPINLOG_INDEX)
     278        break;
     279      if (index >= DEBUG_SPINLOG_MAX)
     280        index = 0;
     281    } while (1);
     282  }
     283#endif
  • cpukit/score/src/threaddispatch.c

    r3f1545b rdad36c52  
    170170
    171171post_switch:
    172   _Thread_Dispatch_set_disable_level( 0 );
    173172
    174173  _ISR_Enable( level );
    175174
     175  _Thread_Unnest_dispatch();
     176 
    176177  _API_extensions_Run_postswitch();
    177178}
  • cpukit/score/src/threaddispatchdisablelevel.c

    r3f1545b rdad36c52  
    6767  level = _Thread_Dispatch_disable_level;
    6868
    69   _ISR_Enable(isr_level);
    70 
     69  _ISR_Enable_on_this_core(isr_level);
    7170  return level;
    7271}
     
    8079   *  accesses to the dispatch disable level.
    8180   */
    82 
    83   _ISR_Disable( isr_level );
     81  _ISR_Disable_on_this_core( isr_level );
    8482
    8583  _Thread_Dispatch_disable_level--;
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