Changeset d9af2ed4 in rtems


Ignore:
Timestamp:
Aug 20, 2012, 8:15:20 AM (7 years ago)
Author:
Thomas Doerfler <thomas.doerfler@…>
Branches:
4.11, master
Children:
6f89813
Parents:
bd5a1386
git-author:
Thomas Doerfler <thomas.doerfler@…> (08/20/12 08:15:20)
git-committer:
Sebastian Huber <sebastian.huber@…> (08/20/12 08:16:32)
Message:

bsp/gen83xx: Add br_uid BSP variant

Location:
c/src/lib
Files:
2 added
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/gen83xx/Makefile.am

    rbd5a1386 rd9af2ed4  
    4343    startup/linkcmds.mpc8309som \
    4444    startup/linkcmds.mpc8313erdb \
     45    startup/linkcmds.br_uid \
    4546    startup/linkcmds.mpc8349eamds \
    4647    startup/linkcmds.hsc_cm01
  • c/src/lib/libbsp/powerpc/gen83xx/configure.ac

    rbd5a1386 rd9af2ed4  
    3636[if defined, then use settings for the MPC8309SOM board])
    3737
     38RTEMS_BSPOPTS_SET([MPC83XX_BOARD_BR_UID],[br_uid],[1])
     39RTEMS_BSPOPTS_HELP([MPC83XX_BOARD_BR_UID],
     40[if defined, then use settings for the BR UID board])
     41
    3842RTEMS_BSPOPTS_SET([MPC83XX_CHIP_TYPE],[mpc8309som],[8309])
     43RTEMS_BSPOPTS_SET([MPC83XX_CHIP_TYPE],[br_uid],[8309])
    3944RTEMS_BSPOPTS_SET([MPC83XX_CHIP_TYPE],[mpc8349eamds],[8349])
    4045RTEMS_BSPOPTS_SET([MPC83XX_CHIP_TYPE],[hsc_cm01],[8349])
  • c/src/lib/libbsp/powerpc/gen83xx/include/hwreg_vals.h

    rbd5a1386 rd9af2ed4  
    107107                          RCWHR_LDP_SPC)
    108108
     109#elif defined(MPC83XX_BOARD_BR_UID)
     110/*
     111 * for BR UID
     112 */
     113/*
     114 * one DUART channel (UART1) supported
     115 */
     116#define GEN83xx_DUART_AVAIL_MASK 0x01
     117
     118/* we need the low level initialization in start.S*/
     119#define NEED_LOW_LEVEL_INIT
     120/*
     121 * clocking infos
     122 */
     123#define BSP_CLKIN_FRQ 25000000L
     124#define RCFG_SYSPLL_MF  5
     125#define RCFG_COREPLL_MF 5
     126/*
     127 * Reset configuration words
     128 */
     129#define RESET_CONF_WRD_L \
     130  (RCWLR_LBIUCM_1_1                                                     \
     131   | RCWLR_DDRCM_2_1                                                    \
     132   | RCWLR_SPMF(RCFG_SYSPLL_MF)                                         \
     133   | RCWLR_COREPLL(RCFG_COREPLL_MF)                                     \
     134   | RCWLR_CEVCOD_1_2                                                   \
     135   | RCWLR_CEPMF(8)                                                     \
     136   )
     137
     138#define RESET_CONF_WRD_H (RCWHR_PCI_HOST     |  \
     139                          RCWHR_PCI_32       |  \
     140                          RCWHR_PCI1ARB_DIS  |  \
     141                          RCWHR_CORE_EN      |  \
     142                          RCWHR_BMS_LOW      |  \
     143                          RCWHR_BOOTSEQ_NONE |  \
     144                          RCWHR_SW_DIS       |  \
     145                          RCWHR_ROMLOC_LB16  |  \
     146                          RCWHR_RLEXT_LGCY   |  \
     147                          RCWHR_ENDIAN_BIG)
     148
    109149#elif defined( HAS_UBOOT)
    110150
     
    259299#define DDR_SDRAM_INTERVAL_VAL       0x05080000
    260300
     301#elif defined(MPC83XX_BOARD_BR_UID)
     302/**************************
     303 * for BR UID
     304 */
     305
     306/*
     307 * working values for various registers, used in start/start.S
     308 */
     309
     310/*
     311 * Local Access Windows
     312 * FIXME: decode bit settings
     313 */
     314
     315#define LBLAWBAR0_VAL  bsp_rom_start
     316#define LBLAWAR0_VAL   0x80000018
     317#define DDRLAWBAR0_VAL bsp_ram_start
     318#define DDRLAWAR0_VAL  0x8000001B
     319
     320
     321/*
     322 * clocking for local bus:
     323 * ALE active for 1 clock
     324 * local bus clock = 1/2 csb clock
     325 */
     326#define LCRR_VAL  0x80010002
     327
     328/*
     329 * DDR-SDRAM registers
     330 * FIXME: decode bit settings
     331 */
     332#define DDRCDR_VAL                   0x00000001
     333#define CS0_BNDS_VAL                 0x0000000F
     334#define CS0_CONFIG_VAL               0x80014202
     335#define TIMING_CFG_0_VAL             0x00220802
     336#define TIMING_CFG_1_VAL             0x26259222
     337#define TIMING_CFG_2_VAL             0x111048C7
     338#define DDR_SDRAM_CFG_2_VAL          0x00401000
     339#define DDR_SDRAM_MODE_VAL           0x200F1632
     340#define DDR_SDRAM_MODE_2_VAL         0x40006000
     341#define DDR_SDRAM_CLK_CNTL_VAL       0x01800000
     342#define DDR_SDRAM_CFG_VAL            0x43100008
     343
     344#define DDR_ERR_DISABLE_VAL          0x0000008D
     345#define DDR_ERR_DISABLE_VAL2         0x00000089
     346#define DDR_SDRAM_DATA_INIT_VAL      0xC01DCAFE
     347#define DDR_SDRAM_INIT_ADDR_VAL      0
     348#define DDR_SDRAM_INTERVAL_VAL       0x01E8222E
     349
    261350#elif defined( HAS_UBOOT)
    262351
  • c/src/lib/libbsp/powerpc/gen83xx/preinstall.am

    rbd5a1386 rd9af2ed4  
    126126PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.mpc8313erdb
    127127
     128$(PROJECT_LIB)/linkcmds.br_uid: startup/linkcmds.br_uid $(PROJECT_LIB)/$(dirstamp)
     129        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.br_uid
     130PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.br_uid
     131
    128132$(PROJECT_LIB)/linkcmds.mpc8349eamds: startup/linkcmds.mpc8349eamds $(PROJECT_LIB)/$(dirstamp)
    129133        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.mpc8349eamds
  • c/src/lib/libbsp/powerpc/gen83xx/start/start.S

    rbd5a1386 rd9af2ed4  
    369369        blr                     /* now further execution RAM */
    370370copy_rest_of_text:
     371        LWI  r31,IMMRBAR
    371372#ifdef LCRR_VAL
    372373        SET_IMM_REGW r31,r30,LCRR_OFF,LCRR_VAL
  • c/src/lib/libcpu/powerpc/mpc83xx/include/mpc83xx.h

    rbd5a1386 rd9af2ed4  
    921921#define RCWLR_COREPLL(n) (((n)&0xff)<<(31-15))
    922922
     923/* for MPC8309: */
     924#define RCWLR_CEVCOD_1_4 (0<<(31-25))     /* QUICC internal PLL divider 1:4 */
     925#define RCWLR_CEVCOD_1_2 (2<<(31-25))     /* QUICC internal PLL divider 1:2 */
     926                                          /* QUICC Engine PLL mult. factor */
     927#define RCWLR_CEPDF_2     (1<<(31-26))    /* QUICC Engine divide PLL out by 2*/
     928                                          /* QUICC Engine PLL mult. factor */
     929#define RCWLR_CEPMF(n) (((n)&0x1f)<<(31-31))
     930
    923931                                           /* PCI host mode          */
    924932#define RCWHR_PCI_AGENT  (0 << (31- 0))    /* agent mode             */
     
    975983#define RCWHR_LDP_SPC     (1 << (31-30))   /* LDP0-3 are special pins */
    976984
     985/*
     986 * For MPC8309:
     987 */
     988#define RCWHR_RLEXT_LGCY  (0 << (31-13))  /* Boot ROM loc. extension: Legacy */
     989#define RCWHR_RLEXT_NAND  (1 << (31-13))  /* Boot ROM loc. extension: NAND Fl.*/
     990#define RCWHR_RLEXT_RSV2  (2 << (31-13))  /* Boot ROM loc. extension: resrvd */
     991#define RCWHR_RLEXT_RSV3  (3 << (31-13))  /* Boot ROM loc. extension: resrvd */
    977992#endif /* _MPC83XX_MPC83XX_H */
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