Index: cpukit/score/cpu/bfin/.cvsignore
===================================================================
--- cpukit/score/cpu/bfin/.cvsignore	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/.cvsignore	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,2 @@
+Makefile
+Makefile.in
Index: cpukit/score/cpu/bfin/ChangeLog
===================================================================
--- cpukit/score/cpu/bfin/ChangeLog	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/ChangeLog	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,9 @@
+2006-10-23	Joel Sherrill <joel@OARcorp.com>
+
+	* .cvsignore, ChangeLog, Makefile.am, cpu.c, cpu_asm.S, irq.c,
+	preinstall.am, rtems/asm.h, rtems/score/bfin.h, rtems/score/cpu.h,
+	rtems/score/cpu_asm.h, rtems/score/types.h: New files.
+
+2006-10-20  Alain Schaefer <alani@easc.ch>
+
+    * all files : Initial version 
Index: cpukit/score/cpu/bfin/Makefile.am
===================================================================
--- cpukit/score/cpu/bfin/Makefile.am	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/Makefile.am	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,19 @@
+##
+## $Id$
+##
+
+include $(top_srcdir)/automake/compile.am
+
+include_rtemsdir = $(includedir)/rtems
+include_rtems_HEADERS = rtems/asm.h
+
+include_rtems_scoredir = $(includedir)/rtems/score
+include_rtems_score_HEADERS = rtems/score/cpu.h rtems/score/bfin.h \
+    rtems/score/cpu_asm.h rtems/score/types.h
+
+noinst_LIBRARIES = libscorecpu.a
+libscorecpu_a_SOURCES = cpu.c irq.c cpu_asm.S
+libscorecpu_a_CPPFLAGS = $(AM_CPPFLAGS)
+
+include $(srcdir)/preinstall.am
+include $(top_srcdir)/automake/local.am
Index: cpukit/score/cpu/bfin/cpu.c
===================================================================
--- cpukit/score/cpu/bfin/cpu.c	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/cpu.c	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,225 @@
+/*  Blackfin CPU Dependent Source
+ *
+ *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
+ *             written by Alain Schaefer <alain.schaefer@easc.ch>
+ *                    and Antonio Giovanini <antonio@atos.com.br>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/wkspace.h>
+#include <rtems/score/bfin.h>
+
+/*  _CPU_Initialize
+ *
+ *  This routine performs processor dependent initialization.
+ *
+ *  INPUT PARAMETERS:
+ *    cpu_table       - CPU table to initialize
+ *    thread_dispatch - address of disptaching routine
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)      /* ignored on this CPU */
+)
+{
+  /*
+   *  The thread_dispatch argument is the address of the entry point
+   *  for the routine called at the end of an ISR once it has been
+   *  decided a context switch is necessary.  On some compilation
+   *  systems it is difficult to call a high-level language routine
+   *  from assembly.  This allows us to trick these systems.
+   *
+   *  If you encounter this problem save the entry point in a CPU
+   *  dependent variable.
+   */
+
+  _CPU_Thread_dispatch_pointer = thread_dispatch;
+
+  /*
+   *  If there is not an easy way to initialize the FP context
+   *  during Context_Initialize, then it is usually easier to
+   *  save an "uninitialized" FP context here and copy it to
+   *  the task's during Context_Initialize.
+   */
+
+  /* FP context initialization support goes here */
+
+  _CPU_Table = *cpu_table;
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_Get_level
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+uint32_t   _CPU_ISR_Get_level( void )
+{
+  /*
+   *  This routine returns the current interrupt level.
+   */
+
+    register uint32_t   _tmpimask;
+
+    /*read from the IMASK registers*/
+
+    _tmpimask = *((uint32_t*)IMASK);
+
+    return _tmpimask;
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_raw_handler
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_ISR_install_raw_handler(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+   proc_ptr *interrupt_table = NULL;
+  /*
+   *  This is where we install the interrupt handler into the "raw" interrupt
+   *  table used by the CPU to dispatch interrupt handlers.
+   */
+
+   /* base of vector table on blackfin architecture */
+   interrupt_table = (void*)0xFFE02000;
+
+   *old_handler = interrupt_table[ vector ];
+   interrupt_table[ vector ] = new_handler;
+
+}
+
+/*PAGE
+ *
+ *  _CPU_ISR_install_vector
+ *
+ *  This kernel routine installs the RTEMS handler for the
+ *  specified vector.
+ *
+ *  Input parameters:
+ *    vector      - interrupt vector number
+ *    old_handler - former ISR for this vector number
+ *    new_handler - replacement ISR for this vector number
+ *
+ *  Output parameters:  NONE
+ *
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_ISR_install_vector(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+)
+{
+   *old_handler = _ISR_Vector_table[ vector ];
+
+   /*
+    *  If the interrupt vector table is a table of pointer to isr entry
+    *  points, then we need to install the appropriate RTEMS interrupt
+    *  handler for this vector number.
+    */
+
+   _CPU_ISR_install_raw_handler( vector, _ISR_Handler, old_handler );
+
+   /*
+    *  We put the actual user ISR address in '_ISR_vector_table'.  This will
+    *  be used by the _ISR_Handler so the user gets control.
+    */
+
+    _ISR_Vector_table[ vector ] = new_handler;
+}
+
+/*
+ * Copied from the arm port.
+ */
+void _CPU_Context_Initialize(
+  Context_Control  *the_context,
+  uint32_t         *stack_base,
+  uint32_t          size,
+  uint32_t          new_level,
+  void             *entry_point,
+  boolean           is_fp
+)
+{
+    uint32_t     stack_high;  /* highest "stack aligned" address */
+    stack_high = ((uint32_t  )(stack_base) + size);
+
+    the_context->register_sp = stack_high;
+    // gcc/config/bfin/bfin.h defines CPU_MINIMUM_STACK_FRAME_SIZE = 0 thus we do sp=fp
+    // is this correct ?????
+    the_context->register_fp = stack_high;
+    the_context->register_rets = (uint32_t) entry_point;
+
+    //mask the interrupt level
+}
+
+
+
+/*PAGE
+ *
+ *  _CPU_Install_interrupt_stack
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Install_interrupt_stack( void )
+{
+}
+
+/*PAGE
+ *
+ *  _CPU_Thread_Idle_body
+ *
+ *  NOTES:
+ *
+ *  1. This is the same as the regular CPU independent algorithm.
+ *
+ *  2. If you implement this using a "halt", "idle", or "shutdown"
+ *     instruction, then don't forget to put it in an infinite loop.
+ *
+ *  3. Be warned. Some processors with onboard DMA have been known
+ *     to stop the DMA if the CPU were put in IDLE mode.  This might
+ *     also be a problem with other on-chip peripherals.  So use this
+ *     hook with caution.
+ *
+ *  NO_CPU Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+void _CPU_Thread_Idle_body( void )
+{
+
+  for( ; ; )
+    /* insert your "halt" instruction here */ ;
+}
Index: cpukit/score/cpu/bfin/cpu_asm.S
===================================================================
--- cpukit/score/cpu/bfin/cpu_asm.S	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/cpu_asm.S	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,406 @@
+/*  cpu_asm.S
+ *
+ *  This file contains the basic algorithms for all assembly code used
+ *  in the Blackfin port of RTEMS.  These algorithms must be implemented
+ *  in assembly language
+ *
+ *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
+ *             written by Alain Schaefer <alain.schaefer@easc.ch>
+ *                    and Antonio Giovanini <antonio@atos.com.br>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+ 
+ 
+#include <rtems/asm.h>
+#include <rtems/score/cpu_asm.h>
+#include <rtems/score/bfin.h>
+
+
+/*  _CPU_Context_switch
+ *
+ *  This routine performs a normal non-FP context switch.
+ *
+ *  bfin Specific Information:
+ *
+ *  For now we simply save all registers.
+ *  
+ */
+
+.globl __CPU_Context_switch
+__CPU_Context_switch:
+    /* Start saving context R0 = current, R1=heir */
+    /*save P0 first*/
+    [FP+0x8] = P0;
+    P0 = R0;
+    [ P0 + R0_OFFSET ] = R0;
+    [ P0 + R1_OFFSET] = R1;
+    [ P0 + R2_OFFSET] = R2;
+    [ P0 + R4_OFFSET] = R4;
+    [ P0 + R3_OFFSET] = R3;
+    [ P0 + R5_OFFSET] = R5;
+    [ P0 + R6_OFFSET] = R6;
+    [ P0 + R7_OFFSET] = R7;
+    [ P0 + P1_OFFSET] = P1;
+    /* save the original value of P0 */
+    P1 = [FP+0x8];
+    [ P0 + P0_OFFSET] = P1;
+    [ P0 + P2_OFFSET] = P2;
+    [ P0 + P3_OFFSET] = P3;
+    [ P0 + P4_OFFSET] = P4;
+    [ P0 + P5_OFFSET] = P5;
+    [ P0 + FP_OFFSET] = FP; 
+    [ P0 + SP_OFFSET] = SP;
+    
+    /* save ASTAT */
+    R0 = ASTAT;
+    [P0 + ASTAT_OFFSET] = R0;
+
+    /* save Loop Counters */
+    R0 = LC0;
+    [P0 + LC0_OFFSET] = R0;
+    R0 = LC1;
+    [P0 + LC1_OFFSET] = R0;
+
+    /* save Accumulators */
+    R0 = A0.W;
+    [P0 + A0W_OFFSET] = R0;
+    R0 = A0.X;
+    [P0 + A0X_OFFSET] = R0;
+    R0 = A1.W;
+    [P0 + A1W_OFFSET] = R0;
+    R0 = A1.X;
+    [P0 + A1X_OFFSET] = R0;
+    
+    /* save Index Registers */
+    R0 = I0;
+    [P0 + I0_OFFSET] = R0;
+    R0 = I1;
+    [P0 + I1_OFFSET] = R0;
+    R0 = I2;
+    [P0 + I2_OFFSET] = R0;
+    R0 = I3;
+    [P0 + I3_OFFSET] = R0;
+
+    /* save Modifier Registers */
+    R0 = M0;
+    [P0 + M0_OFFSET] = R0;
+    R0 = M1;
+    [P0 + M1_OFFSET] = R0;
+    R0 = M2;
+    [P0 + M2_OFFSET] = R0;
+    R0 = M3;
+    [P0 + M3_OFFSET] = R0;
+
+    /* save Length Registers */
+    R0 = L0;
+    [P0 + L0_OFFSET] = R0;
+    R0 = L1;
+    [P0 + L1_OFFSET] = R0;
+    R0 = L2;
+    [P0 + L2_OFFSET] = R0;
+    R0 = L3;
+    [P0 + L3_OFFSET] = R0;
+
+    /* Base Registers */
+    R0 = B0;
+    [P0 + B0_OFFSET] = R0;
+    R0 = B1;
+    [P0 + B1_OFFSET] = R0;
+    R0 = B2;
+    [P0 + B2_OFFSET] = R0;
+    R0 = B3;
+    [P0 + B3_OFFSET] = R0;
+    
+    /* save RETS */
+    R0 = RETS;
+    [ P0 + RETS_OFFSET] = R0; 
+
+restore:
+    P0 = R1;
+    R1 = [P0 + R1_OFFSET];  
+    R2 = [P0 + R2_OFFSET];
+    R3 = [P0 + R3_OFFSET];
+    R4 = [P0 + R4_OFFSET];
+    R5 = [P0 + R5_OFFSET];
+    R6 = [P0 + R6_OFFSET];
+    R7 = [P0 + R7_OFFSET];
+        
+    P2 = [P0 + P2_OFFSET];
+    P3 = [P0 + P3_OFFSET];
+    P4 = [P0 + P4_OFFSET];
+    P5 = [P0 + P5_OFFSET];
+
+    /* might have to be placed more to the end */
+    FP = [P0 + FP_OFFSET];
+    SP = [P0 + SP_OFFSET];
+
+    /* save ASTAT */
+    R0 = [P0 + ASTAT_OFFSET];
+    ASTAT = R0;
+
+    /* save Loop Counters */
+    R0 = [P0 + LC0_OFFSET];
+    LC0 = R0;
+    R0 = [P0 + LC1_OFFSET];
+    LC1 = R0;
+
+    /* save Accumulators */
+    R0 = [P0 + A0W_OFFSET];
+    A0.W = R0;
+    R0 = [P0 + A0X_OFFSET];
+    A0.X = R0;
+    R0 = [P0 + A1W_OFFSET];
+    A1.W = R0;
+    R0 = [P0 + A1X_OFFSET];
+    A1.X = R0;
+
+    /* save Index Registers */
+    R0 = [P0 + I0_OFFSET];
+    I0 = R0;
+    R0 = [P0 + I1_OFFSET];
+    I1 = R0;
+    R0 = [P0 + I2_OFFSET];
+    I2 = R0;
+    R0 = [P0 + I3_OFFSET];
+    I3 = R0;
+
+    /* save Modifier Registers */
+    R0 = [P0 + M0_OFFSET];
+    M0 = R0;
+    R0 = [P0 + M1_OFFSET];
+    M1 = R0;
+    R0 = [P0 + M2_OFFSET];
+    M2 = R0;
+    R0 = [P0 + M3_OFFSET];
+    M3 = R0;
+
+    /* save Length Registers */
+    R0 = [P0 + L0_OFFSET];
+    L0 = R0;
+    R0 = [P0 + L1_OFFSET];
+    L1 = R0;
+    R0 = [P0 + L2_OFFSET];
+    L2 = R0;
+    R0 = [P0 + L3_OFFSET];
+    L3 = R0;
+
+    /* Base Registers */
+    R0 = [P0 + B0_OFFSET];
+    B0 = R0;
+    R0 = [P0 + B1_OFFSET];
+    B1 = R0;
+    R0 = [P0 + B2_OFFSET];
+    B2 = R0;
+    R0 = [P0 + B3_OFFSET];
+    B3 = R0;
+
+    /* restore RETS */
+    P1 = [P0 + RETS_OFFSET];
+    RETS = P1;
+
+    /* now restore the P1 + P0 */
+    P1 = [P0 + R1_OFFSET];    
+    P0 = [P0 + P0_OFFSET];
+    
+    rts;
+    
+
+/*
+ *  _CPU_Context_restore
+ *
+ *  This routine is generally used only to restart self in an
+ *  efficient manner.  It may simply be a label in _CPU_Context_switch.
+ *
+ *  NOTE: May be unnecessary to reload some registers.
+ *
+ *  Blackfin Specific Information:
+ *
+ *  none
+ *
+ */
+.globl __CPU_Context_restore
+__CPU_Context_restore:
+    jump restore;
+
+
+
+.globl __ISR_Thread_Dispatch
+__ISR_Thread_Dispatch:
+
+    .extern __Thread_Dispatch
+    R0.l = __Thread_Dispatch;
+    R0.h = __Thread_Dispatch;
+  
+    /* Puts the address of th Thread_Dispatch function on Stack
+     * Where it will be restored to the RTI register
+     */
+    P0 = [FP];
+    /* save the old reti */
+    R1 = [P0+0xc];
+    [P0+0xc] = R0;
+    /*
+     * Overwriting the RETS Register is save because Thread_Dispatch is
+     * disabled when we are between call/link or unlink/rts
+     */
+    [P0+0x8] = R1;
+  
+    /* save old rets */
+  
+    rts;
+
+
+.globl __ISR_Handler
+__ISR_Handler:
+    /* First of all check the Stackpointer and */
+    /* switch to Scratchpad if necessary        */
+     
+    /* save P0 and R0 in the scratchpad */
+    USP = P0;
+    
+    /* load base adress of scratchpad */
+    P0.H = HI(SCRATCH);
+    P0.L = LO(SCRATCH);
+
+    /* if SP is already inside the SCRATCHPAD */ 
+    CC=SP<P0 (iu)
+    if !CC jump continue;
+    
+    /* set PO to top of scratchpad */   
+    P0.h=HI(SCRATCH_TOP);
+    P0.l=LO(SCRATCH_TOP);
+    /*save the old SP*/ 
+    [P0] = SP;
+    /*P0 += -4;*/
+    /*set the new Stackpointer*/
+    SP = P0;
+    /*restore the old PO*/
+    
+    /* The Stackpointer is now setup as we want */  
+    continue:
+    /* restore P0 and save some context */
+    P0 = USP;
+    /* save some state on the isr stack (scratchpad), this enables interrupt nesting */
+    [--SP] = RETI;
+    [--SP] = RETS;
+    [--SP] = ASTAT;
+    [--SP] = FP;
+    FP = SP;
+    [--SP] = (R7:0, P5:0) ;
+    
+    
+    /* Context is saved, now check which Instruction we were executing
+     * If we were between a call and link or between a unlink and rts
+     * we have to disable Thread_Dispatch because correct restore of context after
+     * Thread_Dispatch would not be possible. */
+    
+    P0 = RETI;
+    R0 = W[P0];
+    /* shift 16 bits to the right (select the high nibble ) */
+    /*R0 >>= 16;*/
+    
+    R3 = 0;
+    /* Check if RETI is a LINK instruction */
+    R1.h = HI(0xE800);
+    R1.l = LO(0xE800);
+    CC=R0==R1; 
+    if cc jump disablethreaddispatch;
+    
+    /* Check if RETI is a RTS instruction */
+    R1.h = HI(0x0010);
+    R1.l = LO(0x0010);
+    CC=R0==R1; 
+    if cc jump disablethreaddispatch;
+    
+    jump afterthreaddispatch;
+    
+    disablethreaddispatch:
+    /*  _Thread_Dispatch_disable_level++   */
+    .extern _Thread_Dispatch_disable_level
+    P0.H = __Thread_Dispatch_disable_level;
+    P0.L = __Thread_Dispatch_disable_level;
+    R0 = [P0];
+    R0 += 1;
+    [P0] = R0;
+    R3 = 1;
+    
+    afterthreaddispatch:
+    /* Put R3 on the stack */
+    [--SP] = R3;
+
+    /* Obtain a bitlist of the pending interrupts. */
+    P0.H = HI(IPEND);
+    P0.L = LO(IPEND);   
+    R1 = [P0];
+    
+    /*
+     * Search through the bit list stored in R0 to find the first enabled
+     * bit. The offset of this bit is the index of the interrupt that is
+     * to be handled.
+     */
+    R0 = -1;
+    intloop:
+        R0 += 1;
+        R1 = ROT R1 by -1;
+        if !cc jump intloop;
+     
+
+    /* pass SP as parameter to the C function */
+    R1 = SP
+
+    /* pass values by register as well as by stack */
+    /* to comply with the c calling conventions    */
+    [--SP] = R0;
+    [--SP] = R1;
+    
+    .extern _ISR_Handler2
+    call    _ISR_Handler2
+
+    /* inc 2 to compensate the passing of arguments */
+    R3 = [SP++];
+    R3 = [SP++];
+    /* check if _Thread_Dispatch_disable_level has been incremented */
+    R3 = [SP++]
+    CC=R3==0
+    if cc jump dont_decrement;
+    .extern _Thread_Dispatch_disable_level
+    P0.H = __Thread_Dispatch_disable_level;
+    P0.L = __Thread_Dispatch_disable_level;
+    R0 = [P0];
+    R0 += -1;
+    [P0] = R0;
+    
+    dont_decrement:
+    
+    (R7:0, P5:0) = [SP++];
+    FP =    [SP++];
+    ASTAT = [SP++];
+    RETS =  [SP++];
+    RETI =  [SP++];
+    /* Interrupts are now disabled again */
+    
+    /*should restore the old stack !!!*/
+    /*if sp now points to SCRATCH_TOP */
+    
+    /* load base adress of scratchpad */
+    USP = P0;
+    P0.H = HI(SCRATCH_TOP);
+    P0.L = LO(SCRATCH_TOP);
+    
+    CC=SP==P0
+    if !cc jump restoreP0
+    /* restore the stack */
+    SP=[P0];
+    
+    restoreP0:
+    P0 = USP;
+        
+    /*now we should be on the old "user-stack" again */ 
+        
+    /* return from interrupt, will jump to adress stored in RETI */
+    RTI;
+
Index: cpukit/score/cpu/bfin/irq.c
===================================================================
--- cpukit/score/cpu/bfin/irq.c	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/irq.c	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,106 @@
+/*  Blackfin CPU Dependent Source
+ *
+ *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
+ *             written by Alain Schaefer <alain.schaefer@easc.ch>
+ *                    and Antonio Giovanini <antonio@atos.com.br>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+ 
+ 
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/thread.h>
+
+/*
+ *  This routine provides the RTEMS interrupt management.
+ */
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  unsigned long    *_old_stack_ptr;
+#endif
+
+register unsigned long  *stack_ptr asm("SP");
+
+void ISR_Handler2(uint32_t   vector, void *isr_sp)
+{
+  register uint32_t   level;
+
+  _CPU_ISR_Disable( level );
+
+  _Thread_Dispatch_disable_level++;
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 ) {
+    /* Install irq stack */
+    _old_stack_ptr = stack_ptr;
+    stack_ptr = _CPU_Interrupt_stack_high;
+  }
+#endif
+
+  _ISR_Nest_level++;
+
+  /* leave it to the ISR to decide if they get reenabled */
+  _CPU_ISR_Enable( level );
+
+  /* call isp */
+  if ( _ISR_Vector_table[ vector] )
+    (*_ISR_Vector_table[ vector ])(
+       vector, isr_sp - sizeof(CPU_Interrupt_frame) + 1 );
+
+  _CPU_ISR_Disable( level );
+
+  _ISR_Nest_level--;
+
+#if( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 )       /* restore old stack pointer */
+    stack_ptr = _old_stack_ptr;
+#endif
+
+  _Thread_Dispatch_disable_level--;
+
+  _CPU_ISR_Enable( level );
+
+  if ( _ISR_Nest_level )
+    return;
+
+  if ( _Thread_Dispatch_disable_level ) {
+    _ISR_Signals_to_thread_executing = FALSE;
+    return;
+  }
+
+  if ( _Context_Switch_necessary || _ISR_Signals_to_thread_executing ) {
+    _ISR_Signals_to_thread_executing = FALSE;
+    _ISR_Thread_Dispatch();
+    /*_Thread_Running->Registers.register_rets = current_thread_pc;*/
+  }
+}
+
+uint32_t SIC_IAR_Value ( uint8_t Vector )
+{
+  switch ( Vector ){
+    case 7:
+      return 0x00000000;
+    case 8:
+      return 0x11111111;
+    case 9:
+      return 0x22222222;
+    case 10:
+      return 0x33333333;
+    case 11:
+      return 0x44444444;
+    case 12:
+      return 0x55555555;
+    case 13:
+      return 0x66666666;
+    case 14:
+      return 0x77777777;
+    case 15:
+      return 0x88888888;
+  }
+}
Index: cpukit/score/cpu/bfin/preinstall.am
===================================================================
--- cpukit/score/cpu/bfin/preinstall.am	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/preinstall.am	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,45 @@
+## Automatically generated by ampolish3 - Do not edit
+
+if AMPOLISH3
+$(srcdir)/preinstall.am: Makefile.am
+	$(AMPOLISH3) $(srcdir)/Makefile.am > $(srcdir)/preinstall.am
+endif
+
+PREINSTALL_DIRS =
+DISTCLEANFILES = $(PREINSTALL_DIRS)
+
+all-am: $(PREINSTALL_FILES)
+
+PREINSTALL_FILES =
+CLEANFILES = $(PREINSTALL_FILES)
+
+$(PROJECT_INCLUDE)/rtems/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)/rtems
+	@: > $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/asm.h: rtems/asm.h $(PROJECT_INCLUDE)/rtems/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/asm.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/asm.h
+
+$(PROJECT_INCLUDE)/rtems/score/$(dirstamp):
+	@$(mkdir_p) $(PROJECT_INCLUDE)/rtems/score
+	@: > $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+PREINSTALL_DIRS += $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+
+$(PROJECT_INCLUDE)/rtems/score/cpu.h: rtems/score/cpu.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu.h
+
+$(PROJECT_INCLUDE)/rtems/score/bfin.h: rtems/score/bfin.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/bfin.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/bfin.h
+
+$(PROJECT_INCLUDE)/rtems/score/cpu_asm.h: rtems/score/cpu_asm.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/cpu_asm.h
+
+$(PROJECT_INCLUDE)/rtems/score/types.h: rtems/score/types.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/types.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/types.h
+
Index: cpukit/score/cpu/bfin/rtems/asm.h
===================================================================
--- cpukit/score/cpu/bfin/rtems/asm.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/rtems/asm.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,125 @@
+/**
+ * @file rtems/asm.h
+ *
+ *  This include file attempts to address the problems
+ *  caused by incompatible flavors of assemblers and
+ *  toolsets.  It primarily addresses variations in the
+ *  use of leading underscores on symbols and the requirement
+ *  that register names be preceded by a %.
+ */
+
+/*
+ *  NOTE: The spacing in the use of these macros
+ *        is critical to them working as advertised.
+ *
+ *  COPYRIGHT:
+ *
+ *  This file is based on similar code found in newlib available
+ *  from ftp.cygnus.com.  The file which was used had no copyright
+ *  notice.  This file is freely distributable as long as the source
+ *  of the file is noted.  This file is:
+ *
+ *  COPYRIGHT (c) 1994-2006.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_ASM_H
+#define _RTEMS_ASM_H
+
+/*
+ *  Indicate we are in an assembly file and get the basic CPU definitions.
+ */
+
+#ifndef ASM
+#define ASM
+#endif
+#include <rtems/score/cpuopts.h>
+#include <rtems/score/bfin.h>
+
+#ifndef __USER_LABEL_PREFIX__
+/**
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ *
+ *  This symbol is prefixed to all C program symbols.
+ */
+#define __USER_LABEL_PREFIX__ _
+#endif
+
+#ifndef __REGISTER_PREFIX__
+/**
+ *  Recent versions of GNU cpp define variables which indicate the
+ *  need for underscores and percents.  If not using GNU cpp or
+ *  the version does not support this, then you will obviously
+ *  have to define these as appropriate.
+ *
+ *  This symbol is prefixed to all register names.
+ */
+#define __REGISTER_PREFIX__
+#endif
+
+#include <rtems/concat.h>
+
+/** Use the right prefix for global labels.  */
+#define SYM(x) CONCAT1 (__USER_LABEL_PREFIX__, x)
+
+/** Use the right prefix for registers.  */
+#define REG(x) CONCAT1 (__REGISTER_PREFIX__, x)
+
+/*
+ *  define macros for all of the registers on this CPU
+ *
+ *  EXAMPLE:     #define d0 REG (d0)
+ */
+
+/*
+ *  Define macros to handle section beginning and ends.
+ */
+
+
+/** This macro is used to denote the beginning of a code declaration. */
+#define BEGIN_CODE_DCL .text
+/** This macro is used to denote the end of a code declaration. */
+#define END_CODE_DCL
+/** This macro is used to denote the beginning of a data declaration section. */
+#define BEGIN_DATA_DCL .data
+/** This macro is used to denote the end of a data declaration section. */
+#define END_DATA_DCL
+/** This macro is used to denote the beginning of a code section. */
+#define BEGIN_CODE .text
+/** This macro is used to denote the end of a code section. */
+#define END_CODE
+/** This macro is used to denote the beginning of a data section. */
+#define BEGIN_DATA
+/** This macro is used to denote the end of a data section. */
+#define END_DATA
+/** This macro is used to denote the beginning of the
+ *  unitialized data section.
+ */
+#define BEGIN_BSS
+/** This macro is used to denote the end of the unitialized data section.  */
+#define END_BSS
+/** This macro is used to denote the end of the assembly file.  */
+#define END
+
+/**
+ *  This macro is used to declare a public global symbol.
+ *
+ *  @note This must be tailored for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+#define PUBLIC(sym) .globl SYM (sym)
+
+/**
+ *  This macro is used to prototype a public global symbol.
+ *
+ *  @note This must be tailored for a particular flavor of the C compiler.
+ *  They may need to put underscores in front of the symbols.
+ */
+#define EXTERN(sym) .globl SYM (sym)
+
+#endif
Index: cpukit/score/cpu/bfin/rtems/score/bfin.h
===================================================================
--- cpukit/score/cpu/bfin/rtems/score/bfin.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/rtems/score/bfin.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,456 @@
+/*  bfin.h
+ *
+ *  This file sets up basic CPU dependency settings based on 
+ *  compiler settings.  For example, it can determine if
+ *  floating point is available.  This particular implementation
+ *  is specified to the Blackfin port.
+ *
+ *
+ *  COPYRIGHT (c) 1989-2006.
+ *  On-Line Applications Research Corporation (OAR).
+ *             modified by Alain Schaefer <alain.schaefer@easc.ch>
+ *                     and Antonio Giovanini <antonio@atos.com.br>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ *
+ */
+
+#ifndef _RTEMS_SCORE_BFIN_H
+#define _RTEMS_SCORE_BFIN_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*
+ *  This file contains the information required to build
+ *  RTEMS for a particular member of the Blackfin family.
+ *  It does this by setting variables to indicate which
+ *  implementation dependent features are present in a particular
+ *  member of the family.
+ *
+ *  This is a good place to list all the known CPU models
+ *  that this port supports and which RTEMS CPU model they correspond
+ *  to.
+ */
+ 
+/*
+ *  Figure out all CPU Model Feature Flags based upon compiler 
+ *  predefines. 
+ */
+#if defined(BFIN)
+#define CPU_MODEL_NAME  "BF533"
+#define BF_HAS_FPU   0
+#else
+ 
+#error "Unsupported CPU Model"
+ 
+#endif
+
+/*
+ *  Define the name of the CPU family.
+ */
+ 
+#define CPU_NAME "BFIN"
+
+#define MK_BMSK_( x ) (1<<x)    
+
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
+
+/* Scratchpad SRAM */
+ 
+#define SCRATCH                0xFFB00000
+#define SCRATCH_SIZE           0x1000
+#define SCRATCH_TOP            0xFFB00ffc
+
+
+
+/* System Interrupt Controller Chapter 4*/
+#define SIC_RVECT              0xFFC00108
+#define SIC_IMASK              0xFFC0010C
+#define SIC_IAR0               0xFFC00110
+#define SIC_IAR1               0xFFC00114
+#define SIC_IAR2               0xFFC00118
+#define SIC_ISR                0xFFC00120
+#define SIC_IWR                0xFFC00124
+
+/* Event Vector Table        Chapter 4 */
+
+#define EVT0                   0xFFE02000  
+#define EVT1                   0xFFE02004  
+#define EVT2                   0xFFE02008  
+#define EVT3                   0xFFE0200C  
+#define EVT4                   0xFFE02010  
+#define EVT5                   0xFFE02014  
+#define EVT6                   0xFFE02018  
+#define EVT7                   0xFFE0201C  
+#define EVT8                   0xFFE02020  
+#define EVT9                   0xFFE02024  
+#define EVT10                  0xFFE02028  
+#define EVT11                  0xFFE0202C  
+#define EVT12                  0xFFE02030  
+#define EVT13                  0xFFE02034  
+#define EVT14                  0xFFE02038  
+#define EVT15                  0xFFE0203C  
+#define IMASK                  0xFFE02104  
+#define IPEND                  0xFFE02108  
+#define ILAT                   0xFFE0210C  
+#define IPRIO                  0xFFE02110  
+
+/* Clock and System Control  Chapter 8 */
+#define PLL_CTL                0xFFC00000
+#define PLL_DIV                0xFFC00004
+#define VR_CTL                 0xFFC00008
+#define PLL_STAT               0xFFC0000C
+#define PLL_LOCKCNT            0xFFC00010
+#define SWRST                  0xFFC00100
+#define SYSCR                  0xFFC00104
+
+/* SPI Controller           Chapter 10 */
+#define SPI_CTL                0xFFC00500
+#define SPI_FLG                0xFFC00504
+#define SPI_STAT               0xFFC00508
+#define SPI_TDBR               0xFFC0050C
+#define SPI_RDBR               0xFFC00510
+#define SPI_BAUD               0xFFC00514
+#define SPI_SHADOW             0xFFC00518
+
+/* SPORT0 Controller */
+#define SPORT0_TCR1            0xFFC00800 
+#define SPORT0_TCR2            0xFFC00804
+#define SPORT0_TCLKDIV         0xFFC00808
+#define SPORT0_TFSDIV          0xFFC0080C
+#define SPORT0_TX              0xFFC00810
+#define SPORT0_RX              0xFFC00818
+#define SPORT0_RCR1            0xFFC00820
+#define SPORT0_RCR2            0xFFC00824
+#define SPORT0_RCLKDIV         0xFFC00828
+#define SPORT0_RFSDIV          0xFFC0082C
+#define SPORT0_STAT            0xFFC00830
+#define SPORT0_CHNL            0xFFC00834
+#define SPORT0_MCMC1           0xFFC00838
+#define SPORT0_MCMC2           0xFFC0083C
+#define SPORT0_MTCS0           0xFFC00840
+#define SPORT0_MTCS1           0xFFC00844
+#define SPORT0_MTCS2           0xFFC00848
+#define SPORT0_MTCS3           0xFFC0084C
+#define SPORT0_MRCS0           0xFFC00850
+#define SPORT0_MRCS1           0xFFC00854
+#define SPORT0_MRCS2           0xFFC00858
+#define SPORT0_MRCS3           0xFFC0085C
+
+/* Parallel Peripheral Interface (PPI) Chapter 11 */
+  
+#define PPI_CONTROL            0xFFC01000
+#define PPI_STATUS             0xFFC01004
+#define PPI_COUNT              0xFFC01008
+#define PPI_DELAY              0xFFC0100C
+#define PPI_FRAME              0xFFC01010
+
+/*********  PPI MASKS ***********/         
+/*  PPI_CONTROL Masks */        
+#define PORT_EN                0x00000001 
+#define PORT_DIR               0x00000002      
+#define XFR_TYPE               0x0000000C 
+#define PORT_CFG               0x00000030
+#define FLD_SEL                0x00000040
+#define PACK_EN                0x00000080
+#define DMA32                  0x00000100
+#define SKIP_EN                0x00000200
+#define SKIP_EO                0x00000400
+#define DLENGTH                0x00003800 
+#define DLEN_8                 0x0
+#define DLEN(x)                (((x-9) & 0x07) << 11)
+#define POL                    0x0000C000      
+
+/* PPI_STATUS Masks */                                         
+#define FLD                    0x00000400  
+#define FT_ERR                 0x00000800
+#define OVR                    0x00001000
+#define UNDR                   0x00002000
+#define ERR_DET                0x00004000
+#define ERR_NCOR               0x00008000
+
+/* SPORT1 Controller        Chapter 12 */
+#define SPORT1_TCR1            0xFFC00900
+#define SPORT1_TCR2            0xFFC00904
+#define SPORT1_TCLKDIV         0xFFC00908
+#define SPORT1_TFSDIV          0xFFC0090C
+#define SPORT1_TX              0xFFC00910
+#define SPORT1_RX              0xFFC00918
+#define SPORT1_RCR1            0xFFC00920
+#define SPORT1_RCR2            0xFFC00924
+#define SPORT1_RCLKDIV         0xFFC00928
+#define SPORT1_RFSDIV          0xFFC0092C
+#define SPORT1_STAT            0xFFC00930
+#define SPORT1_CHNL            0xFFC00934
+#define SPORT1_MCMC1           0xFFC00938
+#define SPORT1_MCMC2           0xFFC0093C
+#define SPORT1_MTCS0           0xFFC00940
+#define SPORT1_MTCS1           0xFFC00944
+#define SPORT1_MTCS2           0xFFC00948
+#define SPORT1_MTCS3           0xFFC0094C
+#define SPORT1_MRCS0           0xFFC00950
+#define SPORT1_MRCS1           0xFFC00954
+#define SPORT1_MRCS2           0xFFC00958
+#define SPORT1_MRCS3           0xFFC0095C
+
+/* SPORTx_TCR1 Masks */
+#define TSPEN                  0x0001
+#define ITCLK                  0x0002   
+#define TDTYPE                 0x000C  
+#define TLSBIT                 0x0010  
+#define ITFS                   0x0200   
+#define TFSR                   0x0400   
+#define DITFS                  0x0800   
+#define LTFS                   0x1000   
+#define LATFS                  0x2000   
+#define TCKFE                  0x4000   
+
+/* SPORTx_TCR2 Masks */
+#define SLEN                   0x001F 
+#define TXSE                   0x0100
+#define TSFSE                  0x0200
+#define TRFST                  0x0400 
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN                  0x0001 
+#define IRCLK                  0x0002 
+#define RDTYPE                 0x000C
+#define RULAW                  0x0008 
+#define RALAW                  0x000C 
+#define RLSBIT                 0x0010
+#define IRFS                   0x0200 
+#define RFSR                   0x0400 
+#define LRFS                   0x1000 
+#define LARFS                  0x2000 
+#define RCKFE                  0x4000 
+
+/* SPORTx_RCR2 Masks */
+#define SLEN                   0x001F 
+#define RXSE                   0x0100
+#define RSFSE                  0x0200
+#define RRFST                  0x0400 
+
+/* SPORTx_STAT Masks */
+#define RXNE                   0x0001
+#define RUVF                   0x0002
+#define ROVF                   0x0004
+#define TXF                    0x0008
+#define TUVF                   0x0010
+#define TOVF                   0x0020
+#define TXHRE                  0x0040
+
+/* SPORTx_MCMC1 Masks */
+#define WSIZE                  0x0000F000
+#define WOFF                   0x000003FF
+
+/* SPORTx_MCMC2 Masks */
+#define MCCRM                  0x00000003
+#define MCDTXPE                0x00000004
+#define MCDRXPE                0x00000008
+#define MCMEN                  0x00000010
+#define FSDR                   0x00000080
+#define MFD                    0x0000F000   
+
+/* UART Controller          Chapter 13 */
+#define UART_THR               0xFFC00400
+#define UART_RBR               0xFFC00400
+#define UART_DLL               0xFFC00400
+#define UART_IER               0xFFC00404
+#define UART_DLH               0xFFC00404
+#define UART_IIR               0xFFC00408
+#define UART_LCR               0xFFC0040C
+#define UART_MCR               0xFFC00410
+#define UART_LSR               0xFFC00414
+
+#define UART_SCR               0xFFC0041C
+#define UART_GCTL              0xFFC00424
+
+/* 
+ * UART CONTROLLER MASKS
+ */
+
+/* UART_LCR */
+#define DLAB                   0x80
+#define SB                     0x40
+#define STP                    0x20
+#define EPS                    0x10
+#define PEN                    0x08
+#define STB                    0x04
+#define WLS(x)                 ((x-5) & 0x03)
+
+#define DLAB_P                 0x07
+#define SB_P                   0x06
+#define STP_P                  0x05
+#define EPS_P                  0x04
+#define PEN_P                  0x03
+#define STB_P                  0x02
+#define WLS_P1                 0x01
+#define WLS_P0                 0x00
+
+/* UART_MCR */
+#define LOOP_ENA               0x10
+#define LOOP_ENA_P             0x04
+
+/* UART_LSR */
+#define TEMT                   0x40
+#define THRE                   0x20
+#define BI                     0x10
+#define FE                     0x08
+#define PE                     0x04
+#define OE                     0x02
+#define DR                     0x01
+
+#define TEMP_P                 0x06
+#define THRE_P                 0x05
+#define BI_P                   0x04
+#define FE_P                   0x03
+#define PE_P                   0x02
+#define OE_P                   0x01
+#define DR_P                   0x00
+
+/* UART_IER */
+#define ELSI                   0x04
+#define ETBEI                  0x02
+#define ERBFI                  0x01
+
+#define ELSI_P                 0x02
+#define ETBEI_P                0x01
+#define ERBFI_P                0x00
+
+/* UART_IIR */
+#define STATUS(x)              ((x << 1) & 0x06)
+#define NINT                   0x01
+#define STATUS_P1              0x02
+#define STATUS_P0              0x01
+#define NINT_P                 0x00
+
+/* UART_GCTL */
+#define FFE                    0x20
+#define FPE                    0x10
+#define RPOLC                  0x08
+#define TPOLC                  0x04
+#define IREN                   0x02
+#define UCEN                   0x01
+
+#define FFE_P                  0x05
+#define FPE_P                  0x04
+#define RPOLC_P                0x03
+#define TPOLC_P                0x02
+#define IREN_P                 0x01
+#define UCEN_P                 0x00
+
+/* General Purpose IO        Chapter 14*/
+#define FIO_FLAG_D             0xFFC00700
+#define FIO_FLAG_C             0xFFC00704  
+#define FIO_FLAG_S             0xFFC00708  
+#define FIO_FLAG_T             0xFFC0070C  
+#define FIO_MASKA_D            0xFFC00710  
+#define FIO_MASKA_C            0xFFC00714  
+#define FIO_MASKA_S            0xFFC00718
+#define FIO_MASKA_T            0xFFC0071C
+#define FIO_MASKB_D            0xFFC00720
+#define FIO_MASKB_C            0xFFC00724
+#define FIO_MASKB_S            0xFFC00728
+#define FIO_MASKB_T            0xFFC0072C
+#define FIO_DIR                0xFFC00730
+#define FIO_POLAR              0xFFC00734
+#define FIO_EDGE               0xFFC00738
+#define FIO_BOTH               0xFFC0073C
+#define FIO_INEN               0xFFC00740
+
+/*  General Purpose IO Masks */
+#define PF0                    0x0001
+#define PF1                    0x0002
+#define PF2                    0x0004
+#define PF3                    0x0008
+#define PF4                    0x0010
+#define PF5                    0x0020
+#define PF6                    0x0040
+#define PF7                    0x0080
+#define PF8                    0x0100
+#define PF9                    0x0200
+#define PF10                   0x0400
+#define PF11                   0x0800
+#define PF12                   0x1000
+#define PF13                   0x2000
+#define PF14                   0x4000
+#define PF15                   0x8000
+ 
+
+/* TIMER 0, 1, 2            Chapter 15 */
+#define TIMER0_CONFIG          0xFFC00600
+#define TIMER0_COUNTER         0xFFC00604
+#define TIMER0_PERIOD          0xFFC00608
+#define TIMER0_WIDTH           0xFFC0060C
+
+#define TIMER1_CONFIG          0xFFC00610  
+#define TIMER1_COUNTER         0xFFC00614        
+#define TIMER1_PERIOD          0xFFC00618         
+#define TIMER1_WIDTH           0xFFC0061C          
+
+#define TIMER2_CONFIG          0xFFC00620  
+#define TIMER2_COUNTER         0xFFC00624        
+#define TIMER2_PERIOD          0xFFC00628         
+#define TIMER2_WIDTH           0xFFC0062C          
+
+#define TIMER_ENABLE           0xFFC00640
+#define TIMER_DISABLE          0xFFC00644
+#define TIMER_STATUS           0xFFC00648
+ 
+/* Core Timer               Chapter 15 */
+#define TCNTL                  0xFFE03000
+#define TPERIOD                0xFFE03004
+#define TSCALE                 0xFFE03008
+#define TCOUNT                 0xFFE0300C
+
+/* Masks for Timer Control */
+#define TMPWR                  0x00000001  
+#define TMREN                  0x00000002  
+#define TAUTORLD               0x00000004  
+#define TINT                   0x00000008 
+
+/* Event Bit Positions */
+#define EVT_IVTMR_P            0x00000006
+#define EVT_IVTMR              MK_BMSK_(EVT_IVTMR_P )  
+
+/* Real Time Clock          Chapter 16 */
+#define RTC_STAT               0xFFC00300
+#define RTC_ICTL               0xFFC00304
+#define RTC_ISTAT              0xFFC00308
+#define RTC_SWCNT              0xFFC0030C
+#define RTC_ALARM              0xFFC00310
+#define RTC_FAST               0xFFC00314
+#define RTC_PREN               0xFFC00314
+
+/* RTC_FAST Mask (RTC_PREN Mask) */
+#define ENABLE_PRESCALE        0x00000001
+#define PREN                   0x00000001
+
+/* Asynchronous Memory Controller EBUI, Chapter 17*/ 
+#define EBIU_AMGCTL            0xFFC00A00  
+#define EBIU_AMBCTL0           0xFFC00A04
+#define EBIU_AMBCTL1           0xFFC00A08
+
+/* SDRAM Controller External Bus Interface Unit */
+
+#define EBIU_SDGCTL            0xFFC00A10
+#define EBIU_SDBCTL            0xFFC00A14
+#define EBIU_SDRRC             0xFFC00A18
+#define EBIU_SDSTAT            0xFFC00A1C
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTEMS_SCORE_BFIN_H */
Index: cpukit/score/cpu/bfin/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/bfin/rtems/score/cpu.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/rtems/score/cpu.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,1411 @@
+/**
+ * @file rtems/score/cpu.h
+ */
+
+/*
+ *  This include file contains information pertaining to the Blackfin
+ *  processor.
+ * 
+ *  COPYRIGHT (c) 1989-2006.
+ *  On-Line Applications Research Corporation (OAR).
+ *  adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch>
+ *                     and Antonio Giovanini <antonio@atos.com.br>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_SCORE_CPU_H
+#define _RTEMS_SCORE_CPU_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rtems/score/bfin.h>            /* pick up machine definitions */
+#ifndef ASM
+#include <rtems/score/types.h>
+#endif
+
+/* conditional compilation parameters */
+
+/**
+ *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ *
+ *  If TRUE, then they are inlined.
+ *  If FALSE, then a subroutine call is made.
+ *
+ *  This conditional is an example of the classic trade-off of size
+ *  versus speed.  Inlining the call (TRUE) typically increases the
+ *  size of RTEMS while speeding up the enabling of dispatching.
+ *
+ *  @note In general, the @ref _Thread_Dispatch_disable_level will
+ *  only be 0 or 1 unless you are in an interrupt handler and that
+ *  interrupt handler invokes the executive.]  When not inlined
+ *  something calls @ref _Thread_Enable_dispatch which in turns calls
+ *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
+ *  one subroutine call is avoided entirely.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_INLINE_ENABLE_DISPATCH       FALSE
+
+/**
+ *  Should the body of the search loops in _Thread_queue_Enqueue_priority
+ *  be unrolled one time?  In unrolled each iteration of the loop examines
+ *  two "nodes" on the chain being searched.  Otherwise, only one node
+ *  is examined per iteration.
+ *
+ *  If TRUE, then the loops are unrolled.
+ *  If FALSE, then the loops are not unrolled.
+ *
+ *  The primary factor in making this decision is the cost of disabling
+ *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ *  body of the loop.  On some CPUs, the flash is more expensive than
+ *  one iteration of the loop body.  In this case, it might be desirable
+ *  to unroll the loop.  It is important to note that on some CPUs, this
+ *  code is the longest interrupt disable period in RTEMS.  So it is
+ *  necessary to strike a balance when setting this parameter.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
+
+/**
+ *  Does RTEMS manage a dedicated interrupt stack in software?
+ *
+ *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ *  If FALSE, nothing is done.
+ *
+ *  If the CPU supports a dedicated interrupt stack in hardware,
+ *  then it is generally the responsibility of the BSP to allocate it
+ *  and set it up.
+ *
+ *  If the CPU does not support a dedicated interrupt stack, then
+ *  the porter has two options: (1) execute interrupts on the
+ *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ *  interrupt stack.
+ *
+ *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ *  possible that both are FALSE for a particular CPU.  Although it
+ *  is unclear what that would imply about the interrupt processing
+ *  procedure on that CPU.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
+
+/**
+ *  Does this CPU have hardware support for a dedicated interrupt stack?
+ *
+ *  If TRUE, then it must be installed during initialization.
+ *  If FALSE, then no installation is performed.
+ *
+ *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ *
+ *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ *  possible that both are FALSE for a particular CPU.  Although it
+ *  is unclear what that would imply about the interrupt processing
+ *  procedure on that CPU.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
+
+/**
+ *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ *
+ *  If TRUE, then the memory is allocated during initialization.
+ *  If FALSE, then the memory is allocated during initialization.
+ *
+ *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_ALLOCATE_INTERRUPT_STACK FALSE
+
+/**
+ *  Does the RTEMS invoke the user's ISR with the vector number and
+ *  a pointer to the saved interrupt frame (1) or just the vector 
+ *  number (0)?
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_ISR_PASSES_FRAME_POINTER 1
+
+/**
+ *  @def CPU_HARDWARE_FP
+ *
+ *  Does the CPU have hardware floating point?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ *
+ *  If there is a FP coprocessor such as the i387 or mc68881, then
+ *  the answer is TRUE.
+ *
+ *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
+ *  It indicates whether or not this CPU model has FP support.  For
+ *  example, it would be possible to have an i386_nofp CPU model
+ *  which set this to false to indicate that you have an i386 without
+ *  an i387 and wish to leave floating point support out of RTEMS.
+ */
+
+/** 
+ *  @def CPU_SOFTWARE_FP
+ *
+ *  Does the CPU have no hardware floating point and GCC provides a
+ *  software floating point implementation which must be context
+ *  switched?
+ *
+ *  This feature conditional is used to indicate whether or not there
+ *  is software implemented floating point that must be context 
+ *  switched.  The determination of whether or not this applies
+ *  is very tool specific and the state saved/restored is also
+ *  compiler specific.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#if ( BLACKFIN_CPU_HAS_FPU == 1 )
+#define CPU_HARDWARE_FP     TRUE
+#else
+#define CPU_HARDWARE_FP     FALSE
+#endif
+#define CPU_SOFTWARE_FP     FALSE
+
+/**
+ *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ *
+ *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ *
+ *  So far, the only CPUs in which this option has been used are the
+ *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
+ *  gcc both implicitly used the floating point registers to perform
+ *  integer multiplies.  Similarly, the PowerPC port of gcc has been
+ *  seen to allocate floating point local variables and touch the FPU
+ *  even when the flow through a subroutine (like vfprintf()) might
+ *  not use floating point formats.
+ *
+ *  If a function which you would not think utilize the FP unit DOES,
+ *  then one can not easily predict which tasks will use the FP hardware.
+ *  In this case, this option should be TRUE.
+ *
+ *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_ALL_TASKS_ARE_FP     FALSE
+
+/**
+ *  Should the IDLE task have a floating point context?
+ *
+ *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ *  and it has a floating point context which is switched in and out.
+ *  If FALSE, then the IDLE task does not have a floating point context.
+ *
+ *  Setting this to TRUE negatively impacts the time required to preempt
+ *  the IDLE task from an interrupt because the floating point context
+ *  must be saved as part of the preemption.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_IDLE_TASK_IS_FP      FALSE
+
+/**
+ *  Should the saving of the floating point registers be deferred
+ *  until a context switch is made to another different floating point
+ *  task?
+ *
+ *  If TRUE, then the floating point context will not be stored until
+ *  necessary.  It will remain in the floating point registers and not
+ *  disturned until another floating point task is switched to.
+ *
+ *  If FALSE, then the floating point context is saved when a floating
+ *  point task is switched out and restored when the next floating point
+ *  task is restored.  The state of the floating point registers between
+ *  those two operations is not specified.
+ *
+ *  If the floating point context does NOT have to be saved as part of
+ *  interrupt dispatching, then it should be safe to set this to TRUE.
+ *
+ *  Setting this flag to TRUE results in using a different algorithm
+ *  for deciding when to save and restore the floating point context.
+ *  The deferred FP switch algorithm minimizes the number of times
+ *  the FP context is saved and restored.  The FP context is not saved
+ *  until a context switch is made to another, different FP task.
+ *  Thus in a system with only one FP task, the FP context will never
+ *  be saved or restored.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
+
+/**
+ *  Does this port provide a CPU dependent IDLE task implementation?
+ *
+ *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ *  must be provided and is the default IDLE thread body instead of
+ *  @ref _CPU_Thread_Idle_body.
+ *
+ *  If FALSE, then use the generic IDLE thread body if the BSP does
+ *  not provide one.
+ *
+ *  This is intended to allow for supporting processors which have
+ *  a low power or idle mode.  When the IDLE thread is executed, then
+ *  the CPU can be powered down.
+ *
+ *  The order of precedence for selecting the IDLE thread body is:
+ *
+ *    -#  BSP provided
+ *    -#  CPU dependent (if provided)
+ *    -#  generic (if no BSP and no CPU dependent)
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
+
+/**
+ *  Does the stack grow up (toward higher addresses) or down
+ *  (toward lower addresses)?
+ *
+ *  If TRUE, then the grows upward.
+ *  If FALSE, then the grows toward smaller addresses.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_STACK_GROWS_UP               FALSE
+
+/**
+ *  The following is the variable attribute used to force alignment
+ *  of critical RTEMS structures.  On some processors it may make
+ *  sense to have these aligned on tighter boundaries than
+ *  the minimum requirements of the compiler in order to have as
+ *  much of the critical data area as possible in a cache line.
+ *
+ *  The placement of this macro in the declaration of the variables
+ *  is based on the syntactically requirements of the GNU C
+ *  "__attribute__" extension.  For example with GNU C, use
+ *  the following to force a structures to a 32 byte boundary.
+ *
+ *      __attribute__ ((aligned (32)))
+ *
+ *  @note Currently only the Priority Bit Map table uses this feature.
+ *        To benefit from using this, the data must be heavily
+ *        used so it will stay in the cache and used frequently enough
+ *        in the executive to justify turning this on.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_STRUCTURE_ALIGNMENT 
+
+/**
+ *  @defgroup CPUEndian Processor Dependent Endianness Support
+ *
+ *  This group assists in issues related to processor endianness.
+ */
+
+/**
+ *  @ingroup CPUEndian
+ *  Define what is required to specify how the network to host conversion
+ *  routines are handled.
+ *
+ *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ *  same values.
+ *
+ *  @see CPU_LITTLE_ENDIAN
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_BIG_ENDIAN                           FALSE
+
+/**
+ *  @ingroup CPUEndian
+ *  Define what is required to specify how the network to host conversion
+ *  routines are handled.
+ *
+ *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ *  same values.
+ *
+ *  @see CPU_BIG_ENDIAN
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_LITTLE_ENDIAN                        TRUE
+
+/**
+ *  @ingroup CPUInterrupt
+ *  The following defines the number of bits actually used in the
+ *  interrupt field of the task mode.  How those bits map to the
+ *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_MODES_INTERRUPT_MASK   0x00000002
+
+/*
+ *  Processor defined structures required for cpukit/score.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/* may need to put some structures here.  */
+
+/**
+ * @defgroup CPUContext Processor Dependent Context Management
+ *
+ *  From the highest level viewpoint, there are 2 types of context to save.
+ *
+ *     -# Interrupt registers to save
+ *     -# Task level registers to save
+ *
+ *  Since RTEMS handles integer and floating point contexts separately, this
+ *  means we have the following 3 context items:
+ *
+ *     -# task level context stuff::  Context_Control
+ *     -# floating point task stuff:: Context_Control_fp
+ *     -# special interrupt level context :: CPU_Interrupt_frame
+ *
+ *  On some processors, it is cost-effective to save only the callee
+ *  preserved registers during a task context switch.  This means
+ *  that the ISR code needs to save those registers which do not
+ *  persist across function calls.  It is not mandatory to make this
+ *  distinctions between the caller/callee saves registers for the
+ *  purpose of minimizing context saved during task switch and on interrupts.
+ *  If the cost of saving extra registers is minimal, simplicity is the
+ *  choice.  Save the same context on interrupt entry as for tasks in
+ *  this case.
+ *
+ *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ *  care should be used in designing the context area.
+ *
+ *  On some CPUs with hardware floating point support, the Context_Control_fp
+ *  structure will not be used or it simply consist of an array of a
+ *  fixed number of bytes.   This is done when the floating point context
+ *  is dumped by a "FP save context" type instruction and the format
+ *  is not really defined by the CPU.  In this case, there is no need
+ *  to figure out the exact format -- only the size.  Of course, although
+ *  this is enough information for RTEMS, it is probably not enough for
+ *  a debugger such as gdb.  But that is another problem.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/**
+ *  @ingroup CPUContext Management
+ *  This defines the minimal set of integer and processor state registers
+ *  that must be saved during a voluntary context switch from one thread
+ *  to another.
+ */
+typedef struct {
+    /* we are saving all registers, maybe we should not */
+    
+    uint32_t   register_r0;
+    uint32_t   register_r1;
+    uint32_t   register_r2;
+    uint32_t   register_r3;
+    uint32_t   register_r4;
+    uint32_t   register_r5;
+    uint32_t   register_r6;
+    uint32_t   register_r7;
+    uint32_t   register_p0;
+    uint32_t   register_p1;
+    uint32_t   register_p2;
+    uint32_t   register_p3;
+    uint32_t   register_p4;
+    uint32_t   register_p5;                         
+    uint32_t   register_fp;
+    uint32_t   register_sp;
+    
+    uint32_t   register_i0;                         
+    uint32_t   register_i1;
+    uint32_t   register_i2;
+    uint32_t   register_i3;
+    
+    uint32_t   register_m0;
+    uint32_t   register_m1;
+    uint32_t   register_m2;
+    uint32_t   register_m3;
+
+    uint32_t   register_b0;
+    uint32_t   register_b1;
+    uint32_t   register_b2;
+    uint32_t   register_b3;
+
+    uint32_t   register_l0;
+    uint32_t   register_l1;
+    uint32_t   register_l2;
+    uint32_t   register_l3;    
+    
+    uint32_t   register_a0dotx;
+    uint32_t   register_a0dotw;
+    uint32_t   register_a1dotx;
+    uint32_t   register_a1dotw;
+    uint32_t   register_astat;
+    uint32_t   register_rets;
+    uint32_t   register_lc0;
+    uint32_t   register_lt0;
+    uint32_t   register_lb0;
+    uint32_t   register_lc1;
+    uint32_t   register_lt1;
+    uint32_t   register_lb1;
+  
+  /*BFIN_CYCLES_REGNUM,
+  BFIN_CYCLES2_REGNUM, */
+  
+    uint32_t   register_usp;
+    uint32_t   register_seqstat;
+    uint32_t   register_syscfg;
+    uint32_t   register_reti;
+    uint32_t   register_retx;
+    uint32_t   register_retn;
+    uint32_t   register_rete;
+
+    uint32_t   register_pc;
+
+  /*
+  Pseudo Registers
+  BFIN_PC_REGNUM,
+  BFIN_CC_REGNUM,
+  BFIN_EXTRA1,       Address of .text section. 
+  BFIN_EXTRA2,       Address of .data section. 
+  BFIN_EXTRA3,       Address of .bss section.  
+
+  BFIN_FDPIC_EXEC_REGNUM,
+  BFIN_FDPIC_INTERP_REGNUM,
+
+  MMRs
+  BFIN_IPEND_REGNUM,
+
+  LAST ENTRY SHOULD NOT BE CHANGED. 
+  BFIN_NUM_REGS      The number of all registers. 
+  */  
+} Context_Control;
+
+/**
+ *  @ingroup CPUContext Management
+ *  This defines the complete set of floating point registers that must
+ *  be saved during any context switch from one thread to another.
+ */
+typedef struct {
+    /* FPU registers are listed here */
+    /* Blackfin has no Floating Point */
+} Context_Control_fp;
+
+/**
+ *  @ingroup CPUContext Management
+ *  This defines the set of integer and processor state registers that must
+ *  be saved during an interrupt.  This set does not include any which are
+ *  in @ref Context_Control.
+ */
+typedef struct {
+    /** This field is a hint that a port will have a number of integer 
+     *  registers that need to be saved when an interrupt occurs or
+     *  when a context switch occurs at the end of an ISR.
+     */
+    /*uint32_t   special_interrupt_register;*/
+} CPU_Interrupt_frame;
+
+
+/**
+ *  The following table contains the information required to configure
+ *  the XXX processor specific parameters.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+typedef struct {
+  /** This element points to the BSP's pretasking hook. */
+  void       (*pretasking_hook)( void );
+  /** This element points to the BSP's predriver hook. */
+  void       (*predriver_hook)( void );
+  /** This element points to the BSP's postdriver hook. */
+  void       (*postdriver_hook)( void );
+  /** This element points to the BSP's optional idle task which may override
+   *  the default one provided with RTEMS.
+   */
+  void       (*idle_task)( void );
+  /** If this element is TRUE, then RTEMS will zero the Executive Workspace.
+   *  When this element is FALSE, it is assumed that the BSP or invoking
+   *  environment has ensured that memory was cleared before RTEMS was 
+   *  invoked.
+   */
+  boolean      do_zero_of_workspace;
+  /** This field specifies the size of the IDLE task's stack.  If less than or
+   *  equal to the minimum stack size, then the IDLE task will have the minimum
+   *  stack size.
+   */
+  uint32_t     idle_task_stack_size;
+  /** This field specifies the size of the interrupt stack.  If less than or
+   *  equal to the minimum stack size, then the interrupt stack will be of
+   *  minimum stack size.
+   */
+  uint32_t     interrupt_stack_size;
+  /** The MPCI Receive server is assumed to have a stack of at least 
+   *  minimum stack size.  This field specifies the amount of extra
+   *  stack this task will be given in bytes.
+   */
+  uint32_t     extra_mpci_receive_server_stack;
+  /** The BSP may want to provide it's own stack allocation routines.
+   *  In this case, the BSP will provide this stack allocation hook.
+   */
+  void *     (*stack_allocate_hook)( uint32_t   );
+  /** The BSP may want to provide it's own stack free routines.
+   *  In this case, the BSP will provide this stack free hook.
+   */
+  void       (*stack_free_hook)( void *);
+  /* end of fields required on all CPUs */
+}   rtems_cpu_table;
+
+/*
+ *  Macros to access required entires in the CPU Table are in 
+ *  the file rtems/system.h.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/*
+ *  Macros to access Blackfin specific additions to the CPU Table
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/* There are no CPU specific additions to the CPU Table for this port. */
+
+/**
+ *  This variable is optional.  It is used on CPUs on which it is difficult
+ *  to generate an "uninitialized" FP context.  It is filled in by
+ *  @ref _CPU_Initialize and copied into the task's FP context area during
+ *  @ref _CPU_Context_Initialize.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
+
+/**
+ *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ *
+ *  On some CPUs, RTEMS supports a software managed interrupt stack.
+ *  This stack is allocated by the Interrupt Manager and the switch
+ *  is performed in @ref _ISR_Handler.  These variables contain pointers
+ *  to the lowest and highest addresses in the chunk of memory allocated
+ *  for the interrupt stack.  Since it is unknown whether the stack
+ *  grows up or down (in general), this give the CPU dependent
+ *  code the option of picking the version it wants to use.
+ *
+ *  @note These two variables are required if the macro
+ *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This variable points to the lowest physical address of the interrupt 
+ *  stack.
+ */
+SCORE_EXTERN void               *_CPU_Interrupt_stack_low;
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This variable points to the lowest physical address of the interrupt 
+ *  stack.
+ */
+SCORE_EXTERN void               *_CPU_Interrupt_stack_high;
+
+/**
+ *  @ingroup CPUInterrupt
+ *  With some compilation systems, it is difficult if not impossible to
+ *  call a high-level language routine from assembly language.  This
+ *  is especially true of commercial Ada compilers and name mangling
+ *  C++ ones.  This variable can be optionally defined by the CPU porter
+ *  and contains the address of the routine @ref _Thread_Dispatch.  This
+ *  can make it easier to invoke that routine at the end of the interrupt
+ *  sequence (if a dispatch is necessary).
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+SCORE_EXTERN void           (*_CPU_Thread_dispatch_pointer)();
+
+/*
+ *  Nothing prevents the porter from declaring more CPU specific variables.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+/* XXX: if needed, put more variables here */
+
+/**
+ *  @ingroup CPUContext
+ *  The size of the floating point context area.  On some CPUs this
+ *  will not be a "sizeof" because the format of the floating point
+ *  area is not defined -- only the size is.  This is usually on
+ *  CPUs with a "floating point save context" instruction.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
+
+/**
+ *  Amount of extra stack (above minimum stack size) required by
+ *  MPCI receive server thread.  Remember that in a multiprocessor
+ *  system this thread must exist and be able to process all directives.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This defines the number of entries in the @ref _ISR_Vector_table managed
+ *  by RTEMS.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_INTERRUPT_NUMBER_OF_VECTORS      16
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This defines the highest interrupt vector number for this port.
+ */
+#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This is defined if the port has a special way to report the ISR nesting
+ *  level.  Most ports maintain the variable @a _ISR_Nest_level.
+ */
+#define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
+
+/**
+ *  @ingroup CPUContext
+ *  Should be large enough to run all RTEMS tests.  This ensures
+ *  that a "reasonable" small application should not have any problems.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_STACK_MINIMUM_SIZE          (1024*4)
+
+/**
+ *  CPU's worst alignment requirement for data types on a byte boundary.  This
+ *  alignment does not take into account the requirements for the stack.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_ALIGNMENT              8
+
+/**
+ *  This number corresponds to the byte alignment requirement for the
+ *  heap handler.  This alignment requirement may be stricter than that
+ *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
+ *  common for the heap to follow the same alignment requirement as
+ *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
+ *  the heap, then this should be set to @ref CPU_ALIGNMENT.
+ *
+ *  @note  This does not have to be a power of 2 although it should be
+ *         a multiple of 2 greater than or equal to 2.  The requirement
+ *         to be a multiple of 2 is because the heap uses the least 
+ *         significant field of the front and back flags to indicate
+ *         that a block is in use or free.  So you do not want any odd
+ *         length blocks really putting length data in that bit.
+ *
+ *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ *         elements allocated from the heap meet all restrictions.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
+
+/**
+ *  This number corresponds to the byte alignment requirement for memory
+ *  buffers allocated by the partition manager.  This alignment requirement
+ *  may be stricter than that for the data types alignment specified by
+ *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
+ *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
+ *  strict enough for the partition, then this should be set to
+ *  @ref CPU_ALIGNMENT.
+ *
+ *  @note  This does not have to be a power of 2.  It does have to
+ *         be greater or equal to than @ref CPU_ALIGNMENT.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
+
+/**
+ *  This number corresponds to the byte alignment requirement for the
+ *  stack.  This alignment requirement may be stricter than that for the
+ *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
+ *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ *  set to 0.
+ *
+ *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define CPU_STACK_ALIGNMENT        0
+
+/*
+ *  ISR handler macros
+ */
+
+/**
+ *  @ingroup CPUInterrupt
+ *  Support routine to initialize the RTEMS vector table after it is allocated.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Initialize_vectors()
+
+/**
+ *  @ingroup CPUInterrupt
+ *  Disable all interrupts for an RTEMS critical section.  The previous
+ *  level is returned in @a _isr_cookie.
+ *
+ *  @param[out] _isr_cookie will contain the previous level cookie
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_ISR_Disable( _level ) \
+  {                                     \
+    asm volatile ("cli %0 \n"           \
+                   : "=r" (_level) );   \
+                                        \
+  }
+  
+
+/**
+ *  @ingroup CPUInterrupt
+ *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ *  This indicates the end of an RTEMS critical section.  The parameter
+ *  @a _isr_cookie is not modified.
+ *
+ *  @param[in] _isr_cookie contain the previous level cookie
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_ISR_Enable( _level )  \
+  {                                   \
+    asm volatile ("STI %0"            \
+                   : : "r" (_level) );  \
+  }
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This temporarily restores the interrupt to @a _isr_cookie before immediately
+ *  disabling them again.  This is used to divide long RTEMS critical
+ *  sections into two or more parts.  The parameter @a _isr_cookie is not
+ *  modified.
+ *
+ *  @param[in] _isr_cookie contain the previous level cookie
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_ISR_Flash( _level ) 
+/*  { \
+    asm volatile ("cli %0;\n"          \
+                  "ssync; \n"           \
+                  "sti %1; \n"          \
+                   : "=r" (_level) : "0"(_level) );  \
+  }*/
+
+/**
+ *  @ingroup CPUInterrupt
+ *
+ *  This routine and @ref _CPU_ISR_Get_level
+ *  Map the interrupt level in task mode onto the hardware that the CPU
+ *  actually provides.  Currently, interrupt levels which do not
+ *  map onto the CPU in a generic fashion are undefined.  Someday,
+ *  it would be nice if these were "mapped" by the application
+ *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ *  8 - 255 would be available for bsp/application specific meaning.
+ *  This could be used to manage a programmable interrupt controller
+ *  via the rtems_task_mode directive.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_ISR_Set_level( _new_level ) \
+  { \
+    if ( _new_level ) asm volatile ( "cli R0;" : : : "R0" ); \
+    else              asm volatile ( "R0.l = 0xFFFF;\n"\
+                                     "sti R0;" : : : "R0" ); \  
+  }
+
+
+/**
+ *  @ingroup CPUInterrupt
+ *  Return the current interrupt disable level for this task in
+ *  the format used by the interrupt level portion of the task mode.
+ *
+ *  @note This routine usually must be implemented as a subroutine.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+uint32_t   _CPU_ISR_Get_level( void );
+
+/* end of ISR handler macros */
+
+/* Context handler macros */
+
+/**
+ *  @ingroup CPUContext
+ *  Initialize the context to a state suitable for starting a
+ *  task after a context restore operation.  Generally, this
+ *  involves:
+ *
+ *     - setting a starting address
+ *     - preparing the stack
+ *     - preparing the stack and frame pointers
+ *     - setting the proper interrupt level in the context
+ *     - initializing the floating point context
+ *
+ *  This routine generally does not set any unnecessary register
+ *  in the context.  The state of the "general data" registers is
+ *  undefined at task start time.
+ *
+ *  @param[in] _the_context is the context structure to be initialized
+ *  @param[in] _stack_base is the lowest physical address of this task's stack
+ *  @param[in] _size is the size of this task's stack
+ *  @param[in] _isr is the interrupt disable level
+ *  @param[in] _entry_point is the thread's entry point.  This is
+ *         always @a _Thread_Handler
+ *  @param[in] _is_fp is TRUE if the thread is to be a floating
+ *        point thread.  This is typically only used on CPUs where the
+ *        FPU may be easily disabled by software such as on the SPARC
+ *        where the PSR contains an enable FPU bit.
+ *
+ *  Port Specific Information:
+ *
+ *  See implementation in cpu.c
+ */
+void _CPU_Context_Initialize(
+  Context_Control  *the_context,
+  uint32_t         *stack_base,
+  uint32_t          size,
+  uint32_t          new_level,
+  void             *entry_point,
+  boolean           is_fp
+);
+
+/**
+ *  This routine is responsible for somehow restarting the currently
+ *  executing task.  If you are lucky, then all that is necessary
+ *  is restoring the context.  Otherwise, there will need to be
+ *  a special assembly routine which does something special in this
+ *  case.  For many ports, simply adding a label to the restore path
+ *  of @ref _CPU_Context_switch will work.  On other ports, it may be
+ *  possibly to load a few arguments and jump to the restore path. It will
+ *  not work if restarting self conflicts with the stack frame
+ *  assumptions of restoring a context.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Context_Restart_self( _the_context ) \
+   _CPU_Context_restore( (_the_context) );
+
+/**
+ *  @ingroup CPUContext
+ *  The purpose of this macro is to allow the initial pointer into
+ *  a floating point context area (used to save the floating point
+ *  context) to be at an arbitrary place in the floating point
+ *  context area.
+ *
+ *  This is necessary because some FP units are designed to have
+ *  their context saved as a stack which grows into lower addresses.
+ *  Other FP units can be saved by simply moving registers into offsets
+ *  from the base of the context area.  Finally some FP units provide
+ *  a "dump context" instruction which could fill in from high to low
+ *  or low to high based on the whim of the CPU designers.
+ *
+ *  @param[in] _base is the lowest physical address of the floating point
+ *         context area
+ *  @param[in] _offset is the offset into the floating point area
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Context_Fp_start( _base, _offset ) \
+   ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
+
+/**
+ *  This routine initializes the FP context area passed to it to.
+ *  There are a few standard ways in which to initialize the
+ *  floating point context.  The code included for this macro assumes
+ *  that this is a CPU in which a "initial" FP context was saved into
+ *  @a _CPU_Null_fp_context and it simply copies it to the destination
+ *  context passed to it.
+ *
+ *  Other floating point context save/restore models include:
+ *    -# not doing anything, and
+ *    -# putting a "null FP status word" in the correct place in the FP context.
+ *
+ *  @param[in] _destination is the floating point context area
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Context_Initialize_fp( _destination ) \
+  { \
+   *((Context_Control_fp *) *((void **) _destination)) = _CPU_Null_fp_context; \
+  }
+
+/* end of Context handler macros */
+
+/* Fatal Error manager macros */
+
+/**
+ *  This routine copies _error into a known place -- typically a stack
+ *  location or a register, optionally disables interrupts, and
+ *  halts/stops the CPU.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#define _CPU_Fatal_halt( _error ) \
+  { \
+    asm volatile ( "cli R1; \
+                    R1 = %0; \
+                    _halt: \
+                    jump _halt;"\
+                    : "=r" (_error) ); \
+  }
+
+/* end of Fatal Error manager macros */
+
+/* Bitfield handler macros */
+
+/**
+ *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ *
+ *  This set of routines are used to implement fast searches for 
+ *  the most important ready task.
+ */
+
+/**
+ *  @ingroup CPUBitfield
+ *  This definition is set to TRUE if the port uses the generic bitfield
+ *  manipulation implementation.
+ */
+#define CPU_USE_GENERIC_BITFIELD_CODE TRUE
+
+/**
+ *  @ingroup CPUBitfield
+ *  This definition is set to TRUE if the port uses the data tables provided
+ *  by the generic bitfield manipulation implementation.
+ *  This can occur when actually using the generic bitfield manipulation
+ *  implementation or when implementing the same algorithm in assembly
+ *  language for improved performance.  It is unlikely that a port will use
+ *  the data if it has a bitfield scan instruction.
+ */
+#define CPU_USE_GENERIC_BITFIELD_DATA TRUE
+
+/**
+ *  @ingroup CPUBitfield
+ *  This routine sets @a _output to the bit number of the first bit
+ *  set in @a _value.  @a _value is of CPU dependent type 
+ *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
+ *  wide although only the 16 least significant bits will be used.
+ *
+ *  There are a number of variables in using a "find first bit" type
+ *  instruction.
+ *
+ *    -# What happens when run on a value of zero?
+ *    -# Bits may be numbered from MSB to LSB or vice-versa.
+ *    -# The numbering may be zero or one based.
+ *    -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ *  RTEMS guarantees that (1) will never happen so it is not a concern.
+ *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ *  @ref _CPU_Priority_bits_index.  These three form a set of routines
+ *  which must logically operate together.  Bits in the _value are
+ *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ *  The basic major and minor values calculated by @ref _Priority_Major
+ *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ *  to properly range between the values returned by the "find first bit"
+ *  instruction.  This makes it possible for @ref _Priority_Get_highest to
+ *  calculate the major and directly index into the minor table.
+ *  This mapping is necessary to ensure that 0 (a high priority major/minor)
+ *  is the first bit found.
+ *
+ *  This entire "find first bit" and mapping process depends heavily
+ *  on the manner in which a priority is broken into a major and minor
+ *  components with the major being the 4 MSB of a priority and minor
+ *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ *  to the lowest priority.
+ *
+ *  If your CPU does not have a "find first bit" instruction, then
+ *  there are ways to make do without it.  Here are a handful of ways
+ *  to implement this in software:
+ *
+@verbatim
+      - a series of 16 bit test instructions
+      - a "binary search using if's"
+      - _number = 0
+        if _value > 0x00ff
+          _value >>=8
+          _number = 8;
+  
+        if _value > 0x0000f
+          _value >=8
+          _number += 4
+  
+        _number += bit_set_table[ _value ]
+@endverbatim
+  
+ *    where bit_set_table[ 16 ] has values which indicate the first
+ *      bit set
+ *
+ *  @param[in] _value is the value to be scanned
+ *  @param[in] _output is the first bit set
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+#define _CPU_Bitfield_Find_first_bit( _value, _output ) \
+  { \
+    asm ("bit(1);"):
+    (_output) = 0;   /* do something to prevent warnings */ \
+  }
+#endif
+
+/* end of Bitfield handler macros */
+
+/**
+ *  This routine builds the mask which corresponds to the bit fields
+ *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
+ *  for that routine.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_Mask( _bit_number ) \
+  ( 1 << (_bit_number) )
+
+#endif
+
+/**
+ *  @ingroup CPUBitfield
+ *  This routine translates the bit numbers returned by
+ *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ *  a major or minor component of a priority.  See the discussion
+ *  for that routine.
+ *
+ *  @param[in] _priority is the major or minor number to translate
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
+
+#define _CPU_Priority_bits_index( _priority ) \
+  (_priority)
+
+#endif
+
+/* end of Priority handler macros */
+
+/* functions */
+
+/**
+ *  This routine performs CPU dependent initialization.
+ *
+ *  @param[in] cpu_table is the CPU Dependent Configuration Table
+ *  @param[in] thread_dispatch is the address of @ref _Thread_Dispatch
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Initialize(
+  rtems_cpu_table  *cpu_table,
+  void      (*thread_dispatch)
+);
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This routine installs a "raw" interrupt handler directly into the 
+ *  processor's vector table.
+ *
+ *  @param[in] vector is the vector number
+ *  @param[in] new_handler is the raw ISR handler to install
+ *  @param[in] old_handler is the previously installed ISR Handler
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_ISR_install_raw_handler(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This routine installs an interrupt vector.
+ *
+ *  @param[in] vector is the vector number
+ *  @param[in] new_handler is the RTEMS ISR handler to install
+ *  @param[in] old_handler is the previously installed ISR Handler
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_ISR_install_vector(
+  uint32_t    vector,
+  proc_ptr    new_handler,
+  proc_ptr   *old_handler
+);
+
+/**
+ *  @ingroup CPUInterrupt
+ *  This routine installs the hardware interrupt stack pointer.
+ *
+ *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *         is TRUE.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Install_interrupt_stack( void );
+
+/**
+ *  This routine is the CPU dependent IDLE thread body.
+ *
+ *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
+ *         is TRUE.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Thread_Idle_body( void );
+
+/**
+ *  @ingroup CPUContext
+ *  This routine switches from the run context to the heir context.
+ *
+ *  @param[in] run points to the context of the currently executing task
+ *  @param[in] heir points to the context of the heir task
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Context_switch(
+  Context_Control  *run,
+  Context_Control  *heir
+);
+
+/**
+ *  @ingroup CPUContext
+ *  This routine is generally used only to restart self in an
+ *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
+ *
+ *  @param[in] new_context points to the context to be restored.
+ *
+ *  @note May be unnecessary to reload some registers.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Context_restore(
+  Context_Control *new_context
+);
+
+/**
+ *  @ingroup CPUContext
+ *  This routine saves the floating point context passed to it.
+ *
+ *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ *  point context area
+ *
+ *  @return on output @a *fp_context_ptr will contain the address that
+ *  should be used with @ref _CPU_Context_restore_fp to restore this context.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Context_save_fp(
+  void **fp_context_ptr
+);
+
+/**
+ *  @ingroup CPUContext
+ *  This routine restores the floating point context passed to it.
+ *
+ *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ *  point context area to restore
+ *
+ *  @return on output @a *fp_context_ptr will contain the address that
+ *  should be used with @ref _CPU_Context_save_fp to save this context.
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+void _CPU_Context_restore_fp(
+  void **fp_context_ptr
+);
+
+/**
+ *  @ingroup CPUEndian
+ *  The following routine swaps the endian format of an unsigned int.
+ *  It must be static because it is referenced indirectly.
+ *
+ *  This version will work on any processor, but if there is a better
+ *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ *
+ *     swap least significant two bytes with 16-bit rotate
+ *     swap upper and lower 16-bits
+ *     swap most significant two bytes with 16-bit rotate
+ *
+ *  Some CPUs have special instructions which swap a 32-bit quantity in
+ *  a single instruction (e.g. i486).  It is probably best to avoid
+ *  an "endian swapping control bit" in the CPU.  One good reason is
+ *  that interrupts would probably have to be disabled to ensure that
+ *  an interrupt does not try to access the same "chunk" with the wrong
+ *  endian.  Another good reason is that on some CPUs, the endian bit
+ *  endianness for ALL fetches -- both code and data -- so the code
+ *  will be fetched incorrectly.
+ *
+ *  @param[in] value is the value to be swapped
+ *  @return the value after being endian swapped
+ *
+ *  Port Specific Information:
+ *
+ *  XXX document implementation including references if appropriate
+ */
+static inline uint32_t CPU_swap_u32(
+  uint32_t value
+)
+{
+  uint32_t   byte1, byte2, byte3, byte4, swapped;
+ 
+  byte4 = (value >> 24) & 0xff;
+  byte3 = (value >> 16) & 0xff;
+  byte2 = (value >> 8)  & 0xff;
+  byte1 =  value        & 0xff;
+ 
+  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
+  return( swapped );
+}
+
+/**
+ *  @ingroup CPUEndian
+ *  This routine swaps a 16 bir quantity.
+ *
+ *  @param[in] value is the value to be swapped
+ *  @return the value after being endian swapped
+ */
+#define CPU_swap_u16( value ) \
+  (((value&0xff) << 8) | ((value >> 8)&0xff))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Index: cpukit/score/cpu/bfin/rtems/score/cpu_asm.h
===================================================================
--- cpukit/score/cpu/bfin/rtems/score/cpu_asm.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/rtems/score/cpu_asm.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,90 @@
+/**
+ * @file rtems/score/cpu_asm.h
+ */
+
+/*
+ *  Defines a couple of Macros used in cpu_asm.S
+ * 
+ *  Copyright (c) 2006 by Atos Automacao Industrial Ltda.
+ *             written by Alain Schaefer <alain.schaefer@easc.ch>
+ *                    and Antonio Giovanini <antonio@atos.com.br>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ *
+ */
+
+#ifndef _RTEMS_SCORE_CPU_ASM_H
+#define _RTEMS_SCORE_CPU_ASM_H
+
+/* offsets for the registers in the thread context */
+#define R0_OFFSET     0
+#define R1_OFFSET     4
+#define R2_OFFSET     8
+#define R3_OFFSET     12
+#define R4_OFFSET     16
+#define R5_OFFSET     20
+#define R6_OFFSET     24
+#define R7_OFFSET     28
+#define P0_OFFSET     32
+#define P1_OFFSET     36
+#define P2_OFFSET     40
+#define P3_OFFSET     44
+#define P4_OFFSET     48
+#define P5_OFFSET     52
+#define FP_OFFSET     56
+#define SP_OFFSET     60
+
+#define I0_OFFSET     64
+#define I1_OFFSET     68
+#define I2_OFFSET     72
+#define I3_OFFSET     76
+
+#define M0_OFFSET     80
+#define M1_OFFSET     84
+#define M2_OFFSET     88
+#define M3_OFFSET     92
+
+#define B0_OFFSET     96
+#define B1_OFFSET     100
+#define B2_OFFSET     104
+#define B3_OFFSET     108
+
+#define L0_OFFSET     112
+#define L1_OFFSET     116
+#define L2_OFFSET     120
+#define L3_OFFSET     124
+
+#define A0X_OFFSET     128
+#define A0W_OFFSET     132
+#define A1X_OFFSET     136
+#define A1W_OFFSET     140
+
+#define ASTAT_OFFSET   144
+#define RETS_OFFSET    148
+#define LC0_OFFSET     152
+#define LT0_OFFSET     156
+
+#define LB0_OFFSET     160
+#define LC1_OFFSET     164
+#define LT1_OFFSET     168
+#define LB1_OFFSET     172
+
+#define USP_OFFSET     174
+#define SEQSTAT_OFFSET 178
+#define SYSCFG_OFFSET  182
+#define RETI_OFFSET    184
+
+#define RETX_OFFSET    188
+#define RETN_OFFSET    192
+#define RETE_OFFSET    296
+
+#define PC_OFFSET      200
+
+
+#endif
+
+/* end of file */
Index: cpukit/score/cpu/bfin/rtems/score/types.h
===================================================================
--- cpukit/score/cpu/bfin/rtems/score/types.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
+++ cpukit/score/cpu/bfin/rtems/score/types.h	(revision d9a6ab3fed9e77a6343ee56571e4d9d767c8e979)
@@ -0,0 +1,59 @@
+/*
+ *  This include file contains type definitions pertaining to the
+ *  Blackfin processor family.
+ *
+ *  COPYRIGHT (c) 1989-2006.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.com/license/LICENSE.
+ *
+ *  $Id$
+ */
+
+#ifndef _RTEMS_SCORE_TYPES_H
+#define _RTEMS_SCORE_TYPES_H
+
+#ifndef ASM
+
+#include <rtems/stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ *  This section defines the basic types for this processor.
+ */
+
+/** This defines an unsigned 64-bit integer. */
+typedef unsigned long long unsigned64;
+
+/** This defines the type for a priority bit map entry. */
+typedef uint16_t Priority_Bit_map_control;
+
+/** This defines the type for a 64 bit signed integer */
+typedef signed long long signed64;
+
+/** This defines the type for a Boolean value, */
+typedef uint32_t boolean;     /* Boolean value   */
+
+/** This defines the type for a single precision float. */
+typedef float          single_precision;
+/** This defines the type for a double precision float. */
+typedef double         double_precision;
+
+/** This defines the return type for an ISR entry point. */
+typedef void blackfin_isr;
+
+/** This defines the prototype for an ISR entry point. */
+typedef blackfin_isr ( *blackfin_isr_entry )( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* !ASM */
+
+#endif
