Changeset d98eea0 in rtems


Ignore:
Timestamp:
Apr 17, 2014, 9:27:23 AM (6 years ago)
Author:
Ralf Kirchner <ralf.kirchner@…>
Branches:
4.11, master
Children:
fab2f188
Parents:
127634c
git-author:
Ralf Kirchner <ralf.kirchner@…> (04/17/14 09:27:23)
git-committer:
Sebastian Huber <sebastian.huber@…> (04/17/14 11:25:12)
Message:

bsp/arm: Cleanup L2 cache handling

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    r127634c rd98eea0  
    473473* - Revision r3p3
    474474* - Software Developer Errata Notice
    475 * - ARM CoreLink Level 2 Cache Controller (L2C-310 or PL310), 
     475* - ARM CoreLink Level 2 Cache Controller (L2C-310 or PL310),
    476476*   r3 releases Software Developers Errata Notice"
    477 * The corresponding link is: 
     477* The corresponding link is:
    478478* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html
    479479* Please see this document for more information on these erratas */
     
    482482)
    483483{
    484   volatile L2CC                  *l2cc          = 
     484  volatile L2CC                  *l2cc          =
    485485    (volatile L2CC *) BSP_ARM_L2CC_BASE;
    486   const cache_l2c_310_rtl_release RTL_RELEASE   = 
     486  const cache_l2c_310_rtl_release RTL_RELEASE   =
    487487    l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
    488488  bool                            is_applicable = false;
     
    508508              || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
    509509              || RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
    510      break;
    511   }
    512  
     510      break;
     511  }
     512
    513513  return is_applicable;
    514514}
    515 
    516 
    517515
    518516static bool l2c_310_cache_errata_is_applicable_727913(
     
    974972  assert( ! l2c_310_cache_errata_is_applicable_752271() );
    975973
    976   /* This erratum gets handled with a workaround: 753970 The Cache Sync
    977    * operation prevents further bufferable writes from merging in the store.
    978      Search for 753970 in cache_.h for detailed information */
    979 
    980   /* Conditions
    981      This problem occurs when the following conditions are met:
    982      1. PL310 receives a Cache Sync operation.
    983      Workaround
    984      The proposed workaround to avoid this erratum is to replace the normal
    985      offset of Cache Sync operation (0x730) by another offset targeting an
    986      unmapped PL310 register: 0x740.
    987      More specifically, find below a pseudo code sequence illustrating the
    988      workaround:
    989      Replace
    990      // PL310 Cache Sync operation
    991      LDR r1,=PL310_BASE
    992      STR r2,[r1,#0x730]
    993      by
    994      // Workaround for PL310 Cache Sync operation
    995      LDR r1,=PL310_BASE
    996      STR r2,[r1,#0x740] ; write to an unmapped register
    997      This write has the same effect as the Cache Sync operation: store buffer
    998      drained and waiting for all buffers empty.*/
    999   /* assert( ! l2c_310_cache_errata_is_applicable_753970() ); */
    1000 
    1001974  /* This erratum can not be worked around: 754670 A continuous write flow can
    1002975   * stall a read targeting the same memory area
     
    11131086    l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;
    11141087
    1115     while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {
    1116     }
    1117 
    1118     ;
     1088    while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {};
    11191089
    11201090    /* Wait for the flush to complete */
     
    11321102
    11331103  l2cc->inv_pa = (uint32_t) d_addr;
    1134 
    11351104  cache_l2c_310_sync();
    11361105}
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