Changeset d8beaab in rtems-docs


Ignore:
Timestamp:
Nov 15, 2016, 11:54:47 PM (4 years ago)
Author:
Joel Sherrill <joel@…>
Branches:
5, am, master
Children:
7193f09
Parents:
2591ca6
git-author:
Joel Sherrill <joel@…> (11/15/16 23:54:47)
git-committer:
Joel Sherrill <joel@…> (01/12/17 00:22:10)
Message:

Remove references to SPARC/SIS BSP. Also clean up old ERC32 references.

updates #2810.

Files:
3 edited

Legend:

Unmodified
Added
Removed

  • cpu-supplement/sparc.rst

    r2591ca6 rd8beaab  
    3636**ERC32 Specific Information**
    3737
    38 The European Space Agency's ERC32 is a three chip computing core implementing a
     38The European Space Agency's ERC32 is a microprocessor implementing a
    3939SPARC V7 processor and associated support circuitry for embedded space
    4040applications. The integer and floating-point units (90C601E & 90C602E) are
    … …  
    4747performance of 10 MIPS and 2 MFLOPS.
    4848
    49 Information on the ERC32 and a number of development support tools, such as the
    50 SPARC Instruction Simulator (SIS), are freely available on the Internet.  The
    51 following documents and SIS are available via anonymous ftp or pointing your
    52 web browser at ftp://ftp.estec.esa.nl/pub/ws/wsd/erc32.
    53 
    54 - ERC32 System Design Document
    55 
    56 - MEC Device Specification
    57 
    58 Additionally, the SPARC RISC User's Guide from Matra MHS documents the
    59 functionality of the integer and floating point units including the instruction
    60 set information.  To obtain this document as well as ERC32 components and VHDL
    61 models contact:
    62 
    63     Matra MHS SA
    64     3 Avenue du Centre, BP 309,
    65     78054 St-Quentin-en-Yvelines,
    66     Cedex, France
    67     VOICE: +31-1-30607087
    68     FAX: +31-1-30640693
    69 
    70 Amar Guennon (amar.guennon@matramhs.fr) is familiar with the ERC32.
     49The ERC32 is available from Atmel as the TSC695F.
     50
     51The RTEMS configuration of GDB enables the SPARC Instruction Simulator (SIS)
     52which can simulate the ERC32 as well as the follow up LEON2 and LEON3
     53microprocessors.
    7154
    7255CPU Model Dependent Features

  • rsb/third-party-packages.rst

    r2591ca6 rd8beaab  
    4747        --prefix=$HOME/development/rtems/bsps/4.11 \
    4848        --with-tools=$HOME/development/rtems/4.11 \
    49         --host=sparc-rtems4.11 --with-rtems-bsp=sis 4.11/net-mgmt/net-snmp
     49        --host=sparc-rtems4.11 --with-rtems-bsp=erc32 4.11/net-mgmt/net-snmp
    5050    RTEMS Source Builder - Set Builder, v0.3.0
    5151    Build Set: 4.11/net-mgmt/net-snmp

  • user/installation/releases.rst

    r2591ca6 rd8beaab  
    5555   have a specific BSP built you can specify the BSP list by providing to the
    5656   RSB the option ``--with-rtemsbsp``. For example to build two BSPs for the
    57    SPARC architecture you can supply ``--with-rtemsbsp="erc32 sis"``. This can
     57   SPARC architecture you can supply ``--with-rtemsbsp="erc32 leon3"``. This can
    5858   speed the build time up for some architectures that have a lot of BSPs.
    5959
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