Changeset d86bae8 in rtems
- Timestamp:
- 03/30/04 11:47:03 (20 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 2a0a6851
- Parents:
- 9a26317
- Location:
- cpukit/score/cpu/m68k
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
cpukit/score/cpu/m68k/ChangeLog
r9a26317 rd86bae8 1 2004-03-30 Ralf Corsepius <ralf_corsepius@rtems.org> 2 3 * cpu.c, m68302.h, rtems/score/cpu.h, rtems/score/m68k.h: Convert to 4 using c99 fixed size types. 5 1 6 2004-03-29 Ralf Corsepius <ralf_corsepius@rtems.org> 2 7 -
cpukit/score/cpu/m68k/cpu.c
r9a26317 rd86bae8 35 35 onto the stack */ 36 36 37 u nsigned32slot;37 uint32_t slot; 38 38 39 39 for (slot = 0; slot < CPU_INTERRUPT_NUMBER_OF_VECTORS; slot++) … … 42 42 _CPU_ISR_jump_table[slot].format_id = slot << 2; 43 43 _CPU_ISR_jump_table[slot].jmp = M68K_JMP; 44 _CPU_ISR_jump_table[slot].isr_handler = (u nsigned32) 0xDEADDEAD;44 _CPU_ISR_jump_table[slot].isr_handler = (uint32_t ) 0xDEADDEAD; 45 45 } 46 46 #endif /* M68K_HAS_VBR */ … … 54 54 */ 55 55 56 u nsigned32_CPU_ISR_Get_level( void )57 { 58 u nsigned32level;56 uint32_t _CPU_ISR_Get_level( void ) 57 { 58 uint32_t level; 59 59 60 60 m68k_get_interrupt_level( level ); … … 69 69 70 70 void _CPU_ISR_install_raw_handler( 71 u nsigned32vector,71 uint32_t vector, 72 72 proc_ptr new_handler, 73 73 proc_ptr *old_handler … … 109 109 110 110 *old_handler = (proc_ptr) _CPU_ISR_jump_table[vector].isr_handler; 111 _CPU_ISR_jump_table[vector].isr_handler = (u nsigned32) new_handler;112 if ( (u nsigned32) interrupt_table != 0xFFFFFFFF )111 _CPU_ISR_jump_table[vector].isr_handler = (uint32_t ) new_handler; 112 if ( (uint32_t ) interrupt_table != 0xFFFFFFFF ) 113 113 interrupt_table[ vector ] = (proc_ptr) &_CPU_ISR_jump_table[vector]; 114 114 #endif /* M68K_HAS_VBR */ … … 131 131 132 132 void _CPU_ISR_install_vector( 133 u nsigned32vector,133 uint32_t vector, 134 134 proc_ptr new_handler, 135 135 proc_ptr *old_handler -
cpukit/score/cpu/m68k/m68302.h
r9a26317 rd86bae8 40 40 * Section 2.7 41 41 */ 42 #define M302_BAR (*((volatile rtems_unsigned16*) 0xf2))42 #define M302_BAR (*((volatile uint16_t *) 0xf2)) 43 43 44 44 /* … … 46 46 * Section 3.8.1 47 47 */ 48 #define M302_SCR (*((volatile rtems_unsigned32*) 0xf4))48 #define M302_SCR (*((volatile uint32_t *) 0xf4)) 49 49 /* 50 50 * SCR bits … … 237 237 */ 238 238 typedef struct { 239 rtems_unsigned16dram_high; /* DRAM high address and FC */240 rtems_unsigned16dram_low; /* DRAM low address */241 rtems_unsigned16increment; /* increment step (bytes/row) */242 rtems_unsigned16count; /* RAM refresh cycle count (#rows) */243 rtems_unsigned16t_ptr_h; /* temporary refresh high addr & FC */244 rtems_unsigned16t_ptr_l; /* temporary refresh low address */245 rtems_unsigned16t_count; /* temporary refresh cycles count */246 rtems_unsigned16res; /* reserved */239 uint16_t dram_high; /* DRAM high address and FC */ 240 uint16_t dram_low; /* DRAM low address */ 241 uint16_t increment; /* increment step (bytes/row) */ 242 uint16_t count; /* RAM refresh cycle count (#rows) */ 243 uint16_t t_ptr_h; /* temporary refresh high addr & FC */ 244 uint16_t t_ptr_l; /* temporary refresh low address */ 245 uint16_t t_count; /* temporary refresh cycles count */ 246 uint16_t res; /* reserved */ 247 247 } m302_DRAM_refresh_t; 248 248 … … 276 276 */ 277 277 typedef struct m302_SCC_bd { 278 rtems_unsigned16status; /* status and control */279 rtems_unsigned16length; /* data length */280 volatile rtems_unsigned8*buffer; /* data buffer pointer */278 uint16_t status; /* status and control */ 279 uint16_t length; /* data length */ 280 volatile uint8_t *buffer; /* data buffer pointer */ 281 281 } m302_SCC_bd_t; 282 282 … … 298 298 */ 299 299 typedef struct { 300 rtems_unsigned8rfcr; /* Rx Function Code */301 rtems_unsigned8tfcr; /* Tx Function Code */302 rtems_unsigned16mrblr; /* Maximum Rx Buffer Length */303 rtems_unsigned16_rstate; /* Rx Internal State */304 rtems_unsigned8res2;305 rtems_unsigned8rbd; /* Rx Internal Buffer Number */306 rtems_unsigned32_rdptr; /* Rx Internal Data Pointer */307 rtems_unsigned16_rcount; /* Rx Internal Byte Count */308 rtems_unsigned16_rtmp; /* Rx Temp */309 rtems_unsigned16_tstate; /* Tx Internal State */310 rtems_unsigned8res7;311 rtems_unsigned8tbd; /* Tx Internal Buffer Number */312 rtems_unsigned32_tdptr; /* Tx Internal Data Pointer */313 rtems_unsigned16_tcount; /* Tx Internal Byte Count */314 rtems_unsigned16_ttmp; /* Tx Temp */300 uint8_t rfcr; /* Rx Function Code */ 301 uint8_t tfcr; /* Tx Function Code */ 302 uint16_t mrblr; /* Maximum Rx Buffer Length */ 303 uint16_t _rstate; /* Rx Internal State */ 304 uint8_t res2; 305 uint8_t rbd; /* Rx Internal Buffer Number */ 306 uint32_t _rdptr; /* Rx Internal Data Pointer */ 307 uint16_t _rcount; /* Rx Internal Byte Count */ 308 uint16_t _rtmp; /* Rx Temp */ 309 uint16_t _tstate; /* Tx Internal State */ 310 uint8_t res7; 311 uint8_t tbd; /* Tx Internal Buffer Number */ 312 uint32_t _tdptr; /* Tx Internal Data Pointer */ 313 uint16_t _tcount; /* Tx Internal Byte Count */ 314 uint16_t _ttmp; /* Tx Temp */ 315 315 } m302_SCC_parameters_t; 316 316 … … 320 320 */ 321 321 typedef struct { 322 rtems_unsigned16max_idl; /* Maximum IDLE Characters (rx) */323 rtems_unsigned16idlc; /* Temporary rx IDLE counter */324 rtems_unsigned16brkcr; /* Break Count Register (tx) */325 rtems_unsigned16parec; /* Receive Parity Error Counter */326 rtems_unsigned16frmec; /* Receive Framing Error Counter */327 rtems_unsigned16nosec; /* Receive Noise Counter */328 rtems_unsigned16brkec; /* Receive Break Condition Counter */329 rtems_unsigned16uaddr1; /* UART ADDRESS Character 1 */330 rtems_unsigned16uaddr2; /* UART ADDRESS Character 2 */331 rtems_unsigned16rccr; /* Receive Control Character Register */332 rtems_unsigned16character[8]; /* Control Characters 1 through 8*/322 uint16_t max_idl; /* Maximum IDLE Characters (rx) */ 323 uint16_t idlc; /* Temporary rx IDLE counter */ 324 uint16_t brkcr; /* Break Count Register (tx) */ 325 uint16_t parec; /* Receive Parity Error Counter */ 326 uint16_t frmec; /* Receive Framing Error Counter */ 327 uint16_t nosec; /* Receive Noise Counter */ 328 uint16_t brkec; /* Receive Break Condition Counter */ 329 uint16_t uaddr1; /* UART ADDRESS Character 1 */ 330 uint16_t uaddr2; /* UART ADDRESS Character 2 */ 331 uint16_t rccr; /* Receive Control Character Register */ 332 uint16_t character[8]; /* Control Characters 1 through 8*/ 333 333 } m302_SCC_UartSpecific_t; 334 334 /* … … 389 389 */ 390 390 typedef struct { 391 rtems_unsigned16rcrc_l; /* Temp Receive CRC Low */392 rtems_unsigned16rcrc_h; /* Temp Receive CRC High */393 rtems_unsigned16c_mask_l; /* CRC Mask Low */394 rtems_unsigned16c_mask_h; /* CRC Mask High */395 rtems_unsigned16tcrc_l; /* Temp Transmit CRC Low */396 rtems_unsigned16tcrc_h; /* Temp Transmit CRC High */397 398 rtems_unsigned16disfc; /* Discard Frame Counter */399 rtems_unsigned16crcec; /* CRC Error Counter */400 rtems_unsigned16abtsc; /* Abort Sequence Counter */401 rtems_unsigned16nmarc; /* Nonmatching Address Received Cntr */402 rtems_unsigned16retrc; /* Frame Retransmission Counter */403 404 rtems_unsigned16mflr; /* Maximum Frame Length Register */405 rtems_unsigned16max_cnt; /* Maximum_Length Counter */406 407 rtems_unsigned16hmask; /* User Defined Frame Address Mask */408 rtems_unsigned16haddr1; /* User Defined Frame Address */409 rtems_unsigned16haddr2; /* " */410 rtems_unsigned16haddr3; /* " */411 rtems_unsigned16haddr4; /* " */391 uint16_t rcrc_l; /* Temp Receive CRC Low */ 392 uint16_t rcrc_h; /* Temp Receive CRC High */ 393 uint16_t c_mask_l; /* CRC Mask Low */ 394 uint16_t c_mask_h; /* CRC Mask High */ 395 uint16_t tcrc_l; /* Temp Transmit CRC Low */ 396 uint16_t tcrc_h; /* Temp Transmit CRC High */ 397 398 uint16_t disfc; /* Discard Frame Counter */ 399 uint16_t crcec; /* CRC Error Counter */ 400 uint16_t abtsc; /* Abort Sequence Counter */ 401 uint16_t nmarc; /* Nonmatching Address Received Cntr */ 402 uint16_t retrc; /* Frame Retransmission Counter */ 403 404 uint16_t mflr; /* Maximum Frame Length Register */ 405 uint16_t max_cnt; /* Maximum_Length Counter */ 406 407 uint16_t hmask; /* User Defined Frame Address Mask */ 408 uint16_t haddr1; /* User Defined Frame Address */ 409 uint16_t haddr2; /* " */ 410 uint16_t haddr3; /* " */ 411 uint16_t haddr4; /* " */ 412 412 } m302_SCC_HdlcSpecific_t; 413 413 /* … … 462 462 m302_SCC_HdlcSpecific_t hdlc; 463 463 } prot; 464 rtems_unsigned8res[0x040]; /* +0C0 reserved, (not implemented) */464 uint8_t res[0x040]; /* +0C0 reserved, (not implemented) */ 465 465 } m302_SCC_t; 466 466 … … 470 470 */ 471 471 typedef struct { 472 rtems_unsigned16res1;473 rtems_unsigned16scon; /* SCC Configuration Register 4.5.2 */474 rtems_unsigned16scm; /* SCC Mode Register 4.5.3 */475 rtems_unsigned16dsr; /* SCC Data Synchronization Register 4.5.4 */476 rtems_unsigned8scce; /* SCC Event Register 4.5.8.1 */477 rtems_unsigned8res2;478 rtems_unsigned8sccm; /* SCC Mask Register 4.5.8.2 */479 rtems_unsigned8res3;480 rtems_unsigned8sccs; /* SCC Status Register 4.5.8.3 */481 rtems_unsigned8res4;482 rtems_unsigned16res5;472 uint16_t res1; 473 uint16_t scon; /* SCC Configuration Register 4.5.2 */ 474 uint16_t scm; /* SCC Mode Register 4.5.3 */ 475 uint16_t dsr; /* SCC Data Synchronization Register 4.5.4 */ 476 uint8_t scce; /* SCC Event Register 4.5.8.1 */ 477 uint8_t res2; 478 uint8_t sccm; /* SCC Mask Register 4.5.8.2 */ 479 uint8_t res3; 480 uint8_t sccs; /* SCC Status Register 4.5.8.3 */ 481 uint8_t res4; 482 uint16_t res5; 483 483 } m302_SCC_Registers_t; 484 484 … … 510 510 typedef struct { 511 511 /* offset +800 */ 512 rtems_unsigned16res0;513 rtems_unsigned16cmr; /* IDMA Channel Mode Register */514 rtems_unsigned32sapr; /* IDMA Source Address Pointer */515 rtems_unsigned32dapr; /* IDMA Destination Address Pointer */516 rtems_unsigned16bcr; /* IDMA Byte Count Register */517 rtems_unsigned8csr; /* IDMA Channel Status Register */518 rtems_unsigned8res1;519 rtems_unsigned8fcr; /* IDMA Function Code Register */520 rtems_unsigned8res2;512 uint16_t res0; 513 uint16_t cmr; /* IDMA Channel Mode Register */ 514 uint32_t sapr; /* IDMA Source Address Pointer */ 515 uint32_t dapr; /* IDMA Destination Address Pointer */ 516 uint16_t bcr; /* IDMA Byte Count Register */ 517 uint8_t csr; /* IDMA Channel Status Register */ 518 uint8_t res1; 519 uint8_t fcr; /* IDMA Function Code Register */ 520 uint8_t res2; 521 521 522 522 /* offset +812 */ 523 rtems_unsigned16gimr; /* Global Interrupt Mode Register */524 rtems_unsigned16ipr; /* Interrupt Pending Register */525 rtems_unsigned16imr; /* Interrupt Mask Register */526 rtems_unsigned16isr; /* Interrupt In-Service Register */527 rtems_unsigned16res3;528 rtems_unsigned16res4;523 uint16_t gimr; /* Global Interrupt Mode Register */ 524 uint16_t ipr; /* Interrupt Pending Register */ 525 uint16_t imr; /* Interrupt Mask Register */ 526 uint16_t isr; /* Interrupt In-Service Register */ 527 uint16_t res3; 528 uint16_t res4; 529 529 530 530 /* offset +81e */ 531 rtems_unsigned16pacnt; /* Port A Control Register */532 rtems_unsigned16paddr; /* Port A Data Direction Register */533 rtems_unsigned16padat; /* Port A Data Register */534 rtems_unsigned16pbcnt; /* Port B Control Register */535 rtems_unsigned16pbddr; /* Port B Data Direction Register */536 rtems_unsigned16pbdat; /* Port B Data Register */537 rtems_unsigned16res5;531 uint16_t pacnt; /* Port A Control Register */ 532 uint16_t paddr; /* Port A Data Direction Register */ 533 uint16_t padat; /* Port A Data Register */ 534 uint16_t pbcnt; /* Port B Control Register */ 535 uint16_t pbddr; /* Port B Data Direction Register */ 536 uint16_t pbdat; /* Port B Data Register */ 537 uint16_t res5; 538 538 539 539 /* offset +82c */ 540 rtems_unsigned16res6;541 rtems_unsigned16res7;542 543 rtems_unsigned16br0; /* Base Register (CS0) */544 rtems_unsigned16or0; /* Option Register (CS0) */545 rtems_unsigned16br1; /* Base Register (CS1) */546 rtems_unsigned16or1; /* Option Register (CS1) */547 rtems_unsigned16br2; /* Base Register (CS2) */548 rtems_unsigned16or2; /* Option Register (CS2) */549 rtems_unsigned16br3; /* Base Register (CS3) */550 rtems_unsigned16or3; /* Option Register (CS3) */540 uint16_t res6; 541 uint16_t res7; 542 543 uint16_t br0; /* Base Register (CS0) */ 544 uint16_t or0; /* Option Register (CS0) */ 545 uint16_t br1; /* Base Register (CS1) */ 546 uint16_t or1; /* Option Register (CS1) */ 547 uint16_t br2; /* Base Register (CS2) */ 548 uint16_t or2; /* Option Register (CS2) */ 549 uint16_t br3; /* Base Register (CS3) */ 550 uint16_t or3; /* Option Register (CS3) */ 551 551 552 552 /* offset +840 */ 553 rtems_unsigned16tmr1; /* Timer Unit 1 Mode Register */554 rtems_unsigned16trr1; /* Timer Unit 1 Reference Register */555 rtems_unsigned16tcr1; /* Timer Unit 1 Capture Register */556 rtems_unsigned16tcn1; /* Timer Unit 1 Counter */557 rtems_unsigned8res8;558 rtems_unsigned8ter1; /* Timer Unit 1 Event Register */559 rtems_unsigned16wrr; /* Watchdog Reference Register */560 rtems_unsigned16wcn; /* Watchdog Counter */561 rtems_unsigned16res9;562 rtems_unsigned16tmr2; /* Timer Unit 2 Mode Register */563 rtems_unsigned16trr2; /* Timer Unit 2 Reference Register */564 rtems_unsigned16tcr2; /* Timer Unit 2 Capture Register */565 rtems_unsigned16tcn2; /* Timer Unit 2 Counter */566 rtems_unsigned8resa;567 rtems_unsigned8ter2; /* Timer Unit 2 Event Register */568 rtems_unsigned16resb;569 rtems_unsigned16resc;570 rtems_unsigned16resd;553 uint16_t tmr1; /* Timer Unit 1 Mode Register */ 554 uint16_t trr1; /* Timer Unit 1 Reference Register */ 555 uint16_t tcr1; /* Timer Unit 1 Capture Register */ 556 uint16_t tcn1; /* Timer Unit 1 Counter */ 557 uint8_t res8; 558 uint8_t ter1; /* Timer Unit 1 Event Register */ 559 uint16_t wrr; /* Watchdog Reference Register */ 560 uint16_t wcn; /* Watchdog Counter */ 561 uint16_t res9; 562 uint16_t tmr2; /* Timer Unit 2 Mode Register */ 563 uint16_t trr2; /* Timer Unit 2 Reference Register */ 564 uint16_t tcr2; /* Timer Unit 2 Capture Register */ 565 uint16_t tcn2; /* Timer Unit 2 Counter */ 566 uint8_t resa; 567 uint8_t ter2; /* Timer Unit 2 Event Register */ 568 uint16_t resb; 569 uint16_t resc; 570 uint16_t resd; 571 571 572 572 /* offset +860 */ 573 rtems_unsigned8cr; /* Command Register */574 rtems_unsigned8rese[0x1f];573 uint8_t cr; /* Command Register */ 574 uint8_t rese[0x1f]; 575 575 576 576 /* offset +880, +890, +8a0 */ … … 578 578 579 579 /* offset +8b0 */ 580 rtems_unsigned16spmode; /* SCP,SMC Mode and Clock Cntrl Reg */581 rtems_unsigned16simask; /* Serial Interface Mask Register */582 rtems_unsigned16simode; /* Serial Interface Mode Register */580 uint16_t spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ 581 uint16_t simask; /* Serial Interface Mask Register */ 582 uint16_t simode; /* Serial Interface Mode Register */ 583 583 } m302_internalReg_t ; 584 584 … … 590 590 */ 591 591 typedef struct { 592 rtems_unsigned8mem[0x240]; /* +000 User Data Memory */593 rtems_unsigned8res1[0x1c0]; /* +240 reserved, (not implemented) */592 uint8_t mem[0x240]; /* +000 User Data Memory */ 593 uint8_t res1[0x1c0]; /* +240 reserved, (not implemented) */ 594 594 m302_SCC_t scc1; /* +400 SCC1 */ 595 595 m302_SCC_t scc2; /* +500 SCC2 */ 596 596 m302_SCC_t scc3; /* +600 SCC3 */ 597 rtems_unsigned8res2[0x100]; /* +700 reserved, (not implemented) */597 uint8_t res2[0x100]; /* +700 reserved, (not implemented) */ 598 598 m302_internalReg_t reg; /* +800 68302 Internal Registers */ 599 599 } m302_dualPortRAM_t; -
cpukit/score/cpu/m68k/rtems/m68k/m68302.h
r9a26317 rd86bae8 40 40 * Section 2.7 41 41 */ 42 #define M302_BAR (*((volatile rtems_unsigned16*) 0xf2))42 #define M302_BAR (*((volatile uint16_t *) 0xf2)) 43 43 44 44 /* … … 46 46 * Section 3.8.1 47 47 */ 48 #define M302_SCR (*((volatile rtems_unsigned32*) 0xf4))48 #define M302_SCR (*((volatile uint32_t *) 0xf4)) 49 49 /* 50 50 * SCR bits … … 237 237 */ 238 238 typedef struct { 239 rtems_unsigned16dram_high; /* DRAM high address and FC */240 rtems_unsigned16dram_low; /* DRAM low address */241 rtems_unsigned16increment; /* increment step (bytes/row) */242 rtems_unsigned16count; /* RAM refresh cycle count (#rows) */243 rtems_unsigned16t_ptr_h; /* temporary refresh high addr & FC */244 rtems_unsigned16t_ptr_l; /* temporary refresh low address */245 rtems_unsigned16t_count; /* temporary refresh cycles count */246 rtems_unsigned16res; /* reserved */239 uint16_t dram_high; /* DRAM high address and FC */ 240 uint16_t dram_low; /* DRAM low address */ 241 uint16_t increment; /* increment step (bytes/row) */ 242 uint16_t count; /* RAM refresh cycle count (#rows) */ 243 uint16_t t_ptr_h; /* temporary refresh high addr & FC */ 244 uint16_t t_ptr_l; /* temporary refresh low address */ 245 uint16_t t_count; /* temporary refresh cycles count */ 246 uint16_t res; /* reserved */ 247 247 } m302_DRAM_refresh_t; 248 248 … … 276 276 */ 277 277 typedef struct m302_SCC_bd { 278 rtems_unsigned16status; /* status and control */279 rtems_unsigned16length; /* data length */280 volatile rtems_unsigned8*buffer; /* data buffer pointer */278 uint16_t status; /* status and control */ 279 uint16_t length; /* data length */ 280 volatile uint8_t *buffer; /* data buffer pointer */ 281 281 } m302_SCC_bd_t; 282 282 … … 298 298 */ 299 299 typedef struct { 300 rtems_unsigned8rfcr; /* Rx Function Code */301 rtems_unsigned8tfcr; /* Tx Function Code */302 rtems_unsigned16mrblr; /* Maximum Rx Buffer Length */303 rtems_unsigned16_rstate; /* Rx Internal State */304 rtems_unsigned8res2;305 rtems_unsigned8rbd; /* Rx Internal Buffer Number */306 rtems_unsigned32_rdptr; /* Rx Internal Data Pointer */307 rtems_unsigned16_rcount; /* Rx Internal Byte Count */308 rtems_unsigned16_rtmp; /* Rx Temp */309 rtems_unsigned16_tstate; /* Tx Internal State */310 rtems_unsigned8res7;311 rtems_unsigned8tbd; /* Tx Internal Buffer Number */312 rtems_unsigned32_tdptr; /* Tx Internal Data Pointer */313 rtems_unsigned16_tcount; /* Tx Internal Byte Count */314 rtems_unsigned16_ttmp; /* Tx Temp */300 uint8_t rfcr; /* Rx Function Code */ 301 uint8_t tfcr; /* Tx Function Code */ 302 uint16_t mrblr; /* Maximum Rx Buffer Length */ 303 uint16_t _rstate; /* Rx Internal State */ 304 uint8_t res2; 305 uint8_t rbd; /* Rx Internal Buffer Number */ 306 uint32_t _rdptr; /* Rx Internal Data Pointer */ 307 uint16_t _rcount; /* Rx Internal Byte Count */ 308 uint16_t _rtmp; /* Rx Temp */ 309 uint16_t _tstate; /* Tx Internal State */ 310 uint8_t res7; 311 uint8_t tbd; /* Tx Internal Buffer Number */ 312 uint32_t _tdptr; /* Tx Internal Data Pointer */ 313 uint16_t _tcount; /* Tx Internal Byte Count */ 314 uint16_t _ttmp; /* Tx Temp */ 315 315 } m302_SCC_parameters_t; 316 316 … … 320 320 */ 321 321 typedef struct { 322 rtems_unsigned16max_idl; /* Maximum IDLE Characters (rx) */323 rtems_unsigned16idlc; /* Temporary rx IDLE counter */324 rtems_unsigned16brkcr; /* Break Count Register (tx) */325 rtems_unsigned16parec; /* Receive Parity Error Counter */326 rtems_unsigned16frmec; /* Receive Framing Error Counter */327 rtems_unsigned16nosec; /* Receive Noise Counter */328 rtems_unsigned16brkec; /* Receive Break Condition Counter */329 rtems_unsigned16uaddr1; /* UART ADDRESS Character 1 */330 rtems_unsigned16uaddr2; /* UART ADDRESS Character 2 */331 rtems_unsigned16rccr; /* Receive Control Character Register */332 rtems_unsigned16character[8]; /* Control Characters 1 through 8*/322 uint16_t max_idl; /* Maximum IDLE Characters (rx) */ 323 uint16_t idlc; /* Temporary rx IDLE counter */ 324 uint16_t brkcr; /* Break Count Register (tx) */ 325 uint16_t parec; /* Receive Parity Error Counter */ 326 uint16_t frmec; /* Receive Framing Error Counter */ 327 uint16_t nosec; /* Receive Noise Counter */ 328 uint16_t brkec; /* Receive Break Condition Counter */ 329 uint16_t uaddr1; /* UART ADDRESS Character 1 */ 330 uint16_t uaddr2; /* UART ADDRESS Character 2 */ 331 uint16_t rccr; /* Receive Control Character Register */ 332 uint16_t character[8]; /* Control Characters 1 through 8*/ 333 333 } m302_SCC_UartSpecific_t; 334 334 /* … … 389 389 */ 390 390 typedef struct { 391 rtems_unsigned16rcrc_l; /* Temp Receive CRC Low */392 rtems_unsigned16rcrc_h; /* Temp Receive CRC High */393 rtems_unsigned16c_mask_l; /* CRC Mask Low */394 rtems_unsigned16c_mask_h; /* CRC Mask High */395 rtems_unsigned16tcrc_l; /* Temp Transmit CRC Low */396 rtems_unsigned16tcrc_h; /* Temp Transmit CRC High */397 398 rtems_unsigned16disfc; /* Discard Frame Counter */399 rtems_unsigned16crcec; /* CRC Error Counter */400 rtems_unsigned16abtsc; /* Abort Sequence Counter */401 rtems_unsigned16nmarc; /* Nonmatching Address Received Cntr */402 rtems_unsigned16retrc; /* Frame Retransmission Counter */403 404 rtems_unsigned16mflr; /* Maximum Frame Length Register */405 rtems_unsigned16max_cnt; /* Maximum_Length Counter */406 407 rtems_unsigned16hmask; /* User Defined Frame Address Mask */408 rtems_unsigned16haddr1; /* User Defined Frame Address */409 rtems_unsigned16haddr2; /* " */410 rtems_unsigned16haddr3; /* " */411 rtems_unsigned16haddr4; /* " */391 uint16_t rcrc_l; /* Temp Receive CRC Low */ 392 uint16_t rcrc_h; /* Temp Receive CRC High */ 393 uint16_t c_mask_l; /* CRC Mask Low */ 394 uint16_t c_mask_h; /* CRC Mask High */ 395 uint16_t tcrc_l; /* Temp Transmit CRC Low */ 396 uint16_t tcrc_h; /* Temp Transmit CRC High */ 397 398 uint16_t disfc; /* Discard Frame Counter */ 399 uint16_t crcec; /* CRC Error Counter */ 400 uint16_t abtsc; /* Abort Sequence Counter */ 401 uint16_t nmarc; /* Nonmatching Address Received Cntr */ 402 uint16_t retrc; /* Frame Retransmission Counter */ 403 404 uint16_t mflr; /* Maximum Frame Length Register */ 405 uint16_t max_cnt; /* Maximum_Length Counter */ 406 407 uint16_t hmask; /* User Defined Frame Address Mask */ 408 uint16_t haddr1; /* User Defined Frame Address */ 409 uint16_t haddr2; /* " */ 410 uint16_t haddr3; /* " */ 411 uint16_t haddr4; /* " */ 412 412 } m302_SCC_HdlcSpecific_t; 413 413 /* … … 462 462 m302_SCC_HdlcSpecific_t hdlc; 463 463 } prot; 464 rtems_unsigned8res[0x040]; /* +0C0 reserved, (not implemented) */464 uint8_t res[0x040]; /* +0C0 reserved, (not implemented) */ 465 465 } m302_SCC_t; 466 466 … … 470 470 */ 471 471 typedef struct { 472 rtems_unsigned16res1;473 rtems_unsigned16scon; /* SCC Configuration Register 4.5.2 */474 rtems_unsigned16scm; /* SCC Mode Register 4.5.3 */475 rtems_unsigned16dsr; /* SCC Data Synchronization Register 4.5.4 */476 rtems_unsigned8scce; /* SCC Event Register 4.5.8.1 */477 rtems_unsigned8res2;478 rtems_unsigned8sccm; /* SCC Mask Register 4.5.8.2 */479 rtems_unsigned8res3;480 rtems_unsigned8sccs; /* SCC Status Register 4.5.8.3 */481 rtems_unsigned8res4;482 rtems_unsigned16res5;472 uint16_t res1; 473 uint16_t scon; /* SCC Configuration Register 4.5.2 */ 474 uint16_t scm; /* SCC Mode Register 4.5.3 */ 475 uint16_t dsr; /* SCC Data Synchronization Register 4.5.4 */ 476 uint8_t scce; /* SCC Event Register 4.5.8.1 */ 477 uint8_t res2; 478 uint8_t sccm; /* SCC Mask Register 4.5.8.2 */ 479 uint8_t res3; 480 uint8_t sccs; /* SCC Status Register 4.5.8.3 */ 481 uint8_t res4; 482 uint16_t res5; 483 483 } m302_SCC_Registers_t; 484 484 … … 510 510 typedef struct { 511 511 /* offset +800 */ 512 rtems_unsigned16res0;513 rtems_unsigned16cmr; /* IDMA Channel Mode Register */514 rtems_unsigned32sapr; /* IDMA Source Address Pointer */515 rtems_unsigned32dapr; /* IDMA Destination Address Pointer */516 rtems_unsigned16bcr; /* IDMA Byte Count Register */517 rtems_unsigned8csr; /* IDMA Channel Status Register */518 rtems_unsigned8res1;519 rtems_unsigned8fcr; /* IDMA Function Code Register */520 rtems_unsigned8res2;512 uint16_t res0; 513 uint16_t cmr; /* IDMA Channel Mode Register */ 514 uint32_t sapr; /* IDMA Source Address Pointer */ 515 uint32_t dapr; /* IDMA Destination Address Pointer */ 516 uint16_t bcr; /* IDMA Byte Count Register */ 517 uint8_t csr; /* IDMA Channel Status Register */ 518 uint8_t res1; 519 uint8_t fcr; /* IDMA Function Code Register */ 520 uint8_t res2; 521 521 522 522 /* offset +812 */ 523 rtems_unsigned16gimr; /* Global Interrupt Mode Register */524 rtems_unsigned16ipr; /* Interrupt Pending Register */525 rtems_unsigned16imr; /* Interrupt Mask Register */526 rtems_unsigned16isr; /* Interrupt In-Service Register */527 rtems_unsigned16res3;528 rtems_unsigned16res4;523 uint16_t gimr; /* Global Interrupt Mode Register */ 524 uint16_t ipr; /* Interrupt Pending Register */ 525 uint16_t imr; /* Interrupt Mask Register */ 526 uint16_t isr; /* Interrupt In-Service Register */ 527 uint16_t res3; 528 uint16_t res4; 529 529 530 530 /* offset +81e */ 531 rtems_unsigned16pacnt; /* Port A Control Register */532 rtems_unsigned16paddr; /* Port A Data Direction Register */533 rtems_unsigned16padat; /* Port A Data Register */534 rtems_unsigned16pbcnt; /* Port B Control Register */535 rtems_unsigned16pbddr; /* Port B Data Direction Register */536 rtems_unsigned16pbdat; /* Port B Data Register */537 rtems_unsigned16res5;531 uint16_t pacnt; /* Port A Control Register */ 532 uint16_t paddr; /* Port A Data Direction Register */ 533 uint16_t padat; /* Port A Data Register */ 534 uint16_t pbcnt; /* Port B Control Register */ 535 uint16_t pbddr; /* Port B Data Direction Register */ 536 uint16_t pbdat; /* Port B Data Register */ 537 uint16_t res5; 538 538 539 539 /* offset +82c */ 540 rtems_unsigned16res6;541 rtems_unsigned16res7;542 543 rtems_unsigned16br0; /* Base Register (CS0) */544 rtems_unsigned16or0; /* Option Register (CS0) */545 rtems_unsigned16br1; /* Base Register (CS1) */546 rtems_unsigned16or1; /* Option Register (CS1) */547 rtems_unsigned16br2; /* Base Register (CS2) */548 rtems_unsigned16or2; /* Option Register (CS2) */549 rtems_unsigned16br3; /* Base Register (CS3) */550 rtems_unsigned16or3; /* Option Register (CS3) */540 uint16_t res6; 541 uint16_t res7; 542 543 uint16_t br0; /* Base Register (CS0) */ 544 uint16_t or0; /* Option Register (CS0) */ 545 uint16_t br1; /* Base Register (CS1) */ 546 uint16_t or1; /* Option Register (CS1) */ 547 uint16_t br2; /* Base Register (CS2) */ 548 uint16_t or2; /* Option Register (CS2) */ 549 uint16_t br3; /* Base Register (CS3) */ 550 uint16_t or3; /* Option Register (CS3) */ 551 551 552 552 /* offset +840 */ 553 rtems_unsigned16tmr1; /* Timer Unit 1 Mode Register */554 rtems_unsigned16trr1; /* Timer Unit 1 Reference Register */555 rtems_unsigned16tcr1; /* Timer Unit 1 Capture Register */556 rtems_unsigned16tcn1; /* Timer Unit 1 Counter */557 rtems_unsigned8res8;558 rtems_unsigned8ter1; /* Timer Unit 1 Event Register */559 rtems_unsigned16wrr; /* Watchdog Reference Register */560 rtems_unsigned16wcn; /* Watchdog Counter */561 rtems_unsigned16res9;562 rtems_unsigned16tmr2; /* Timer Unit 2 Mode Register */563 rtems_unsigned16trr2; /* Timer Unit 2 Reference Register */564 rtems_unsigned16tcr2; /* Timer Unit 2 Capture Register */565 rtems_unsigned16tcn2; /* Timer Unit 2 Counter */566 rtems_unsigned8resa;567 rtems_unsigned8ter2; /* Timer Unit 2 Event Register */568 rtems_unsigned16resb;569 rtems_unsigned16resc;570 rtems_unsigned16resd;553 uint16_t tmr1; /* Timer Unit 1 Mode Register */ 554 uint16_t trr1; /* Timer Unit 1 Reference Register */ 555 uint16_t tcr1; /* Timer Unit 1 Capture Register */ 556 uint16_t tcn1; /* Timer Unit 1 Counter */ 557 uint8_t res8; 558 uint8_t ter1; /* Timer Unit 1 Event Register */ 559 uint16_t wrr; /* Watchdog Reference Register */ 560 uint16_t wcn; /* Watchdog Counter */ 561 uint16_t res9; 562 uint16_t tmr2; /* Timer Unit 2 Mode Register */ 563 uint16_t trr2; /* Timer Unit 2 Reference Register */ 564 uint16_t tcr2; /* Timer Unit 2 Capture Register */ 565 uint16_t tcn2; /* Timer Unit 2 Counter */ 566 uint8_t resa; 567 uint8_t ter2; /* Timer Unit 2 Event Register */ 568 uint16_t resb; 569 uint16_t resc; 570 uint16_t resd; 571 571 572 572 /* offset +860 */ 573 rtems_unsigned8cr; /* Command Register */574 rtems_unsigned8rese[0x1f];573 uint8_t cr; /* Command Register */ 574 uint8_t rese[0x1f]; 575 575 576 576 /* offset +880, +890, +8a0 */ … … 578 578 579 579 /* offset +8b0 */ 580 rtems_unsigned16spmode; /* SCP,SMC Mode and Clock Cntrl Reg */581 rtems_unsigned16simask; /* Serial Interface Mask Register */582 rtems_unsigned16simode; /* Serial Interface Mode Register */580 uint16_t spmode; /* SCP,SMC Mode and Clock Cntrl Reg */ 581 uint16_t simask; /* Serial Interface Mask Register */ 582 uint16_t simode; /* Serial Interface Mode Register */ 583 583 } m302_internalReg_t ; 584 584 … … 590 590 */ 591 591 typedef struct { 592 rtems_unsigned8mem[0x240]; /* +000 User Data Memory */593 rtems_unsigned8res1[0x1c0]; /* +240 reserved, (not implemented) */592 uint8_t mem[0x240]; /* +000 User Data Memory */ 593 uint8_t res1[0x1c0]; /* +240 reserved, (not implemented) */ 594 594 m302_SCC_t scc1; /* +400 SCC1 */ 595 595 m302_SCC_t scc2; /* +500 SCC2 */ 596 596 m302_SCC_t scc3; /* +600 SCC3 */ 597 rtems_unsigned8res2[0x100]; /* +700 reserved, (not implemented) */597 uint8_t res2[0x100]; /* +700 reserved, (not implemented) */ 598 598 m302_internalReg_t reg; /* +800 68302 Internal Registers */ 599 599 } m302_dualPortRAM_t; -
cpukit/score/cpu/m68k/rtems/score/cpu.h
r9a26317 rd86bae8 106 106 107 107 typedef struct { 108 u nsigned32sr; /* (sr) status register */109 u nsigned32d2; /* (d2) data register 2 */110 u nsigned32d3; /* (d3) data register 3 */111 u nsigned32d4; /* (d4) data register 4 */112 u nsigned32d5; /* (d5) data register 5 */113 u nsigned32d6; /* (d6) data register 6 */114 u nsigned32d7; /* (d7) data register 7 */108 uint32_t sr; /* (sr) status register */ 109 uint32_t d2; /* (d2) data register 2 */ 110 uint32_t d3; /* (d3) data register 3 */ 111 uint32_t d4; /* (d4) data register 4 */ 112 uint32_t d5; /* (d5) data register 5 */ 113 uint32_t d6; /* (d6) data register 6 */ 114 uint32_t d7; /* (d7) data register 7 */ 115 115 void *a2; /* (a2) address register 2 */ 116 116 void *a3; /* (a3) address register 3 */ … … 135 135 136 136 typedef struct { 137 u nsigned16_exception_bits;138 u nsigned16_trap_enable_bits;139 u nsigned16_sticky_bits;140 u nsigned16_rounding_mode;141 u nsigned16_format;142 u nsigned16_last_operation;137 uint16_t _exception_bits; 138 uint16_t _trap_enable_bits; 139 uint16_t _sticky_bits; 140 uint16_t _rounding_mode; 141 uint16_t _format; 142 uint16_t _last_operation; 143 143 union { 144 144 float sf; … … 158 158 159 159 typedef struct { 160 u nsigned8fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */160 uint8_t fp_save_area[332]; /* 216 bytes for FSAVE/FRESTORE */ 161 161 /* 96 bytes for FMOVEM FP0-7 */ 162 162 /* 12 bytes for FMOVEM CREGS */ … … 173 173 174 174 typedef struct { 175 u nsigned32vecnum; /* vector number */175 uint32_t vecnum; /* vector number */ 176 176 } CPU_Interrupt_frame; 177 177 178 178 typedef struct { 179 u nsigned32vecnum; /* vector number */180 u nsigned32sr; /* status register */181 u nsigned32pc; /* program counter */182 u nsigned32d0, d1, d2, d3, d4, d5, d6, d7;183 u nsigned32a0, a1, a2, a3, a4, a5, a6, a7;179 uint32_t vecnum; /* vector number */ 180 uint32_t sr; /* status register */ 181 uint32_t pc; /* program counter */ 182 uint32_t d0, d1, d2, d3, d4, d5, d6, d7; 183 uint32_t a0, a1, a2, a3, a4, a5, a6, a7; 184 184 } CPU_Exception_frame; 185 185 … … 195 195 void (*idle_task)( void ); 196 196 boolean do_zero_of_workspace; 197 u nsigned32idle_task_stack_size;198 u nsigned32interrupt_stack_size;199 u nsigned32extra_mpci_receive_server_stack;200 void * (*stack_allocate_hook)( u nsigned32);197 uint32_t idle_task_stack_size; 198 uint32_t interrupt_stack_size; 199 uint32_t extra_mpci_receive_server_stack; 200 void * (*stack_allocate_hook)( uint32_t ); 201 201 void (*stack_free_hook)( void* ); 202 202 /* end of fields required on all CPUs */ … … 237 237 238 238 typedef struct { 239 u nsigned16move_a7; /* move #FORMAT_ID,%a7@- */240 u nsigned16format_id;241 u nsigned16jmp; /* jmp _ISR_Handlers */242 u nsigned32isr_handler;239 uint16_t move_a7; /* move #FORMAT_ID,%a7@- */ 240 uint16_t format_id; 241 uint16_t jmp; /* jmp _ISR_Handlers */ 242 uint32_t isr_handler; 243 243 } _CPU_ISR_handler_entry; 244 244 … … 338 338 m68k_set_interrupt_level( _newlevel ) 339 339 340 u nsigned32_CPU_ISR_Get_level( void );340 uint32_t _CPU_ISR_Get_level( void ); 341 341 342 342 /* end of ISR handler macros */ … … 355 355 _isr, _entry_point, _is_fp ) \ 356 356 do { \ 357 u nsigned32_stack; \357 uint32_t _stack; \ 358 358 \ 359 359 (_the_context)->sr = 0x3000 | ((_isr) << 8); \ 360 _stack = (u nsigned32)(_stack_base) + (_size) - 4; \360 _stack = (uint32_t )(_stack_base) + (_size) - 4; \ 361 361 (_the_context)->a7_msp = (void *)_stack; \ 362 362 *(void **)_stack = (void *)(_entry_point); \ … … 408 408 409 409 #define _CPU_Context_Initialize_fp( _fp_area ) \ 410 { u nsigned32 *_fp_context = (unsigned32*)*(_fp_area); \410 { uint32_t *_fp_context = (uint32_t *)*(_fp_area); \ 411 411 \ 412 412 *(--(_fp_context)) = 0; \ 413 *(_fp_area) = (u nsigned8*)(_fp_context); \413 *(_fp_area) = (uint8_t *)(_fp_context); \ 414 414 } 415 415 #endif … … 587 587 588 588 void _CPU_ISR_install_raw_handler( 589 u nsigned32vector,589 uint32_t vector, 590 590 proc_ptr new_handler, 591 591 proc_ptr *old_handler … … 599 599 600 600 void _CPU_ISR_install_vector( 601 u nsigned32vector,601 uint32_t vector, 602 602 proc_ptr new_handler, 603 603 proc_ptr *old_handler … … 672 672 673 673 SCORE_EXTERN int (*_FPSP_install_raw_handler)( 674 u nsigned32vector,674 uint32_t vector, 675 675 proc_ptr new_handler, 676 676 proc_ptr *old_handler -
cpukit/score/cpu/m68k/rtems/score/m68k.h
r9a26317 rd86bae8 257 257 #if ( M68K_COLDFIRE_ARCH == 1 ) 258 258 #define m68k_disable_interrupts( _level ) \ 259 do { register u nsigned32_tmpsr = 0x0700; \259 do { register uint32_t _tmpsr = 0x0700; \ 260 260 asm volatile ( "move.w %%sr,%0\n\t" \ 261 261 "or.l %0,%1\n\t" \ … … 275 275 #if ( M68K_COLDFIRE_ARCH == 1 ) 276 276 #define m68k_flash_interrupts( _level ) \ 277 do { register u nsigned32_tmpsr = 0x0700; \277 do { register uint32_t _tmpsr = 0x0700; \ 278 278 asm volatile ( "move.w %2,%%sr\n\t" \ 279 279 "or.l %2,%1\n\t" \ … … 290 290 #define m68k_get_interrupt_level( _level ) \ 291 291 do { \ 292 register u nsigned32_tmpsr; \292 register uint32_t _tmpsr; \ 293 293 \ 294 294 asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ … … 298 298 #define m68k_set_interrupt_level( _newlevel ) \ 299 299 do { \ 300 register u nsigned32_tmpsr; \300 register uint32_t _tmpsr; \ 301 301 \ 302 302 asm volatile( "move.w %%sr,%0" : "=d" (_tmpsr)); \ … … 340 340 ) 341 341 { 342 u nsigned32byte1, byte2, byte3, byte4, swapped;342 uint32_t byte1, byte2, byte3, byte4, swapped; 343 343 344 344 byte4 = (value >> 24) & 0xff;
Note: See TracChangeset
for help on using the changeset viewer.