- Timestamp:
- 06/26/15 19:28:06 (9 years ago)
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doc/cpu_supplement/arm.t
r32005a72 rd84408a9 10 10 This chapter discusses the 11 11 @uref{http://en.wikipedia.org/wiki/ARM_architecture,ARM architecture} 12 dependencies in this port of RTEMS. The ARM family has a wide variety of13 implementations by a wide range of vendors. Consequently, there are many, many 14 CPU models within it. Currently the ARMv5 (and compatible) architecture 15 version as defined in the @code{ARMv5 Architecture Reference Manual} is supported by RTEMS.12 dependencies in this port of RTEMS. The ARMv4T (and compatible), ARMv7-A, 13 ARMv7-R and ARMv7-M architecture versions are supported by RTEMS. Processors 14 with a MMU use a static configuration which is set up during system start. SMP 15 is supported. 16 16 17 17 @subheading Architecture Documents … … 122 122 @section Interrupt Processing 123 123 124 The ARMv 5(and compatible) architecture has seven exception types:124 The ARMv4T (and compatible) architecture has seven exception types: 125 125 126 126 @itemize @bullet … … 140 140 operating system support for the FIQ it is not necessary to disable them during 141 141 critical sections of the system. 142 143 The ARMv7-M architecture has a completely different exception model. Here 144 interrupts are disabled with a write of 0x80 to the @code{basepri_max} 145 register. This means that all exceptions and interrupts with a priority value 146 of greater than or equal to 0x80 are disabled. Thus exceptions and interrupts 147 with a priority value of less than 0x80 are non-maskable with respect to the 148 operating system and therefore must not use operating system services. Several 149 support libraries of chip vendors implicitly shift the priority value somehow 150 before the value is written to the NVIC IPR register. This can easily lead to 151 confusion. 142 152 143 153 @subsection Interrupt Levels
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