Changeset d84408a9 in rtems


Ignore:
Timestamp:
Jun 26, 2015, 7:28:06 PM (4 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
cb2b8f0
Parents:
32005a72
Message:

doc: Update ARM documentation

File:
1 edited

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  • doc/cpu_supplement/arm.t

    r32005a72 rd84408a9  
    1010This chapter discusses the
    1111@uref{http://en.wikipedia.org/wiki/ARM_architecture,ARM architecture}
    12 dependencies in this port of RTEMS.  The ARM family has a wide variety of
    13 implementations by a wide range of vendors.  Consequently, there are many, many
    14 CPU models within it.  Currently the ARMv5 (and compatible) architecture
    15 version as defined in the @code{ARMv5 Architecture Reference Manual} is supported by RTEMS.
     12dependencies in this port of RTEMS.  The ARMv4T (and compatible), ARMv7-A,
     13ARMv7-R and ARMv7-M architecture versions are supported by RTEMS.  Processors
     14with a MMU use a static configuration which is set up during system start.  SMP
     15is supported.
    1616
    1717@subheading Architecture Documents
     
    122122@section Interrupt Processing
    123123
    124 The ARMv5 (and compatible) architecture has seven exception types:
     124The ARMv4T (and compatible) architecture has seven exception types:
    125125
    126126@itemize @bullet
     
    140140operating system support for the FIQ it is not necessary to disable them during
    141141critical sections of the system.
     142
     143The ARMv7-M architecture has a completely different exception model.  Here
     144interrupts are disabled with a write of 0x80 to the @code{basepri_max}
     145register.  This means that all exceptions and interrupts with a priority value
     146of greater than or equal to 0x80 are disabled.  Thus exceptions and interrupts
     147with a priority value of less than 0x80 are non-maskable with respect to the
     148operating system and therefore must not use operating system services.  Several
     149support libraries of chip vendors implicitly shift the priority value somehow
     150before the value is written to the NVIC IPR register.  This can easily lead to
     151confusion.
    142152
    143153@subsection Interrupt Levels
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