Changeset d7a2009a in rtems


Ignore:
Timestamp:
Dec 2, 2007, 9:35:49 PM (13 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.9, master
Children:
80d2e60
Parents:
a3ae5896
Message:

2007-12-02 Till Straumann <strauman@…>

  • shared/openpic/openpic.c shared/openpic/openpic.h, shared/irq/irq_init.c: added more parameters to openpic_init() so that more details of the configuration can be overridden/set from the BSP. Moved setup of the EPIC-specific EOI delay from BSP code into openpic_init() using the new 'epic_freq' parameter.
Location:
c/src/lib/libbsp/powerpc
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ChangeLog

    ra3ae5896 rd7a2009a  
     12007-12-02      Till Straumann <strauman@slac.stanford.edu>
     2
     3        * shared/openpic/openpic.c shared/openpic/openpic.h,
     4        shared/irq/irq_init.c: added more parameters to
     5        openpic_init() so that more details of the configuration
     6        can be overridden/set from the BSP. Moved setup of
     7        the EPIC-specific EOI delay from BSP code into openpic_init()
     8        using the new 'epic_freq' parameter.
     9
    1102007-12-02      Till Straumann <strauman@slac.stanford.edu>
    211        * shared/openpic/openpic.c, shared/openpic/openpic.h:
  • c/src/lib/libbsp/powerpc/shared/irq/irq_init.c

    ra3ae5896 rd7a2009a  
    271271  printk("Going to initialize EPIC interrupt controller (openpic compliant)\n");
    272272#endif
    273   openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses);
    274   /* Speed up the serial interface; if it is too slow then we might get spurious
    275    * interrupts:
    276    * After an ISR clears the interrupt condition at the source/device, the wire
    277    * remains asserted during the propagation delay introduced by the serial interface
    278    * (something really stupid). If the ISR returns while the wire is not released
    279    * yet, then a spurious interrupt happens.
    280    * The book says we should be careful if the serial clock is > 33MHz.
    281    * Empirically, it seems that running it at 33MHz is fast enough. Otherwise,
    282    * we should introduce a delay in openpic_eoi().
    283    * The maximal delay are 16 (serial) clock cycles. If the divisor is 8
    284    * [power-up default] then the lag is 2us [66MHz SDRAM clock; I assume this
    285    * is equal to the bus frequency].
    286    * FIXME: This should probably be a 8240-specific piece in 'openpic.c'
    287    */
    288   {
    289   uint32_t eicr_val, ratio;
    290     /* On the 8240 this is the EICR register */
    291     eicr_val = in_le32( &OpenPIC->Global.Global_Configuration1 ) & ~(7<<28);
    292     if ( (1<<27) & eicr_val ) {
    293       /* serial interface mode enabled */
    294 
    295       /* round to nearest integer:
    296        *   round(Bus_freq/33000000) = floor( 2*(Bus_freq/33e6) + 1 ) / 2
    297        */
    298       ratio   = BSP_bus_frequency / 16500000 + 1;
    299       ratio >>= 2; /* EICR value is half actual divisor */
    300       if ( 0==ratio )
    301         ratio = 1;
    302       out_le32(&OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28));
    303       /*  Delay in TB cycles (assuming TB runs at 1/4 of the bus frequency) */
    304       openpic_set_eoi_delay( 16 * (2*ratio) / 4 );
    305     }
    306   }
     273  /* EPIC sources don't start at the regular place; define appropriate offset
     274   * prior to initializing the PIC.
     275   */
     276  openpic_init(1, mvme2100_openpic_initpolarities, mvme2100_openpic_initsenses, 16, 16, BSP_bus_frequency);
    307277#else
    308278#ifdef TRACE_IRQ_INIT 
    309279  printk("Going to initialize raven interrupt controller (openpic compliant)\n");
    310280#endif
    311   openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses);
     281  openpic_init(1, mcp750_openpic_initpolarities, mcp750_openpic_initsenses, 0, 0, 0);
    312282#ifdef TRACE_IRQ_INIT 
    313283  printk("Going to initialize the PCI/ISA bridge IRQ related setting (VIA 82C586)\n");
  • c/src/lib/libbsp/powerpc/shared/openpic/openpic.c

    ra3ae5896 rd7a2009a  
    168168     */
    169169
    170 void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses)
     170void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses, int num_sources, int source_offset, unsigned long epic_freq)
    171171{
    172172    unsigned int t, i;
     
    238238           vendor, devid, device, stepping);
    239239
     240        /* Override if they desire */
     241        if ( num_sources ) {
     242                if ( NumSources != num_sources )
     243                        printk("Overriding NumSources (%i) from configuration with %i\n",
     244                                NumSources, num_sources);
     245                NumSources = num_sources;
     246        }
     247
     248        openpic_src_offst = source_offset;
     249
    240250    timerfreq = openpic_read(&OpenPIC->Global.Timer_Frequency);
    241251    printk("OpenPIC timer frequency is ");
     
    281291            openpic_disable_8259_pass_through();
    282292    }
     293        if ( epic_freq ) {
     294                /* Speed up the serial interface; if it is too slow then we might get spurious
     295                 * interrupts:
     296                 * After an ISR clears the interrupt condition at the source/device, the wire
     297                 * remains asserted during the propagation delay introduced by the serial interface
     298                 * (something really stupid). If the ISR returns while the wire is not released
     299                 * yet, then a spurious interrupt happens.
     300                 * The book says we should be careful if the serial clock is > 33MHz.
     301                 * Empirically, it seems that running it at 33MHz is fast enough. Otherwise,
     302                 * we should introduce a delay in openpic_eoi().
     303                 * The maximal delay are 16 (serial) clock cycles. If the divisor is 8
     304                 * [power-up default] then the lag is 2us [66MHz SDRAM clock; I assume this
     305                 * is equal to the bus frequency].
     306                 * FIXME: This should probably be a EPIC-specific piece in 'openpic.c'
     307                 *        Unfortunately, there is no easy way of figuring out if the
     308                 *        device is an EPIC or not.
     309                 */
     310                uint32_t eicr_val, ratio;
     311                /* On the 8240 this is the EICR register */
     312                eicr_val = in_le32( &OpenPIC->Global.Global_Configuration1 ) & ~(7<<28);
     313                if ( (1<<27) & eicr_val ) {
     314                        /* serial interface mode enabled */
     315
     316                        /* round to nearest integer:
     317                         *   round(Bus_freq/33000000) = floor( 2*(Bus_freq/33e6) + 1 ) / 2
     318                         */
     319                        ratio   = epic_freq / 16500000 + 1;
     320                        ratio >>= 2; /* EICR value is half actual divisor */
     321                        if ( 0==ratio )
     322                                ratio = 1;
     323                        out_le32(&OpenPIC->Global.Global_Configuration1, eicr_val | ((ratio &7) << 28));
     324                        /*  Delay in TB cycles (assuming TB runs at 1/4 of the bus frequency) */
     325                        openpic_set_eoi_delay( 16 * (2*ratio) / 4 );
     326                }
     327        }
    283328}
    284329
     
    339384unsigned rval = openpic_eoi_delay;
    340385    openpic_eoi_delay = tb_cycles;
    341         return rval;
    342 }
    343 
    344 int openpic_set_src_offst(int offset)
    345 {
    346 int rval = openpic_src_offst;
    347     openpic_src_offst = offset;
    348386        return rval;
    349387}
  • c/src/lib/libbsp/powerpc/shared/openpic/openpic.h

    ra3ae5896 rd7a2009a  
    316316 *      openpic_get_source_priority()
    317317 *      openpic_set_source_priority()
    318  *
    319  * The routines 'openpic_set_eoi_delay()' and 'openpic_set_src_offst()'
    320  * return the respective previous values of the affected parameters.
    321  *
    322  * NOTE: openpic_set_src_offst() MUST be called PRIOR to openpic_init()
     318 *    the desired source offset parameter is passed to openpic_init().
     319 *
     320 * The routine 'openpic_set_eoi_delay()' returns the previous/old
     321 * value of the delay parameter.
    323322 */
    324323extern unsigned openpic_set_eoi_delay(unsigned tb_cycles);
    325 extern      int openpic_set_src_offst(int offset);
    326324
    327325
    328326/* Global Operations */
    329 extern void openpic_init(int,unsigned char *, unsigned char *);
     327
     328/* num_sources: number of sources to use; if zero this value
     329 * is read from the device, if nonzero the value read from
     330 * the device is overridden.
     331 * 'polarities' and 'senses' are arrays defining the desired
     332 * polarities (active hi [nonzero]/lo [zero]) and
     333 * senses (level [nonzero]/edge [zero]).
     334 * Either of the two array pointers may be NULL resulting
     335 * in the driver choosing default values of: 'active low'
     336 * and 'level sensitive', respectively.
     337 * NOTE: if you do pass arrays then their size must either
     338 *       match the number of sources read from the device or
     339 *       that value must be overridden by specifying
     340 *       a non-zero 'num_sources' parameter.
     341 *
     342 * Nonzero 'epic_freq' activates the EOI delay if the EPIC is
     343 * configured in serial mode (driver assumes firmware performs initial
     344 * EPIC setup). The BSP must pass the clock frequency of the EPIC
     345 * serial interface here.
     346 */
     347extern void openpic_init(int main_pic, unsigned char *polarities, unsigned char *senses, int num_sources, int source_offset, unsigned long epic_freq);
     348
    330349extern void openpic_reset(void);
    331350extern void openpic_enable_8259_pass_through(void);
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