- Timestamp:
- 03/15/11 21:34:44 (13 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 67cf697
- Parents:
- 59eb125
- Location:
- c/src/lib/libbsp/m68k/uC5282
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/m68k/uC5282/ChangeLog
r59eb125 rd75792b 1 2011-03-15 Till Straumann <strauman@slac.stanford.edu> 2 3 * startup/bspstart.c: Fix clock code on qemu. Also ensure UART is 4 initialized early for printk. 5 1 6 2011-03-04 Till Straumann <strauman@slac.stanford.edu> 2 7 -
c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c
r59eb125 rd75792b 245 245 const char *clk_speed_str; 246 246 uint32_t clk_speed, mfd, rfd; 247 uint8_t byte; 248 249 /* 250 * Make sure UART TX is running - necessary for 251 * early printk to work. The firmware monitor 252 * usually enables this anyways but qemu doesn't! 253 */ 254 MCF5282_UART_UCR(CONSOLE_PORT) = MCF5282_UART_UCR_TX_ENABLED; 247 255 248 256 /* … … 335 343 if ( 0 == clk_speed ) { 336 344 printk("Using some heuristics to determine clock speed...\n"); 345 byte = MCF5282_CLOCK_SYNSR; 346 if ( 0 == byte ) { 347 printk("SYNSR == 0; assuming QEMU at 66MHz\n"); 348 BSP_pll_ref_clock = 8250000; 349 mfd = ( 0 << 8 ) | ( 2 << 12 ); 350 } else { 351 if ( 0xf8 != byte ) { 352 printk("FATAL ERROR: Unexpected SYNSR contents (0x%02x), can't proceed\n", byte); 353 bsp_sysReset(0); 354 } 355 mfd = MCF5282_CLOCK_SYNCR; 356 } 337 357 printk("Assuming %uHz PLL ref. clock\n", BSP_pll_ref_clock); 338 if ( 0xf8 != MCF5282_CLOCK_SYNSR ) {339 printk("FATAL ERROR: Unexpected SYNSR contents, can't proceed\n");340 bsp_sysReset(0);341 }342 mfd = MCF5282_CLOCK_SYNCR;343 358 rfd = (mfd >> 8) & 7; 344 359 mfd = (mfd >> 12) & 7;
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