Changeset d7196bf in rtems


Ignore:
Timestamp:
May 4, 2009, 8:06:43 PM (10 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.8
Children:
dc927fe
Parents:
e1be2b3
Message:

2009-04-20 Kate Feng <feng1@…>

1396/bsps

  • pci/pci.c : Updated it to be consistent with the original pci.c
  • written by Eric Valette. There is no change in its function.
  • irq/irq_init.c : set defaultIrq->next_handler to be 0
  • for BSP_SHARED_HANDLER_SUPPORT.
  • network/if_1GHz/if_wm.c : fixed some bugs in the 1GHz driver.
  • irq/BSP_irq.c : added supports for shared IRQ.
  • pci/pci_interface.c : Enabled PCI "Read", "Read Line", and "Read Multiple"
  • Agressive Prefetch to improve the performance of the PCI based
  • applications (e.g. 1GHz NIC).
  • irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value
  • register to monitor the cause of the level sensitive interrupts.
  • This unique solution solves various bugs in the 1GHz network drivers
  • Fixed bugs in compute_pic_masks_from_prio()
Location:
c/src/lib/libbsp/powerpc/mvme5500
Files:
1 added
28 edited
1 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/mvme5500/ChangeLog

    re1be2b3 rd7196bf  
     12009-04-20      Kate Feng <feng1@bnl.gov>
     2
     3        1396/bsps
     4        * pci/pci.c : Updated it to be consistent with the original pci.c
     5        * written by Eric Valette.  There is no change in its function.
     6        * irq/irq_init.c : set defaultIrq->next_handler to be 0
     7        * for BSP_SHARED_HANDLER_SUPPORT.
     8        * network/if_1GHz/if_wm.c : fixed some bugs in the 1GHz driver.
     9        * irq/BSP_irq.c : added supports for shared IRQ.
     10        * pci/pci_interface.c : Enabled PCI "Read", "Read Line", and
     11        "Read Multiple"
     12        *  Agressive Prefetch to improve the performance of the PCI based
     13        *  applications (e.g. 1GHz NIC).
     14        * irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value
     15        * register to monitor the cause of the level sensitive interrupts.
     16        * This unique solution solves various bugs in the 1GHz network drivers
     17        * Fixed bugs in compute_pic_masks_from_prio()
     18
     192009-04-20      Kate Feng <feng1@bnl.gov>
     20
     21        1396/bsps
     22        * pci/pci.c : Updated it to be consistent with the original pci.c
     23        * written by Eric Valette.  There is no change in its function.
     24        * irq/irq_init.c : set defaultIrq->next_handler to be 0
     25        * for BSP_SHARED_HANDLER_SUPPORT.
     26        * network/if_1GHz/if_wm.c : fixed some bugs in the 1GHz driver.
     27        * irq/BSP_irq.c : added supports for shared IRQ.
     28        * pci/pci_interface.c : Enabled PCI "Read", "Read Line", and
     29        "Read Multiple"
     30        *  Agressive Prefetch to improve the performance of the PCI based
     31        *  applications (e.g. 1GHz NIC).
     32        * irq/BSP_irq.c : Replaced the irq/irq.c, and used GT_GPP_Value
     33        * register to monitor the cause of the level sensitive interrupts.
     34        * This unique solution solves various bugs in the 1GHz network drivers
     35        * Fixed bugs in compute_pic_masks_from_prio()
     36       
    1372007-11-30      Joel Sherrill <joel.sherrill@OARcorp.com>
    238
     
    743
    844        * network/if_100MHz/GT64260eth.c: Add else.
    9 
     45   
    10462007-09-19      Kate Feng <feng1@bnl.gov>
    1147
  • c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.c

    re1be2b3 rd7196bf  
    11/* GT64260TWSI.c : Two-Wire Serial Interface (TWSI) support for the GT64260
    22 *
    3  * Copyright (c) 2004, Brookhaven National Laboratory and
    4  *                 Shuchen Kate Feng <feng1@bnl.gov>
     3 * Copyright (c) 2004, Brookhaven National Laboratory
     4 *               and Shuchen Kate Feng <feng1@bnl.gov>
     5 *               under the Deaprtment of Energy contract DE-AC02-98CH10886
    56 * All rights reserved.
    67 *
  • c/src/lib/libbsp/powerpc/mvme5500/GT64260/GT64260TWSI.h

    re1be2b3 rd7196bf  
    11/*
    22 *  $Id$
     3 *
     4 *  Copyright 2003  S. Kate Feng <feng1@bnl.gov>,
     5 *            NSLS, Brookhaven National Laboratory. All rights reserved.
     6 *            under the Deaprtment of Energy contract DE-AC02-98CH10886
    37 */
    48
  • c/src/lib/libbsp/powerpc/mvme5500/GT64260/MVME5500I2C.c

    re1be2b3 rd7196bf  
    33 * Copyright (c) 2003, 2004 Brookhaven National Laboratory
    44 * Author:    S. Kate Feng <feng1@bnl.gov>
     5 *            under the Deaprtment of Energy contract DE-AC02-98CH10886
    56 * All rights reserved.
    67 *
     
    3031* I2Cread_eeprom - read EEPROM VPD from the I2C
    3132*/
    32 int I2Cread_eeprom(unchar I2cBusAddr,u32 devA2A1A0,u32 AddrBytes,unchar *pBuff,u32 numBytes)
     33int I2Cread_eeprom(unchar I2cBusAddr,u32 devA2A1A0,u32 AddrBytes,void *pBuff,u32 numBytes)
    3334{
    3435  int status=0, lastByte=0;
     36  unchar *ptr=(unchar *) pBuff;
    3537
    3638  switch (AddrBytes) {
     
    8486     for ( ; numBytes > 0; numBytes-- ) {     
    8587       if ( numBytes == 1) lastByte=1;
    86        if (GT64260TWSIread(pBuff,lastByte) == -1) return (-1);
     88       if (GT64260TWSIread(ptr,lastByte) == -1) {
     89         printk("numBytes %d\n", numBytes);
     90          return (-1);
     91       }
    8792#ifdef I2C_DEBUG
    88        printk("%2x ", *pBuff);
     93       printk("%2x ", *ptr);
    8994       if ( (numBytes % 20)==0 ) printk("\n");
    9095#endif
    91        pBuff++;
     96       ptr++;   
    9297     }
    9398#ifdef I2C_DEBUG
  • c/src/lib/libbsp/powerpc/mvme5500/GT64260/VPD.h

    re1be2b3 rd7196bf  
    33 * (C) 2004, NSLS, Brookhaven National Laboratory,
    44 *           S. Kate Feng, <feng1@bnl.gov>
    5  *
     5 *  under the Deaprtment of Energy contract DE-AC02-98CH10886
    66 */
    77
    88extern unsigned char ConfVPD_buff[200];
    99
    10 #define VPD_ENET0_OFFSET  0x3c
    11 #define VPD_ENET1_OFFSET  0x45
     10typedef struct ConfVpdRec {
     11  char VendorId[8];
     12  char pad0[4];
     13  char BrdId[13];
     14  char pad1[2];
     15  char ManAssmNum[12];
     16  char pad2[2];
     17  char SerialNum[7];
     18  char pad3[2];
     19  /*  char IntClk[4];*/
     20  uint32_t IntClk;
     21  char pad4[3];
     22  /*char ExtClk[4];*/
     23  uint32_t ExtClk;
     24  char pad5[3];
     25  char EnetAddr0[7];
     26  char pad6[2];
     27  char EnetAddr1[7];
     28  char pad7[20];
     29} ConfVpdRec_t;
     30
     31#define VPD_BOARD_ID   8
     32#define VPD_ENET0_OFFSET  0x40
     33#define VPD_ENET1_OFFSET  0x49
     34
     35/*
     364D4F544F 524F4C41 0200010D 4D564D45  MOTOROLA....MVME
     3735353030 2D303136 33020C30 312D5733  5500-0163..01-W3
     3838323946 30314403 07373035 31383238  829F01D..7051828
     3905053B9A CA000106 0507F281 55010807  ..;.........U...
     40ethernet address
     41xxxxxxxx xxxxxxxx xxxxxxxx xxxx3701  ................
     4209043734 35350A04 87A6E98C 0B0C0089  ..7455..."=.....
     4300181002 02101000 78070B0C FFFFFFFF  ........x.......
     4410020210 10017805 0E0FFFFF FFFFFFFF  ......x.........
     45FFFFFF01 FF01FFFF FF0F0400 03000019  ................
     460A010107 02030000 000100FF FFFFFFFF  ................
     47FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF  ................
     48FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF  ................
     4900000000 00000000 00000000 00000000  ................
     5000000000 00000000 00000000 00000000  ................
     5100000000 00000000 00000000 00000000  ................
     5200000000 00000000 00000000 00000000  ................
     53
     54For the MVME5500 :
     55
     56Product Identifier                 : MVME5500-0163
     57Manufacturing Assembly Number      : 01-W3829F01D
     58Serial Number                      : 7051828
     59Internal Clock Speed (Hertz)       : 3B9ACA00 (&1000000000)
     60External Clock Speed (Hertz)       : 07F28155 (&133333333)
     61Ethernet Address                   : xx xx xx xx xx xx xx
     62Ethernet Address                   : xx xx xx xx xx xx xx
     63Microprocessor Type                : 7455
     64SROM/EEPROM CRC                    : D3223DD0 (&-752730672)
     65Flash0 Memory Configuration        : 00 89 00 18 10 02 02 10
     66                                   : 10 00 78 07
     67Flash1 Memory Configuration        : FF FF FF FF 10 02 02 10
     68                                   : 10 01 78 05
     69L2 Cache Configuration             : FF FF FF FF FF FF FF FF
     70                                   : FF 01 FF 01 FF FF FF
     71VPD Revision                       : 00 03 00 00
     72L3 Cache Configuration             : 01 01 07 02 03 00 00 00
     73                                   : 01 00
     74                                                                               
     75*/
  • c/src/lib/libbsp/powerpc/mvme5500/GT64260/gtreg.h

    re1be2b3 rd7196bf  
    191191#define GT_MPP_Control3                 0xf00c
    192192
    193 /* <skf> added */
     193/* <skf> added for GT64260 */
    194194#define GT_MPP_SerialPortMultiplex      0xf010
    195195
     
    791791
    792792/* Interrupt Controller - Interrupt Controller Registers */
     793/* <skf> added for GT64360 */
     794
     795#define GT64360_MAIN_INT_CAUSE_LO       0x004 /* read Only */
     796#define GT64360_MAIN_INT_CAUSE_HI       0x00c /* read Only */
     797#define GT64360_CPU0_INT_MASK_LO        0x014
     798#define GT64360_CPU0_INT_MASK_HI        0x01c
     799#define GT64360_CPU0_SEL_CAUSE          0x024 /* read Only */
     800
     801#define GT64360_CPU1_INT_MASK_LO        0x034
     802#define GT64360_CPU1_INT_MASK_HI        0x03c
     803#define GT64360_CPU1_SEL_CAUSE          0x044 /* read Only */
     804
    793805/* Section 25.2 : Table 734 <skf> */
    794806
    795 #define GT_MAIN_INT_CAUSE_LO    0xc18 /* read Only */
    796 #define GT_MAIN_INT_CAUSE_HI   0xc68 /* read Only */
    797 #define GT_CPU_INT_MASK_LO      0xc1c
    798 #define GT_CPU_INT_MASK_HI      0xc6c
    799 #define GT_CPU_SEL_CAUSE        0xc70 /* read Only */
     807#define GT64260_MAIN_INT_CAUSE_LO       0xc18 /* read Only */
     808#define GT64260_MAIN_INT_CAUSE_HI       0xc68 /* read Only */
     809#define GT64260_CPU_INT_MASK_LO         0xc1c
     810#define GT64260_CPU_INT_MASK_HI         0xc6c
     811#define GT64260_CPU_SEL_CAUSE   0xc70 /* read Only */
    800812#define GT_PCI0_INT_MASK_LO     0xc24
    801813#define GT_PCI0_INT_MASK_HI     0xc64
  • c/src/lib/libbsp/powerpc/mvme5500/Makefile.am

    re1be2b3 rd7196bf  
    3636    ../../powerpc/shared/startup/sbrk.c ../../shared/bootcard.c \
    3737    startup/bspclean.c ../../shared/bsplibc.c ../../shared/bsppost.c \
    38     ../../shared/gnatinstallhandler.c startup/reboot.c
     38    ../../shared/gnatinstallhandler.c startup/reboot.c \
     39    ../../powerpc/shared/startup/probeMemEnd.c
    3940startup_rel_CPPFLAGS = $(AM_CPPFLAGS)
    4041startup_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     
    6970
    7071noinst_PROGRAMS += irq.rel
    71 irq_rel_SOURCES = irq/irq_init.c irq/irq.c \
    72     ../../powerpc/shared/irq/irq_asm.S
     72irq_rel_SOURCES = irq/irq_init.c irq/BSP_irq.c \
     73   ../../powerpc/shared/irq/irq.c ../../powerpc/shared/irq/irq_asm.S
    7374irq_rel_CPPFLAGS = $(AM_CPPFLAGS)
    7475irq_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     
    109110network_CPPFLAGS = -D_KERNEL
    110111noinst_PROGRAMS += network.rel
    111 network_rel_SOURCES = network/if_100MHz/GT64260eth.c \
    112     network/if_1GHz/if_wm.c network/if_1GHz/pci_map.c
     112network_rel_SOURCES = network/if_100MHz/GT64260eth.c network/if_1GHz/if_wm.c \
     113        network/if_1GHz/pci_map.c
     114
    113115network_rel_CPPFLAGS = $(AM_CPPFLAGS) $(network_CPPFLAGS)
    114116network_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
     
    124126noinst_PROGRAMS += vme.rel
    125127vme_rel_SOURCES = ../../shared/vmeUniverse/vmeUniverse.c\
    126         ../shared/vme/vmeconfig.c ../../shared/vmeUniverse/bspVmeDmaList.c\
    127         ../shared/vme/vme_universe.c ../shared/vme/vme_universe_dma.c
     128        vme/vmeconfig.c ../../shared/vmeUniverse/bspVmeDmaList.c\
     129        ../shared/vme/vme_universe_dma.c
    128130
    129131vme_rel_CPPFLAGS = $(AM_CPPFLAGS)
  • c/src/lib/libbsp/powerpc/mvme5500/README

    re1be2b3 rd7196bf  
    11#
    2 #  $Id: README,v 1.3.1  Shuchen Kate Feng, NSLS, BNL (08/27/07)
     2#  $Id: README,v 1.4.1  Shuchen Kate Feng, NSLS, BNL (03/16/2009)
    33#
    44
     
    88reference README.irq
    99
    10 The BSP is built and tested on the 4.7.1 and 4.7.99.2 CVS RTEMS release.
     10The BSP is built and tested on the 4.8.0 RTEMS release.
    1111
    1212I believe in valuable real-time programming, where technical neatness,
  • c/src/lib/libbsp/powerpc/mvme5500/README.booting

    re1be2b3 rd7196bf  
    1 README.booting: written by S. Kate Feng <feng1@bnl.gov>, Aug. 28, 2007
     1README.booting: written by S. Kate Feng <feng1@bnl.gov>, March 16, 2009
    22
    3 The bootloader is adapted from Till Straumann's Generic Mini-loader,
    4 which he wrote originally for the SVGM powerpc board.
    5 The BSP is built and tested on the 4.7 CVS RTEMS release.
     3The BSP is built and tested on the  RTEMS 4.8.0 release.
    64
    75Booting requirement :
     
    1210   (Note : EPICS needs a NTP server).
    1311 
    14 2) Please copy the prebuilt RTEMS binary (e.g. misc/rtems5500-cexp.bin)
    15    and perhaps others (e.g. misc/st.sys) to the /tftpboot/epics/hostname/bin/
    16    directory or the TFTPBOOT one you specified in the 'tftpGet'
    17    command of the boot script (as shown in the following example).
    18 
    19 3) Example of the boot script setup carried out on the MOTLoad
     122) Example of the boot script setup carried out on the MOTLoad
    2013   command line :
    2114
     
    3326        sxx.xx.xx.xx is the server IP address)
    3427
    35 4) Other reference web sites for mvme5500 BSP:
    36 http://lansce.lanl.gov/EPICS/presentations/KateFeng%20RTEMS-mvme55001.ppt
     283) Other reference web sites for mvme5500 BSP:
    3729http://www.nsls.bnl.gov/facility/expsys/software/EPICS/
    38 http://www.nsls.bnl.gov/facility/expsys/software/EPICS/FAQ.txt
    3930
    40 5) When generating code (especially C++) for this system, one should
    41    use at least gcc-3.2 (preferrably a copy downloaded from the RTEMS
    42    site [snapshot area] )
    4331
    44 6) To reboot the RTEMS-MVME5500 (board reset), one can invoke the
     324) To reboot the RTEMS-MVME5500 (board reset), one can invoke the
    4533   rtemsReboot() command at Cexp> prompt.
    4634 
    47 7) Please reference http://www.slac.stanford.edu/~strauman/rtems
    48 for the source code and installation guidance of cexp, GeSys and
    49 other useful utilities such as telnet, nfs, and so on.
    50 
    51 8) To get started with RTEMS/EPICS and to build development
     355) To get started with RTEMS/EPICS and to build development
    5236tools and BSP, I would recommend one to reference
    5337http://www.aps.anl.gov/epics/base/RTEMS/tutorial/
  • c/src/lib/libbsp/powerpc/mvme5500/include/bsp.h

    re1be2b3 rd7196bf  
    88 *  http://www.rtems.com/license/LICENSE.
    99 *
    10  *  S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
     10 *  (C) S. Kate Feng 2003-2007 : Modified it to support the mvme5500 BSP.
     11 *
    1112 *
    1213 */
     
    2324#include <bsp/vectors.h>
    2425
    25 #include <bsp/bspMvme5500.h>
     26/* Board type */
     27typedef enum {
     28        undefined = 0,
     29        MVME5500,
     30        MVME6100
     31} BSP_BoardTypes;
     32
     33BSP_BoardTypes BSP_getBoardType();
     34
     35/* Board type */
     36typedef enum {
     37        Undefined,
     38        UNIVERSE2,
     39        TSI148,
     40} BSP_VMEchipTypes;
     41
     42BSP_VMEchipTypes BSP_getVMEchipType();
     43
     44/* The version of Discovery system controller */
     45
     46typedef enum {
     47        notdefined,
     48        GT64260A,
     49        GT64260B,           
     50        MV64360,
     51} DiscoveryChipVersion;
     52
     53DiscoveryChipVersion BSP_getDiscoveryChipVersion();
     54
     55#define _256M           0x10000000
     56#define _512M           0x20000000
     57
     58#define GT64x60_REG_BASE        0xf1000000  /* Base of GT64260 Reg Space */
     59#define GT64x60_REG_SPACE_SIZE  0x10000     /* 64Kb Internal Reg Space */
     60
     61#define GT64x60_DEV1_BASE       0xf1100000  /* Device bank1(chip select 1) base
     62                                             */
     63#define GT64260_DEV1_SIZE       0x00100000 /* Device bank size */
    2664
    2765/* fundamental addresses for this BSP (PREPxxx are from libcpu/io.h) */
    28 #define _IO_BASE GT64260_REG_BASE
     66#define _IO_BASE GT64x60_REG_BASE
     67
     68#define BSP_NVRAM_BASE_ADDR     0xf1110000
     69
     70#define BSP_RTC_INTA_REG        0x7ff0
     71#define BSP_RTC_SECOND          0x7ff2 
     72#define BSP_RTC_MINUTE          0x7ff3
     73#define BSP_RTC_HOUR            0x7ff4 
     74#define BSP_RTC_DATE            0x7ff5
     75#define BSP_RTC_INTERRUPTS      0x7ff6
     76#define BSP_RTC_WATCHDOG        0x7ff7
    2977
    3078/* PCI0 Domain I/O space */
     
    73121
    74122/* uart.c uses out_8 instead of outb  */
    75 #define BSP_UART_IOBASE_COM1    GT64260_DEV1_BASE + 0x20000
    76 #define BSP_UART_IOBASE_COM2    GT64260_DEV1_BASE + 0x21000
     123#define BSP_UART_IOBASE_COM1    GT64x60_DEV1_BASE + 0x20000
     124#define BSP_UART_IOBASE_COM2    GT64x60_DEV1_BASE + 0x21000
    77125
    78126#define BSP_CONSOLE_PORT                BSP_UART_COM1  /* console */
    79127#define BSP_UART_BAUD_BASE              115200
    80128
    81 /*
    82  * Vital Board data Start using DATA RESIDUAL
    83  */
    84129/*
    85130 * Total memory using RESIDUAL DATA
     
    121166#endif
    122167
    123 extern int
    124 RTEMS_BSP_NETWORK_DRIVER_ATTACH(/* struct rtems_bsdnet_ifconfig * */);
     168extern int RTEMS_BSP_NETWORK_DRIVER_ATTACH();
    125169
    126 /* As per Linux, This should be in the ppc/system.h */
     170#define gccMemBar() RTEMS_COMPILER_MEMORY_BARRIER()
    127171
     172static inline void lwmemBar()
     173{
     174    asm volatile("lwsync":::"memory");
     175}
     176
     177static inline void io_flush()
     178{
     179    asm volatile("isync":::"memory");
     180}
    128181static inline void memBar()
    129182{
    130183    asm volatile("sync":::"memory");
    131184}
    132 
    133185static inline void ioBar()
    134186{
    135     asm volatile("eieio");
     187    asm volatile("eieio":::"memory");
    136188}
    137189
  • c/src/lib/libbsp/powerpc/mvme5500/irq/BSP_irq.c

    re1be2b3 rd7196bf  
    1 /*  irq.c
     1/*  BSP_irq.c
    22 *
    33 *  This file contains the implementation of the function described in irq.h
     
    99 *  http://www.OARcorp.com/rtems/license.html.
    1010 *
    11  *  Acknowledgement May 2004 : to Till Straumann <strauman@slac.stanford.edu>
    12  *  for some inputs.
     11 *  Acknowledgement to Till Straumann <strauman@slac.stanford.edu>
     12 *  for some inputs in May 2004.
    1313 *
    1414 *  Copyright 2003, 2004, 2005, 2007  Shuchen Kate Feng <feng1@bnl.gov>,
    15  *                  NSLS,Brookhaven National Laboratory
    16  *  1) Modified and added support for the MVME5500 board.
    17  *  2) The implementation of picIsrTable[] is an original work by the
     15 *            NSLS, Brookhaven National Laboratory. All rights reserved.
     16 *
     17 *  1) Used GT_GPP_Value register instead of the GT_GPP_Interrupt_Cause
     18 *     register to monitor the cause of the level sensitive interrupts.
     19 *     (Copyright : NDA item)
     20 *  2) The implementation of picPrioTable[] is an original work by the
    1821 *     author to optimize the software IRQ priority scheduling because
    1922 *     Discovery controller does not provide H/W IRQ priority schedule.
     
    2124 *     highest/higher priority IRQ, if pendig.
    2225 *  3) _CPU_MSR_SET() needs RTEMS_COMPILER_MEMORY_BARRIER()
    23  *
    24  */
    25  
     26 *
     27 */
     28
     29#include <stdio.h> 
    2630#include <rtems/system.h>
    2731#include <bsp.h>
     
    4044#define HI_INT_CAUSE 0x40000000
    4145
    42 #define MAX_IRQ_LOOP 30
    43 
    44 #define EDGE_TRIGGER
     46#define MAX_IRQ_LOOP 20
    4547
    4648#define _MSR_GET( _mask) \
     
    7779/*
    7880 * location used to store initial tables used for interrupt
    79  * management.
    80  */
    81 static rtems_irq_global_settings*       internal_config;
    82 static rtems_irq_connect_data*          rtems_hdl_tbl;
     81 * management.BSP copy of the configuration
     82 */
     83static rtems_irq_global_settings        BSP_config;
    8384
    8485static volatile unsigned  *BSP_irqMask_reg[3];
    8586static volatile unsigned  *BSP_irqCause_reg[3];
    8687static volatile unsigned  BSP_irqMask_cache[3]={0,0,0};
    87 
    88 
    89 static int picIsrTblPtr=0;
     88static unsigned int BSP_GPP_mask[4]= { 1<<24, 1<<25, 1<<26, 1<<27};
     89
     90static int picPrioTblPtr=0;
    9091static unsigned int GPPIrqInTbl=0;
    9192static unsigned long long MainIrqInTbl=0;
    9293
    9394/*
    94  * The software developers are forbidden to setup picIsrTable[],
     95 * The software developers are forbidden to setup picPrioTable[],
    9596 * as it is a powerful engine for the BSP to find the pending
    9697 * highest priority IRQ at run time.  It ensures the fastest/faster
    9798 * interrupt service to the highest/higher priority IRQ, if pendig.
    9899 *
    99  * The picIsrTable[96] is updated dynamically at run time
     100 * The picPrioTable[96] is updated dynamically at run time
    100101 * based on the priority levels set at BSPirqPrioTable[96],
    101  * while the BSP_enable_pic_irq(), and BSP_disable_pic_irq()
     102 * while the BSP_enable_irq_at_pic(), and BSP_disable_irq_at_pic()
    102103 * commands are invoked.
    103104 *
    104  * The picIsrTable[96] lists the enabled CPU main and GPP external interrupt
     105 * The picPrioTable[96] lists the enabled CPU main and GPP external interrupt
    105106 * numbers [0 (lowest)- 95 (highest)] starting from the highest priority
    106107 * one to the lowest priority one. The highest priority interrupt is
    107  * located at picIsrTable[0], and the lowest priority interrupt is located
    108  * at picIsrTable[picIsrTblPtr-1].
    109  *
    110  *
    111  */
    112 /* BitNums for Main Interrupt Lo/High Cause and GPP, -1 means invalid bit */
    113 static unsigned int picIsrTable[BSP_PIC_IRQ_NUMBER]={ 
     108 * located at picPrioTable[0], and the lowest priority interrupt is located
     109 * at picPrioTable[picPrioTblPtr-1].
     110 *
     111 *
     112 */
     113#define DynamicIsrTable
     114#ifdef DynamicIsrTable
     115/* BitNums for Main Interrupt Lo/High Cause, -1 means invalid bit */
     116static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={
    114117     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    115118     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     
    122125     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
    123126     -1, -1, -1, -1, -1, -1 };
    124 
     127#else
     128static unsigned int picPrioTable[BSP_PIC_IRQ_NUMBER]={
     129     80, 84, 76, 77, 32, -1, -1, -1, -1, -1,
     130     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     131     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     132     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     133     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     134     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     135     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     136     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     137     -1, -1, -1, -1, -1, -1, -1, -1, -1, -1,
     138     -1, -1, -1, -1, -1, -1 };
     139#endif
    125140
    126141/*
     
    144159}
    145160
    146 static inline unsigned int divIrq32(unsigned irq)
    147 {
    148   return(irq/32);
    149 }
    150 
    151 static inline unsigned int modIrq32(unsigned irq)
    152 {
    153    return(irq%32);
    154 }
    155 
    156161/*
    157162 * ------------------------ RTEMS Irq helper functions ----------------
     
    159164 
    160165/*
    161  * Caution : this function assumes the variable "internal_config"
     166 * Caution : this function assumes the variable "BSP_config"
    162167 * is already set and that the tables it contains are still valid
    163168 * and accessible.
     
    165170static void compute_pic_masks_from_prio()
    166171{
    167   int i,j, k;
     172  int i,j, k, isGppMain;
    168173  unsigned long long irq_prio_mask=0;
    169174
     
    181186
    182187        irq_prio_mask =0;
     188        isGppMain =1;
    183189        break;
    184190      default :
     191        isGppMain =0;
    185192        irq_prio_mask = (unsigned long long) (1LLU << i);
    186193        break;
    187194    }
    188    
    189     if (irq_prio_mask) {
     195    if ( isGppMain) continue;
    190196    for (j = 0; j <BSP_MAIN_IRQ_NUMBER; j++) {
    191197        /*
     
    193199         * or <Till Straumann> a equal priority.
    194200         */
    195         if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])
     201        if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j])
    196202           irq_prio_mask |= (unsigned long long)(1LLU << j);
    197203    }
     
    200206    BSP_irq_prio_mask_tbl[0][i] = irq_prio_mask & 0xffffffff;
    201207    BSP_irq_prio_mask_tbl[1][i] = (irq_prio_mask>>32) & 0xffffffff;
    202 #ifdef DEBUG
     208#if 0
    203209    printk("irq_mask_prio_tbl[%d]:0x%8x%8x\n",i,BSP_irq_prio_mask_tbl[1][i],
    204210           BSP_irq_prio_mask_tbl[0][i]);
     
    208214    /* Compute for the GPP priority interrupt mask */
    209215    for (j=BSP_GPP_IRQ_LOWEST_OFFSET; j <BSP_PROCESSOR_IRQ_LOWEST_OFFSET; j++) {     
    210       if (internal_config->irqPrioTbl [i] >= internal_config->irqPrioTbl [j])
     216      if (BSP_config.irqPrioTbl [i] >= BSP_config.irqPrioTbl [j])
    211217           BSP_irq_prio_mask_tbl[2][i] |= 1 << (j-BSP_GPP_IRQ_LOWEST_OFFSET);
    212218    }
    213     }
    214   }
    215 }
    216 
     219#if 0
     220    printk("GPPirq_mask_prio_tbl[%d]:0x%8x\n",i,BSP_irq_prio_mask_tbl[2][i]);
     221#endif
     222  }
     223}
    217224
    218225static void UpdateMainIrqTbl(int irqNum)
    219226{
    220   int i=0, j, shifted=0;
     227  int i=0, j, k, shifted=0;
    221228
    222229  switch (irqNum) {
     
    238245        (!(( 1 << (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET)) & GPPIrqInTbl))))
    239246  {
    240       while ( picIsrTable[i]!=-1) {
    241         if (internal_config->irqPrioTbl[irqNum]>internal_config->irqPrioTbl[picIsrTable[i]]) {
     247      while ( picPrioTable[i]!=-1) {
     248        if (BSP_config.irqPrioTbl[irqNum]>BSP_config.irqPrioTbl[picPrioTable[i]]) {
    242249          /* all other lower priority entries shifted right */
    243           for (j=picIsrTblPtr;j>i; j--)
    244               picIsrTable[j]=picIsrTable[j-1];
    245           picIsrTable[i]=irqNum;
     250          for (j=picPrioTblPtr;j>i; j--) {
     251              picPrioTable[j]=picPrioTable[j-1];
     252          }
     253          picPrioTable[i]=irqNum;
    246254          shifted=1;
    247255          break;
     
    249257       i++;
    250258     }
    251      if (!shifted) picIsrTable[picIsrTblPtr]=irqNum;
     259     if (!shifted) picPrioTable[picPrioTblPtr] =irqNum;
     260
    252261     if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
    253262        GPPIrqInTbl |= (1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));
    254263     else     
    255264        MainIrqInTbl |= (unsigned long long)(1LLU << irqNum);
    256      picIsrTblPtr++;
     265     picPrioTblPtr++;
    257266  }
    258267#ifdef SHOW_MORE_INIT_SETTINGS
     
    268277static void CleanMainIrqTbl(int irqNum)
    269278{
    270   int i, j;
     279  int i, j, k;
    271280
    272281  switch (irqNum) {
     
    284293  { /* If entry in table*/
    285294     for (i=0; i<64; i++) {
    286        if (picIsrTable[i]==irqNum) {/*remove it from the entry */
     295       if (picPrioTable[i]==irqNum) {/*remove it from the entry */
    287296          /* all other lower priority entries shifted left */
    288           for (j=i;j<picIsrTblPtr; j++)
    289               picIsrTable[j]=picIsrTable[j+1];
     297          for (j=i;j<picPrioTblPtr; j++) {
     298              picPrioTable[j]=picPrioTable[j+1];
     299          }
    290300          if (irqNum >BSP_MICH_IRQ_MAX_OFFSET)
    291301            GPPIrqInTbl &= ~(1<< (irqNum-BSP_GPP_IRQ_LOWEST_OFFSET));
    292302          else     
    293303            MainIrqInTbl &= ~(1LLU << irqNum);
    294           picIsrTblPtr--;
     304          picPrioTblPtr--;
    295305          break;
    296306       }
     
    299309}
    300310
    301 void BSP_enable_pic_irq(const rtems_irq_number irqNum)
     311void BSP_enable_irq_at_pic(const rtems_irq_number irqNum)
    302312{
    303313  unsigned bitNum, regNum;
    304314  unsigned int level;
    305315
    306   bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
    307   regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
     316  bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32;
     317  regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5;
    308318
    309319  rtems_interrupt_disable(level);
    310320
     321#ifdef DynamicIsrTable
    311322  UpdateMainIrqTbl((int) irqNum);
     323#endif
    312324  BSP_irqMask_cache[regNum] |= (1 << bitNum);
    313325
     
    315327  while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
    316328
     329  memBar();
    317330  rtems_interrupt_enable(level);
    318331}
    319332
    320 void BSP_disable_pic_irq(const rtems_irq_number irqNum)
     333void BSP_disable_irq_at_pic(const rtems_irq_number irqNum)
    321334{
    322335  unsigned bitNum, regNum;
    323336  unsigned int level;
    324337
    325   bitNum = modIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
    326   regNum = divIrq32(((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET);
     338  bitNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)%32;
     339  regNum = (((unsigned int)irqNum) - BSP_MICL_IRQ_LOWEST_OFFSET)>>5;
    327340
    328341  rtems_interrupt_disable(level);
    329342
     343#ifdef DynamicIsrTable
    330344  CleanMainIrqTbl((int) irqNum);
     345#endif
    331346  BSP_irqMask_cache[regNum] &=  ~(1 << bitNum);
    332347
    333348  out_le32(BSP_irqMask_reg[regNum], BSP_irqMask_cache[regNum]);
    334349  while (in_le32(BSP_irqMask_reg[regNum]) != BSP_irqMask_cache[regNum]);
    335 
     350  memBar();
    336351  rtems_interrupt_enable(level);
    337352}
    338353
    339 int BSP_setup_the_pic()  /* adapt the same name as shared/irq */
     354/* Use shared/irq : 2008 */
     355int BSP_setup_the_pic(rtems_irq_global_settings* config) 
    340356{
    341357    int i;
    342358
    343     /* Get ready for discovery BSP */
    344     BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_LO);
    345     BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_CPU_INT_MASK_HI);
    346     BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Mask);
    347 
    348     BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_LO);
    349     BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64260_REG_BASE + GT_MAIN_INT_CAUSE_HI);
    350     BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64260_REG_BASE + GT_GPP_Interrupt_Cause);
    351 
    352 #ifdef EDGE_TRIGGER
     359    BSP_config = *config;
     360
     361    switch(BSP_getDiscoveryChipVersion()) {
     362    case GT64260B:
     363    case GT64260A:
     364      /* Get ready for discovery BSP */
     365      BSP_irqMask_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_LO);
     366      BSP_irqMask_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_CPU_INT_MASK_HI);
     367      BSP_irqCause_reg[0]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_LO);
     368      BSP_irqCause_reg[1]= (volatile unsigned int *) (GT64x60_REG_BASE + GT64260_MAIN_INT_CAUSE_HI);
     369      break;
     370    default:
     371      printk("Not supported by this BSP yet\n");
     372      return(0);
     373      break;
     374    }
     375
     376    BSP_irqMask_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Interrupt_Mask);
     377    BSP_irqCause_reg[2]= (volatile unsigned int *) (GT64x60_REG_BASE + GT_GPP_Value);
    353378
    354379    /* Page 401, Table 598:
    355380     * Comm Unit Arbiter Control register :
    356381     * bit 10:GPP interrupts as level sensitive(1) or edge sensitive(0).
    357      * We set the GPP interrupts to be edge sensitive.
    358      * MOTload default is set as level sensitive(1).
     382     * MOTload default is set as level sensitive(1). Set it agin to make sure.
    359383     */
    360     outl((inl(GT_CommUnitArb_Ctrl)& (~(1<<10))), GT_CommUnitArb_Ctrl);
    361 #else
    362384    outl((inl(GT_CommUnitArb_Ctrl)| (1<<10)), GT_CommUnitArb_Ctrl);
    363 #endif
    364385
    365386#if 0
     
    375396#endif
    376397
    377     /* Initialize the interrupt related GT64260 registers */
     398    /* Initialize the interrupt related registers */
    378399    for (i=0; i<3; i++) {
    379400      out_le32(BSP_irqCause_reg[i], 0);
     
    399420     */
    400421    for (i=BSP_MICL_IRQ_LOWEST_OFFSET; i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET ; i++) {
    401       if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    402         BSP_enable_pic_irq(i);
    403         rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
     422      if ( BSP_config.irqHdlTbl[i].hdl != BSP_config.defaultEntry.hdl) {
     423        BSP_enable_irq_at_pic(i);
     424        BSP_config.irqHdlTbl[i].on(&BSP_config.irqHdlTbl[i]);
    404425      }
    405426      else {
    406         rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    407         BSP_disable_pic_irq(i);
     427        BSP_config.irqHdlTbl[i].off(&BSP_config.irqHdlTbl[i]);
     428        BSP_disable_irq_at_pic(i);
    408429      }
    409430    }
    410 
     431    for (i= BSP_MAIN_GPP7_0_IRQ; i < BSP_MAIN_GPP31_24_IRQ; i++)
     432      BSP_enable_irq_at_pic(i);
     433   
    411434    return(1);
    412435}
    413 
    414 /*
    415  * This function check that the value given for the irq line
    416  * is valid.
    417  */
    418 
    419 static int isValidInterrupt(int irq)
    420 {
    421   if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET))
    422     return 0;
    423   return 1;
    424 }
    425 
    426 /*
    427  * ------------------------ RTEMS Single Irq Handler Mngt Routines ----------------
    428  */
    429 
    430 int BSP_install_rtems_irq_handler  (const rtems_irq_connect_data* irq)
    431 {
    432     unsigned int level;
    433  
    434     if (!isValidInterrupt(irq->name)) {
    435       printk("Invalid interrupt vector %d\n",irq->name);
    436       return 0;
    437     }
    438     /*
    439      * Check if default handler is actually connected. If not issue an error.
    440      * You must first get the current handler via i386_get_current_idt_entry
    441      * and then disconnect it using i386_delete_idt_entry.
    442      * RATIONALE : to always have the same transition by forcing the user
    443      * to get the previous handler before accepting to disconnect.
    444      */
    445     rtems_interrupt_disable(level);
    446     if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
    447       rtems_interrupt_enable(level);
    448       printk("IRQ vector %d already connected\n",irq->name);
    449       return 0;
    450     }
    451 
    452     /*
    453      * store the data provided by user
    454      */
    455     rtems_hdl_tbl[irq->name] = *irq;
    456 #ifdef BSP_SHARED_HANDLER_SUPPORT
    457     rtems_hdl_tbl[irq->name].next_handler = (void *)-1;
    458 #endif
    459 
    460     if (is_pic_irq(irq->name)) {
    461       /*
    462        * Enable PIC  irq : Main Interrupt Cause Low and High & GPP external
    463        */
    464 #ifdef DEBUG_IRQ
    465       printk("PIC irq %d\n",irq->name);
    466 #endif
    467       BSP_enable_pic_irq(irq->name);
    468     }
    469     else {
    470       if (is_processor_irq(irq->name)) {
    471          /*
    472           * Enable exception at processor level
    473           */
    474 
    475        }
    476     }
    477     /*
    478      * Enable interrupt on device
    479      */
    480     irq->on(irq);
    481    
    482     rtems_interrupt_enable(level);
    483 
    484     return 1;
    485 }
    486 
    487 
    488 int BSP_get_current_rtems_irq_handler   (rtems_irq_connect_data* irq)
    489 {
    490      if (!isValidInterrupt(irq->name)) {
    491       return 0;
    492      }
    493      *irq = rtems_hdl_tbl[irq->name];
    494      return 1;
    495 }
    496 
    497 int BSP_remove_rtems_irq_handler  (const rtems_irq_connect_data* irq)
    498 {
    499     unsigned int level;
    500  
    501     if (!isValidInterrupt(irq->name)) {
    502       return 0;
    503     }
    504     /*
    505      * Check if default handler is actually connected. If not issue an error.
    506      * You must first get the current handler via i386_get_current_idt_entry
    507      * and then disconnect it using i386_delete_idt_entry.
    508      * RATIONALE : to always have the same transition by forcing the user
    509      * to get the previous handler before accepting to disconnect.
    510      */
    511     if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
    512       return 0;
    513     }
    514     rtems_interrupt_disable(level);
    515 
    516     /*
    517      * disable PIC interrupt
    518      */
    519     if (is_pic_irq(irq->name))
    520       BSP_disable_pic_irq(irq->name);
    521     else {
    522       if (is_processor_irq(irq->name)) {
    523          /*
    524           * disable exception at processor level
    525           */
    526        }
    527     }   
    528 
    529     /*
    530      * Disable interrupt on device
    531      */
    532     irq->off(irq);
    533 
    534     /*
    535      * restore the default irq value
    536      */
    537     rtems_hdl_tbl[irq->name] = default_rtems_entry;
    538 
    539 
    540     rtems_interrupt_enable(level);
    541 
    542     return 1;
    543 }
    544 
    545 /*
    546  * ------------------------ RTEMS Global Irq Handler Mngt Routines ----------------
    547  */
    548 
    549 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
    550 {
    551     unsigned int level;
    552     int i;
    553 
    554    /*
    555     * Store various code accelerators
    556     */
    557     internal_config             = config;
    558     default_rtems_entry         = config->defaultEntry;
    559     rtems_hdl_tbl               = config->irqHdlTbl;
    560 
    561     rtems_interrupt_disable(level);
    562 
    563     if ( !BSP_setup_the_pic() ) {
    564        printk("PIC setup failed; leaving IRQs OFF\n");
    565        return 0;
    566     }
    567 
    568     for (i= BSP_MAIN_GPP7_0_IRQ; i <= BSP_MAIN_GPP31_24_IRQ; i++)
    569       BSP_enable_pic_irq(i);
    570 
    571     rtems_interrupt_enable(level);
    572     return 1;
    573 }
    574 
    575 int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
    576 {
    577     *config = internal_config;
    578     return 0;
    579 }   
    580436
    581437/*
     
    587443  register unsigned msr, new_msr;
    588444  unsigned long irqCause[3]={0, 0,0};
    589   register unsigned long selectCause;
    590445  unsigned oldMask[3]={0,0,0};
    591   register unsigned i=0, j, irq=0, bitmask=0, group=0;
     446  int loop=0, wloop=0, i=0, j;
     447  register irq=0, group=0;
    592448
    593449  if (excNum == ASM_DEC_VECTOR) {
     
    596452    _MSR_SET(new_msr);
    597453   
    598     rtems_hdl_tbl[BSP_DECREMENTER].hdl(rtems_hdl_tbl[BSP_DECREMENTER].handle);
    599 
     454    BSP_config.irqHdlTbl[BSP_DECREMENTER].hdl(BSP_config.irqHdlTbl[BSP_DECREMENTER].handle);
    600455    _MSR_SET(msr);
    601456    return;
     
    604459
    605460  for (j=0; j<3; j++ ) oldMask[j] = BSP_irqMask_cache[j];
    606 
    607   if ((selectCause= in_le32((volatile unsigned *)0xf1000c70)) & HI_INT_CAUSE ){
    608     irqCause[1] = (selectCause & BSP_irqMask_cache[1]);
    609     irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
    610   }
    611   else {
    612     irqCause[0] = (selectCause & BSP_irqMask_cache[0]);
    613     if ((irqCause[1] =(in_le32((volatile unsigned *)0xf1000c68)&BSP_irqMask_cache[1])))
    614        irqCause[2] = in_le32(BSP_irqCause_reg[2]) & BSP_irqMask_cache[2];
    615   }
    616  
    617   while ((irq = picIsrTable[i++])!=-1)
    618   {
    619     if (irqCause[group=(irq/32)] && (irqCause[group]&(bitmask=(1<<(irq % 32))))) {
     461  for (j=0; j<3; j++) irqCause[j] = in_le32(BSP_irqCause_reg[j]) & in_le32(BSP_irqMask_reg[j]);
     462
     463  while (((irq = picPrioTable[i++])!=-1)&& (loop++ < MAX_IRQ_LOOP))
     464  {   
     465    if (irqCause[group= irq/32] & ( 1<<(irq % 32))) {
    620466      for (j=0; j<3; j++)
    621467        BSP_irqMask_cache[j] &= (~ BSP_irq_prio_mask_tbl[j][irq]);
    622468
    623       RTEMS_COMPILER_MEMORY_BARRIER();
    624       out_le32((volatile unsigned *)0xf1000c1c, BSP_irqMask_cache[0]);
    625       out_le32((volatile unsigned *)0xf1000c6c, BSP_irqMask_cache[1]);
    626       out_le32((volatile unsigned *)0xf100f10c, BSP_irqMask_cache[2]);
    627       in_le32((volatile unsigned *)0xf100f10c);
    628 
    629 #ifdef EDGE_TRIGGER
    630       if (irq > BSP_MICH_IRQ_MAX_OFFSET)
    631          out_le32(BSP_irqCause_reg[2], ~bitmask);/* Till Straumann: Ack the edge triggered GPP IRQ */
    632 #endif
    633 
     469      out_le32(BSP_irqMask_reg[0], BSP_irqMask_cache[0]);
     470      out_le32(BSP_irqMask_reg[1], BSP_irqMask_cache[1]);
     471      out_le32(BSP_irqMask_reg[2], BSP_irqMask_cache[2]);
     472      in_le32(BSP_irqMask_reg[2]);
     473     
    634474      _MSR_GET(msr);
    635475      new_msr = msr | MSR_EE;
    636476      _MSR_SET(new_msr);
    637       rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
     477      /* handler */
     478#ifdef BSP_SHARED_HANDLER_SUPPORT
     479      {
     480         rtems_irq_connect_data* vchain;
     481         for( vchain = &BSP_config.irqHdlTbl[irq];
     482            (vchain->hdl != BSP_config.defaultEntry.hdl && ((int)vchain != -1) );
     483            vchain = (rtems_irq_connect_data*)vchain->next_handler )
     484         {
     485            vchain->hdl(vchain->handle);
     486         }
     487      }
     488#else
     489      BSP_config.irqHdlTbl[irq].hdl(BSP_config.irqHdlTbl[irq].handle);
     490#endif
    638491      _MSR_SET(msr);
    639      
     492
    640493      for (j=0; j<3; j++ ) BSP_irqMask_cache[j] = oldMask[j];
    641       break;
     494 
     495      out_le32(BSP_irqMask_reg[0], oldMask[0]);
     496      out_le32(BSP_irqMask_reg[1], oldMask[1]);
     497      out_le32(BSP_irqMask_reg[2], oldMask[2]);
     498      in_le32(BSP_irqMask_reg[2]);
    642499    }
    643500  }
    644 
    645   out_le32((volatile unsigned *)0xf1000c1c, oldMask[0]);
    646   out_le32((volatile unsigned *)0xf1000c6c, oldMask[1]);
    647   out_le32((volatile unsigned *)0xf100f10c, oldMask[2]);
    648   in_le32((volatile unsigned *)0xf100f10c);
    649 }
    650 
    651 void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    652 {
    653   /*
    654    * Process pending signals that have not already been
    655    * processed by _Thread_Displatch. This happens quite
    656    * unfrequently : the ISR must have posted an action
    657    * to the current running thread.
    658    */
    659   if ( _Thread_Do_post_task_switch_extension ||
    660        _Thread_Executing->do_post_task_switch_extension ) {
    661     _Thread_Executing->do_post_task_switch_extension = FALSE;
    662     _API_extensions_Run_postswitch();
    663   }
    664   /*
    665    * I plan to process other thread related events here.
    666    * This will include DEBUG session requested from keyboard...
    667    */
    668501}
    669502
     
    673506  int i;
    674507
    675   printk("picIsrTable[12]={");
     508  printf("picPrioTable[12]={ irq# :");
    676509  for (i=0; i<12; i++)
    677     printk("%d,", picIsrTable[i]);
    678   printk("}\n");
    679 
    680   printk("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
    681 }
     510    printf("%d,", picPrioTable[i]);
     511  printf("}\n");
     512
     513  printf("GPPIrqInTbl: 0x%x :\n", GPPIrqInTbl);
     514}
  • c/src/lib/libbsp/powerpc/mvme5500/irq/irq.h

    re1be2b3 rd7196bf  
    3030#define LIBBSP_POWERPC_MVME5500_IRQ_IRQ_H
    3131
    32 /*#define BSP_SHARED_HANDLER_SUPPORT      1*/
     32#define BSP_SHARED_HANDLER_SUPPORT      1
     33
    3334#include <rtems/irq.h>
    3435
     
    8586   * Summary
    8687   */
    87 #define BSP_IRQ_NUMBER                  (BSP_MISC_IRQ_MAX_OFFSET + 1)
     88#define BSP_IRQ_NUMBER                  (BSP_PIC_IRQ_NUMBER + BSP_PROCESSOR_IRQ_NUMBER)
    8889#define BSP_MAIN_IRQ_NUMBER             (64)
    8990#define BSP_PIC_IRQ_NUMBER              (96)
    90 #define BSP_LOWEST_OFFSET               (BSP_MICL_IRQ_LOWEST_OFFSET)
    91 #define BSP_MAX_OFFSET                  (BSP_MISC_IRQ_MAX_OFFSET)
     91#define BSP_LOWEST_OFFSET               (0)
     92#define BSP_MAX_OFFSET                  (BSP_LOWEST_OFFSET + BSP_IRQ_NUMBER - 1)
    9293
    9394  /* Main CPU interrupt cause (Low) */
  • c/src/lib/libbsp/powerpc/mvme5500/irq/irq_init.c

    re1be2b3 rd7196bf  
    4242static rtems_irq_connect_data           rtemsIrq[BSP_IRQ_NUMBER];
    4343static rtems_irq_global_settings        initial_config;
     44
     45#ifdef BSP_SHARED_HANDLER_SUPPORT
     46static rtems_irq_connect_data           defaultIrq = {
     47  /* vectorIdex,  hdl       ,handle  , on       , off      , isOn      ,next_handler, */
     48  0,              nop_func  , NULL   , nop_func , nop_func , not_connected, 0
     49};
     50#else
    4451static rtems_irq_connect_data           defaultIrq = {
    4552  /* vectorIdex,         hdl      , handle      , on            , off           , isOn */
    4653  0,                     nop_func  , NULL       , nop_func      , nop_func      , not_connected
    4754};
     55#endif
    4856
    4957rtems_irq_prio BSPirqPrioTable[BSP_PIC_IRQ_NUMBER]={
     
    141149#endif     
    142150
    143   /*
    144    * We must connect the raw irq handler for the two
    145    * expected interrupt sources : decrementer and external interrupts.
    146    */
    147   vectorDesc.exceptIndex        = ASM_DEC_VECTOR;
    148   vectorDesc.hdl.vector = ASM_DEC_VECTOR;
    149   vectorDesc.hdl.raw_hdl        = decrementer_exception_vector_prolog_code;
    150   vectorDesc.hdl.raw_hdl_size   = (unsigned) decrementer_exception_vector_prolog_code_size;
    151   vectorDesc.on         = nop_func;
    152   vectorDesc.off                = nop_func;
    153   vectorDesc.isOn               = connected;
    154   if (!ppc_set_exception (&vectorDesc)) {
    155       BSP_panic("Unable to initialize RTEMS decrementer raw exception\n");
    156   }
    157   vectorDesc.exceptIndex        = ASM_EXT_VECTOR;
    158   vectorDesc.hdl.vector = ASM_EXT_VECTOR;
    159   vectorDesc.hdl.raw_hdl        = external_exception_vector_prolog_code;
    160   vectorDesc.hdl.raw_hdl_size   = (unsigned) external_exception_vector_prolog_code_size;
    161   if (!ppc_set_exception (&vectorDesc)) {
    162       BSP_panic("Unable to initialize RTEMS external raw exception\n");
    163     }
    164151#ifdef TRACE_IRQ_INIT 
    165152  printk("RTEMS IRQ management is now operationnal\n");
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.c

    re1be2b3 rd7196bf  
    33 * Copyright (c) 2003,2004 Brookhaven National  Laboratory
    44 *               S. Kate Feng <feng1@bnl.gov>
    5  * All rights reserved
     5 *               All rights reserved
    66 *
    77 * Acknowledgements:
    88 * netBSD : Copyright (c) 2002 Allegro Networks, Inc., Wasabi Systems, Inc.
    99 * Marvell : NDA document for the discovery system controller
    10  * The author referenced two RTEMS network drivers of other NICs.
    11  * rtems : 1) dec21140.c, a network driver for for TULIP based Ethernet Controller
    12  *            (C) 1999 Emmanuel Raguet. raguet@crf.canon.fr
    13  *
    14  *         2) yellowfin.c, a network driver for the SVGM5 BSP.
    15  *           Stanford Linear Accelerator Center, Till Straumann
    1610 *
    1711 * Some notes from the author, S. Kate Feng :
    1812 *
    1913 * 1) Mvme5500 uses Eth0 (controller 0) of the GT64260 to implement
    20  *    the 10/100 BaseT Ethernet with PCI Master Data Byte Swap\
    21  *    control.
     14 *    the 10/100 BaseT Ethernet with PCI Master Data Byte Swap control.
    2215 * 2) Implemented hardware snoop instead of software snoop
    2316 *    to ensure SDRAM cache coherency. (Copyright : NDA item)
     
    5649#include <net/if.h>
    5750#include <net/if_dl.h>
     51#include <net/ethernet.h>
    5852#include <netinet/in.h>
    5953#include <netinet/if_ether.h>
     
    111105#define ET_MINLEN 64            /* minimum message length */
    112106
    113 static int GTeth_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data);
     107static int GTeth_ifioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data);
    114108static void GTeth_ifstart (struct ifnet *);
    115109static void GTeth_ifchange(struct GTeth_softc *sc);
     
    170164
    171165  if ( (!cause) || (cause & 0x803d00)) {
    172        sc->intr_errsts[sc->intr_err_ptr2++]=cause;
    173        sc->intr_err_ptr2 %=INTR_ERR_SIZE;  /* Till Straumann */
     166       sc->if_errsts[sc->if_err_ptr2]=cause;
     167       if ( (++sc->if_err_ptr2) == IF_ERR_BUFSZE) sc->if_err_ptr2=0; /* Till Straumann */
    174168       events |= ERR_EVENT;
    175169  } 
     
    202196        BSP_MAIN_ETH0_IRQ,
    203197        (rtems_irq_hdl) GT64260eth_isr,
    204         NULL,
     198        (rtems_irq_hdl_param) NULL,
    205199        (rtems_irq_enable) GT64260eth_irq_on,
    206200        (rtems_irq_disable) GT64260eth_irq_off,
     
    331325#endif
    332326
    333   sc->intr_err_ptr1=0;
    334   sc->intr_err_ptr2=0;
    335   for (i=0; i< INTR_ERR_SIZE; i++) sc->intr_errsts[i]=0;
     327  sc->if_err_ptr1=0;
     328  sc->if_err_ptr2=0;
     329  for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0;
    336330
    337331  /* initialize the hardware (we are holding the network semaphore at this point) */
     
    339333
    340334  /* launch network daemon */
    341 
    342   /* NOTE:
    343    * in ss-20011025 (and later) any task created by 'bsdnet_newproc' is
    344    * wrapped by code which acquires the network semaphore...
    345    */
    346    sc->daemonTid = rtems_bsdnet_newproc(GT_ETH_TASK_NAME,4096,GT64260eth_daemon,arg);
     335  sc->daemonTid = rtems_bsdnet_newproc(GT_ETH_TASK_NAME,4096,GT64260eth_daemon,arg);
    347336
    348337  /* Tell the world that we're running */
     
    365354  unit = rtems_bsdnet_parse_driver_name(config, &name);
    366355  if (unit < 0) return 0;
    367  
    368   printk("\nEthernet driver name %s unit %d \n",name, unit);
    369   printk("(c) 2004, Brookhaven National Lab. <feng1@bnl.gov> (RTEMS/mvme5500 port)\n");
     356  if ( !strncmp((const char *)name,"autoz",5))
     357     memcpy(name,"gtMHz",5);
     358           
     359  printk("\nAttaching GT64260 built-in 10/100 MHz NIC%d\n", unit);
     360  printk("RTEMS-mvme5500 BSP Copyright (c) 2004, Brookhaven National Lab., Shuchen Kate Feng\n");
    370361
    371362  /* Make certain elements e.g. descriptor lists are aligned. */
     
    389380   * by config
    390381   */
    391   if (config->hardware_address) {
    392      memcpy(hwaddr, config->hardware_address, ETHER_ADDR_LEN);
    393   } else {
    394     printk("Read EEPROM ");
    395      for (i = 0; i < 6; i++)
    396        hwaddr[i] = ConfVPD_buff[VPD_ENET0_OFFSET+i];
    397   }
     382  if (config->hardware_address)
     383     memcpy((void *)sc->arpcom.ac_enaddr,(const void *) config->hardware_address, ETHER_ADDR_LEN);
     384  else
     385    memcpy((void *)sc->arpcom.ac_enaddr, (const void *) &ConfVPD_buff[VPD_ENET0_OFFSET], ETHER_ADDR_LEN);
    398386
    399387#ifdef GT_DEBUG
    400388  printk("using MAC addr from device:");
    401   for (i = 0; i < ETHER_ADDR_LEN; i++) printk("%x:", hwaddr[i]);
     389  for (i = 0; i < ETHER_ADDR_LEN; i++) printk("%x:", sc->arpcom.ac_enaddr[i]);
    402390  printk("\n");
    403391#endif
    404 
    405   memcpy(sc->arpcom.ac_enaddr, hwaddr, ETHER_ADDR_LEN);
    406392
    407393  ifp = &sc->arpcom.ac_if;
     
    411397  sc->sc_intrmask = inl(ETH0_EIMR) | ETH_IR_MIIPhySTC;
    412398
     399#ifdef GT_DEBUG
    413400  printk("address %s\n", ether_sprintf(hwaddr));
    414 
    415 #ifdef GT_DEBUG
    416401  printk(", pcr %x, pcxr %x ", sc->sc_pcr, sc->sc_pcxr);
    417402#endif
     
    512497  struct ifnet *ifp = &sc->arpcom.ac_if;
    513498
    514 #if 0
    515499  printf("       Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts);
    516500  printf("     Receive Packets:%-8lu\n", ifp->if_ipackets);
     
    521505  printf("         Active Rxqs:%-8u\n",  sc->rxq_active);
    522506  printf("       Tx Interrupts:%-8lu\n", sc->stats.txInterrupts);
    523 #endif
    524   printf("Multi-BuffTx Packets:%-8lu\n", sc->stats.txMultiBuffPacket);
    525   printf("Multi-BuffTx max len:%-8lu\n", sc->stats.txMultiMaxLen);
    526   printf("SingleBuffTx max len:%-8lu\n", sc->stats.txSinglMaxLen);
    527   printf("Multi-BuffTx maxloop:%-8lu\n", sc->stats.txMultiMaxLoop);
    528   printf("Tx buffer max len   :%-8lu\n", sc->stats.txBuffMaxLen);
    529 #if 0
    530507  printf("   Transmitt Packets:%-8lu\n", ifp->if_opackets);
    531508  printf("   Transmitt  errors:%-8lu\n", ifp->if_oerrors);
    532509  printf("    Tx/Rx collisions:%-8lu\n", ifp->if_collisions);
    533510  printf("         Active Txqs:%-8u\n", sc->txq_nactive);
    534 #endif
    535511}
    536512
     
    540516}
    541517
    542 static int GTeth_ifioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
     518static int GTeth_ifioctl(struct ifnet *ifp, ioctl_command_t cmd, caddr_t data)
    543519{
    544520  struct GTeth_softc *sc = ifp->if_softc;
     
    586562           if (ifp->if_flags & IFF_RUNNING)
    587563              GTeth_ifchange(sc);
    588            else
     564           else
    589565              error = 0;
    590566       }
     
    863839}
    864840
     841#if 0
    865842static int txq_high_limit(struct GTeth_softc *sc)
    866843{
     
    902879  return 0;
    903880}
     881#endif
    904882
    905883static int GT64260eth_sendpacket(struct GTeth_softc *sc,struct mbuf *m)
     
    917895  intrmask = sc->sc_intrmask;
    918896
    919   if ( !(m->m_next)) {/* single buffer packet */
     897  if ( !(m->m_next)) /* single buffer packet */
    920898    sc->txq_mbuf[index]= m;
    921     sc->stats.txSinglMaxLen= MAX(m->m_len, sc->stats.txSinglMaxLen);
    922   }
    923899  else /* multiple mbufs in this packet */
    924900  {
     
    948924#endif
    949925      len += mtp->m_len;
    950       sc->stats.txBuffMaxLen=MAX(mtp->m_len,sc->stats.txBuffMaxLen);
    951926    }
    952     sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop);
    953927#if 0
    954928    printk("\n");
     
    958932    m_freem(m);
    959933    sc->txq_mbuf[index] = m = mdest;
    960     sc->stats.txMultiBuffPacket++;
    961     sc->stats.txMultiMaxLen= MAX(m->m_len, sc->stats.txMultiMaxLen);
    962934  }
    963935  if (m->m_len < ET_MINLEN) m->m_len = ET_MINLEN;
     
    11381110}
    11391111
    1140 /* TOCHECK : Should it be about rx or tx ? */
    11411112static void GTeth_ifchange(struct GTeth_softc *sc)
    11421113{
    11431114  if (GTeth_debug>0) printk("GTeth_ifchange(");
    11441115  if (GTeth_debug>5) printk("(pcr=%#x,imr=%#x)",inl(ETH0_EPCR),inl(ETH0_EIMR));
    1145   /*  printk("SIOCADDMULTI (SIOCDELMULTI): is it about rx or tx ?\n");*/
    11461116  outl(sc->sc_pcr | ETH_EPCR_EN, ETH0_EPCR);
    11471117  outl(sc->sc_intrmask, ETH0_EIMR);
     
    14461416}
    14471417
     1418#ifdef GT64260eth_DEBUG
    14481419static void GT64260eth_error(struct GTeth_softc *sc)
    14491420{
    14501421  struct ifnet          *ifp = &sc->arpcom.ac_if;
    1451   unsigned int          intr_status= sc->intr_errsts[sc->intr_err_ptr1];
     1422  unsigned int          intr_status= sc->if_errsts[sc->if_err_ptr1];
    14521423
    14531424  /* read and reset the status; because this is written
     
    14721443    printk("%s%d: Ghost interrupt ?\n",ifp->if_name,
    14731444           ifp->if_unit);
    1474   sc->intr_errsts[sc->intr_err_ptr1++]=0; 
    1475   sc->intr_err_ptr1 %= INTR_ERR_SIZE;  /* Till Straumann */
    1476 }
    1477 
     1445  sc->if_errsts[sc->if_err_ptr1]=0; 
     1446  if ( (++sc->if_err_ptr1) == IF_ERR_BUFSZE) sc->if_err_ptr1=0; /* Till Straumann */
     1447}
     1448#endif
    14781449
    14791450/* The daemon does all of the work; RX, TX and cleaning up buffers/descriptors */
     
    14841455  struct mbuf   *m=0;
    14851456  struct ifnet  *ifp=&sc->arpcom.ac_if;
    1486 
    1487 #if 0   
    1488   /* see comments in GT64260eth_init(); in newer versions of
    1489    * rtems, we hold the network semaphore at this point
    1490    */
    1491   rtems_semaphore_release(sc->daemonSync);
    1492 #endif
    14931457
    14941458  /* NOTE: our creator possibly holds the bsdnet_semaphore.
     
    15491513
    15501514       /* Log errors and other uncommon events. */
    1551        if (events & ERR_EVENT) GT64260eth_error(sc);
     1515#ifdef GT64260eth_DEBUG
     1516          if (events & ERR_EVENT) GT64260eth_error(sc);
     1517#endif
    15521518  } /* end for(;;) { rtems_bsdnet_event_receive() .....*/
    15531519
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_100MHz/GT64260eth.h

    re1be2b3 rd7196bf  
    55 *
    66 * RTEMS/Mvme5500 port 2004  by S. Kate Feng, <feng1@bnl.gov>,
     7 * under the Deaprtment of Energy contract DE-AC02-98CH10886
    78 * All rights reserved.
    89 *
     
    5152#define HASH_TABLE_SIZE 16
    5253#define HASH_DRAM_SIZE  HASH_TABLE_SIZE*1024  /* size of DRAM for hash table */
    53 #define INTR_ERR_SIZE   16
     54#define IF_ERR_BUFSZE   16
    5455               
    5556enum GTeth_txprio {
     
    7172  struct mbuf* rxq_mbuf[RX_RING_SIZE];  /* receive buffer memory */
    7273  struct GTeth_softc *next_module;
    73   volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* capture the right intr_status */
    74   unsigned int intr_err_ptr1;   /* ptr used in GTeth_error() */
    75   unsigned int intr_err_ptr2;   /* ptr used in ISR */
     74  volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* capture the right intr_status */
     75  unsigned int if_err_ptr1;   /* ptr used in GTeth_error() */
     76  unsigned int if_err_ptr2;   /* ptr used in ISR */
    7677  struct ifqueue txq_pendq;     /* these are ready to go to the GT */
    7778  unsigned int txq_pending;
     
    126127  struct {
    127128    volatile unsigned long       rxInterrupts;
    128 
    129129    volatile unsigned long       txInterrupts;
    130     unsigned long       txMultiBuffPacket;
    131     unsigned long       txMultiMaxLen;
    132     unsigned long       txSinglMaxLen;
    133     unsigned long       txMultiMaxLoop;
    134     unsigned long       txBuffMaxLen;
    135130    unsigned long       length_errors;
    136131    unsigned long       frame_errors;
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wm.c

    re1be2b3 rd7196bf  
    11/*
    2  * Copyright (c) 2004,2005 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov>
     2 * Copyright (c) 2004,2005, 2008 RTEMS/Mvme5500 port by S. Kate Feng <feng1@bnl.gov>
     3 *      under the Deaprtment of Energy contract DE-AC02-98CH10886
    34 *      Brookhaven National Laboratory, All rights reserved
    45 *
     
    2627 *    to WB region", MII mode (PHY) instead of TBI mode.
    2728 * 6) We currently only use 32-bit (instead of 64-bit) DMA addressing.
    28  * 7) Support for checksum offloading and TCP segmentation offload will
    29  *    be available for releasing in 2008, upon request, if I still believe.
     29 * 7) Implementation for Jumbo Frame and TCP checksum is not yet completed.
    3030 *   
    3131 */
     
    3434
    3535#define INET
     36
     37/*#define RTEMS_ETHERMTU_JUMBO*/
    3638
    3739#include <rtems.h>
    3840#include <rtems/bspIo.h>      /* printk */
     41
    3942#include <stdio.h>            /* printf for statistics */
    4043#include <string.h>
     
    6568#include <netinet/in.h>
    6669#include <netinet/if_ether.h>
     70#include <net/ethernet.h>
    6771
    6872#ifdef INET
     
    8387#define SOFTC_ALIGN        4095
    8488
    85 #define INTR_ERR_SIZE        16
     89#define IF_ERR_BUFSZE        16
    8690
    8791/*#define WM_DEBUG*/
     
    110114#define ALL_EVENTS (KILL_EVENT|START_TRANSMIT_EVENT|RX_EVENT|TX_EVENT|ERR_EVENT|INIT_EVENT)
    111115
    112 
    113 #define NTXDESC                 128
     116/* <skf> used 64 in 4.8.0, TOD; try 4096 */
     117#define NTXDESC                 256
    114118#define NTXDESC_MASK            (NTXDESC - 1)
    115119#define WM_NEXTTX(x)            (((x) + 1) & NTXDESC_MASK)
    116120
    117 #define NRXDESC                 64
     121#define NRXDESC                 256
    118122#define NRXDESC_MASK            (NRXDESC - 1)
    119123#define WM_NEXTRX(x)            (((x) + 1) & NRXDESC_MASK)
     
    124128#define WM_CDRXOFF(x)   WM_CDOFF(sc_rxdescs[(x)])
    125129
    126 #define TXQ_HiLmt_OFF 64
     130#define TXQ_HiLmt_OFF 32
    127131
    128132static uint32_t TxDescCmd;
     133static unsigned BSP_1GHz_membase;
    129134
    130135/*
     
    137142        struct mbuf *rxs_mbuf[NRXDESC];        /* receive buffer memory */
    138143        struct wm_softc *next_module;
    139         volatile unsigned int intr_errsts[INTR_ERR_SIZE]; /* intr_status */
    140         unsigned int intr_err_ptr1;     /* ptr used in i82544EI_error() */
    141         unsigned int intr_err_ptr2;     /* ptr used in ISR */
     144        volatile unsigned int if_errsts[IF_ERR_BUFSZE]; /* intr_status */
     145        unsigned int if_err_ptr1;     /* ptr used in i82544EI_error() */
     146        unsigned int if_err_ptr2;     /* ptr used in ISR */
    142147        int txs_firstdesc;              /* first descriptor in packet */
    143148        int txs_lastdesc;               /* last descriptor in packet */
     
    169174        int     sc_rxdiscard;
    170175        int     sc_rxlen;
     176
    171177        uint32_t sc_ctrl;               /* prototype CTRL register */
    172 #if 0
    173178        uint32_t sc_ctrl_ext;           /* prototype CTRL_EXT register */
    174 #endif
     179
    175180        uint32_t sc_icr;                /* prototype interrupt bits */
    176181        uint32_t sc_tctl;               /* prototype TCTL register */
     
    178183        uint32_t sc_tipg;               /* prototype TIPG register */
    179184        uint32_t sc_fcrtl;              /* prototype FCRTL register */
     185        uint32_t sc_pba;                /* prototype PBA register */
    180186
    181187        int sc_mchash_type;             /* multicast filter offset */
     
    185191          volatile unsigned long     rxInterrupts;
    186192          volatile unsigned long     txInterrupts;
    187           unsigned long     txMultiBuffPacket;
    188           unsigned long     txMultiMaxLen;
    189           unsigned long     txSinglMaxLen;
    190           unsigned long     txMultiMaxLoop;
    191           unsigned long     txBuffMaxLen;
    192193          unsigned long     linkInterrupts;
    193194          unsigned long     length_errors;
     
    225226
    226227static void i82544EI_ifstart(struct ifnet *ifp);
    227 static int  wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data);
     228static int  wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data);
    228229static void i82544EI_ifinit(void *arg);
    229230static void wm_stop(struct ifnet *ifp, int disable);
     231static void wm_gmii_mediainit(struct wm_softc *sc);
    230232
    231233static void wm_rxdrain(struct wm_softc *sc);
     
    234236static void i82544EI_daemon(void *arg);
    235237static void wm_set_filter(struct wm_softc *sc);
    236 
    237 static void i82544EI_isr();
     238static void i82544EI_rx(struct wm_softc *sc);
     239static void i82544EI_isr(rtems_irq_hdl_param handle);
    238240static void i82544EI_sendpacket(struct wm_softc *sc, struct mbuf *m);
    239241extern int  pci_mem_find(), pci_io_find(), pci_get_capability();
    240 extern char * ether_sprintf1();
    241242
    242243static void i82544EI_irq_on(const rtems_irq_connect_data *irq)
     
    270271        BSP_GPP_82544_IRQ,
    271272        (rtems_irq_hdl) i82544EI_isr,
     273        (rtems_irq_hdl_param) NULL,
    272274        (rtems_irq_enable) i82544EI_irq_on,
    273275        (rtems_irq_disable) i82544EI_irq_off,
     
    289291  unit = rtems_bsdnet_parse_driver_name(config, &name);
    290292  if (unit < 0) return 0;
    291  
    292   printk("\nEthernet driver name %s unit %d \n",name, unit);
    293   printk("Copyright (c) 2004,2005 S. Kate Feng <feng1@bnl.gov> (RTEMS/mvme5500 port)\n");
     293
     294  if ( !strncmp((const char *)name,"autoz",5))
     295     memcpy(name,"gtGHz",5);
     296         
     297  printk("\nAttaching MVME5500 1GHz NIC%d\n", unit);
     298  printk("RTEMS-mvme5500 BSP Copyright (c) 2004,2005,2008 Shuchen Kate Feng \n");
    294299
    295300  /* Make sure certain elements e.g. descriptor lists are aligned.*/
     
    317322     rtems_panic("i82544EI: unable to map memory space\n");
    318323
     324  printk("Memory base addr 0x%x\n", sc->sc_membase);
     325  BSP_1GHz_membase= sc->sc_membase;
     326
    319327#ifdef WM_DEBUG
    320328  printk("Memory base addr 0x%x\n", sc->sc_membase);
     
    323331
    324332
    325   sc->sc_ctrl |=CSR_READ(sc,WMREG_CTRL); 
     333  sc->sc_ctrl=CSR_READ(sc,WMREG_CTRL); 
    326334  /*
    327335   * Determine a few things about the bus we're connected to.
     
    361369  enaddr[5] = myea[2] >> 8;
    362370
    363 
    364371  memcpy(sc->arpcom.ac_enaddr, enaddr, ETHER_ADDR_LEN);
    365372#ifdef WM_DEBUG
    366373  printk("%s: Ethernet address %s\n", sc->dv_xname,
    367             ether_sprintf1(enaddr));
     374            ether_sprintf(enaddr));
    368375#endif
    369376
     
    395402  CSR_WRITE(sc,WMREG_CTRL_EXT, sc->sc_ctrl_ext);
    396403#endif
     404
     405  /*
     406   * Determine if we're TBI or GMII mode, and initialize the
     407   * media structures accordingly.
     408   */
     409  if ((CSR_READ(sc, WMREG_STATUS) & STATUS_TBIMODE) != 0) {
     410    /* 1000BASE-X : fiber  (TBI mode)
     411       wm_tbi_mediainit(sc); */
     412  } else {   /* 1000BASE-T : copper (internal PHY mode), for the mvme5500 */
     413           wm_gmii_mediainit(sc);
     414  } 
    397415
    398416  ifp = &sc->arpcom.ac_if;
     
    402420  ifp->if_softc = sc;
    403421  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
     422#ifdef RTEMS_ETHERMTU_JUMBO
     423  sc->arpcom.ec_capabilities |= ETHERCAP_JUMBO_MTU;
     424  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU_JUMBO;
     425#else
    404426  ifp->if_mtu = config->mtu ? config->mtu : ETHERMTU;
     427#endif
     428#ifdef RTEMS_CKSUM_OFFLOAD
     429  /* < skf> The following is really not related to jumbo frame
     430  sc->arpcom.ec_capabilities |= ETHERCAP_VLAN_MTU;*/
     431  ifp->if_capabilities |= IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx |
     432                    IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx |
     433                    IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx |
     434                    IFCAP_CSUM_TCPv6_Tx | IFCAP_CSUM_UDPv6_Tx |
     435                    IFCAP_TSOv4;  /* TCP segmentation offload. */
     436#endif
     437
    405438  ifp->if_ioctl = wm_ioctl;
    406439  ifp->if_start = i82544EI_ifstart;
     
    417450     rtems_panic("i82544EI: semaphore creation failed");
    418451
    419   sc->next_module = root_i82544EI_dev;
     452  i82544IrqData.handle= (rtems_irq_hdl_param) sc;
     453  /* sc->next_module = root_i82544EI_dev;*/
    420454  root_i82544EI_dev = sc;
    421455
     
    431465
    432466/*
     467 * wm_reset:
     468 *
     469 *      Reset the i82544 chip.
     470 */
     471static void wm_reset(struct wm_softc *sc)
     472{
     473  int i;
     474
     475  sc->sc_pba = sc->arpcom.ac_if.if_mtu > 8192 ? PBA_40K : PBA_48K;
     476  CSR_WRITE(sc, WMREG_PBA, sc->sc_pba);
     477
     478  /* device reset */
     479  CSR_WRITE(sc, WMREG_CTRL, CTRL_RST);
     480  rtems_bsp_delay(10000);
     481
     482  for (i = 0; i < 1000; i++) {
     483      if ((CSR_READ(sc, WMREG_CTRL) & CTRL_RST) == 0)
     484        break;
     485      rtems_bsp_delay(20);
     486  }
     487  if (CSR_READ(sc, WMREG_CTRL) & CTRL_RST)
     488      printk("Intel 82544 1GHz reset failed to complete\n");
     489
     490  sc->sc_ctrl_ext = CSR_READ(sc,WMREG_CTRL_EXT);
     491  sc->sc_ctrl_ext |= CTRL_EXT_EE_RST;
     492  CSR_WRITE(sc, WMREG_CTRL_EXT, sc->sc_ctrl_ext); 
     493  CSR_READ(sc, WMREG_STATUS);
     494  /* Wait for EEPROM reload */
     495  rtems_bsp_delay(2000);
     496  sc->sc_ctrl= CSR_READ(sc, WMREG_CTRL);
     497}
     498
     499/*
    433500 * i82544EI_ifstart:            [ifnet interface function]
    434501 *
     
    462529  struct ifnet *ifp = &sc->arpcom.ac_if;
    463530
    464   printf("       Rx Interrupts:%-8u\n", sc->stats.rxInterrupts);
     531  printf("    Ghost Interrupts:%-8lu\n", sc->stats.ghostInterrupts);
     532  printf("       Rx Interrupts:%-8lu\n", sc->stats.rxInterrupts);
    465533  printf("     Receive Packets:%-8u\n", CSR_READ(sc,WMREG_GPRC));
    466   printf("     Receive Overrun:%-8u\n", sc->stats.rxOvrRunInterrupts);
     534  printf("     Receive Overrun:%-8lu\n", sc->stats.rxOvrRunInterrupts);
    467535  printf("     Receive  errors:%-8u\n", CSR_READ(sc,WMREG_RXERRC));
    468   printf("   Rx sequence error:%-8u\n", sc->stats.rxSeqErr);
    469   printf("      Rx /C/ ordered:%-8u\n", sc->stats.rxC_ordered);
     536  printf("   Rx sequence error:%-8lu\n", sc->stats.rxSeqErr);
     537  printf("      Rx /C/ ordered:%-8lu\n", sc->stats.rxC_ordered);
    470538  printf("    Rx Length Errors:%-8u\n", CSR_READ(sc,WMREG_RLEC));
    471   printf("       Tx Interrupts:%-8u\n", sc->stats.txInterrupts);
    472 #if 0
    473   printf("Multi-BuffTx Packets:%-8u\n", sc->stats.txMultiBuffPacket);
    474   printf("Multi-BuffTx max len:%-8u\n", sc->stats.txMultiMaxLen);
    475   printf("SingleBuffTx max len:%-8u\n", sc->stats.txSinglMaxLen);
    476   printf("Multi-BuffTx maxloop:%-8u\n", sc->stats.txMultiMaxLoop);
    477   printf("Tx buffer max len   :%-8u\n", sc->stats.txBuffMaxLen);
    478 #endif
     539  printf("       Tx Interrupts:%-8lu\n", sc->stats.txInterrupts);
    479540  printf("   Transmitt Packets:%-8u\n", CSR_READ(sc,WMREG_GPTC));
    480   printf("   Transmitt  errors:%-8u\n", ifp->if_oerrors);
    481   printf("         Active Txqs:%-8u\n", sc->txq_nactive);
     541  printf("   Transmitt  errors:%-8lu\n", ifp->if_oerrors);
     542  printf("         Active Txqs:%-8lu\n", sc->txq_nactive);
    482543  printf("          collisions:%-8u\n", CSR_READ(sc,WMREG_COLC));
    483544  printf("          Crc Errors:%-8u\n", CSR_READ(sc,WMREG_CRCERRS));
    484   printf("  Link Status Change:%-8u\n", sc->stats.linkStatusChng);
     545  printf("  Link Status Change:%-8lu\n", sc->stats.linkStatusChng);
    485546}
    486547
     
    490551 *      Handle control requests from the operator.
    491552 */
    492 static int wm_ioctl(struct ifnet *ifp, u_long cmd,uint32_t data)
     553static int wm_ioctl(struct ifnet *ifp, ioctl_command_t cmd,caddr_t data)
    493554{
    494555  struct wm_softc *sc = ifp->if_softc;
     
    522583 *      Interrupt service routine.
    523584 */
    524 static void i82544EI_isr()
    525 {
    526   volatile struct wm_softc *sc = root_i82544EI_dev;
     585static void i82544EI_isr(rtems_irq_hdl_param handle)
     586{
     587  volatile struct wm_softc *sc = (struct wm_softc *) handle;
    527588  uint32_t icr;
    528589  rtems_event_set  events=0;
     
    548609  }
    549610  if (icr & ICR_RXSEQ) /* framing error */ {
    550      sc->intr_errsts[sc->intr_err_ptr2++]=icr;
    551      sc->intr_err_ptr2 %=INTR_ERR_SIZE; /* Till Straumann */
     611     sc->if_errsts[sc->if_err_ptr2]=icr;
     612     if ((++sc->if_err_ptr2)==IF_ERR_BUFSZE) sc->if_err_ptr2=0;/* Till Straumann */
    552613     events |= ERR_EVENT;
    553614     sc->stats.rxSeqErr++;
     
    607668         */
    608669        if ( ((y=(len+mtp->m_len)) > sizeof(union mcluster))) {
    609           printk(">2048, use next descriptor\n");
     670          printk(" >%d, use next descriptor\n", sizeof(union mcluster));
    610671          break;
    611672        }
     
    613674        pt += mtp->m_len;
    614675        len += mtp->m_len;
    615 #if 0
    616         sc->stats.txSinglMaxLen= MAX(mtp->m_len, sc->stats.txSinglMaxLen);
    617 #endif
    618676      } /* end for loop */
    619677      mdest->m_len=len;
     
    629687      else
    630688         rtems_panic("i8254EI : no more free descriptors");
    631 #if 0
    632       sc->stats.txMultiMaxLen= MAX(mdest->m_len, sc->stats.txMultiMaxLen);
    633       sc->stats.txMultiBuffPacket++;
    634 #endif
    635689    } /* end for while */
    636690    /* free old mbuf chain */
    637 #if 0
    638     sc->stats.txMultiMaxLoop=MAX(loop, sc->stats.txMultiMaxLoop);
    639 #endif
    640691    m_freem(m);
    641692    m=0;
     
    743794
    744795    status = sc->sc_rxdescs[i].wrx_status;
     796    if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
     797
    745798    errors = sc->sc_rxdescs[i].wrx_errors;
    746799    len = le16toh(sc->sc_rxdescs[i].wrx_len);
    747800    m = sc->rxs_mbuf[i];
    748 
    749     if ((status & WRX_ST_DD) == 0)  break; /* descriptor not done */
    750 
    751801    if (sc->sc_rxdiscard) {
    752802       printk("RX: discarding contents of descriptor %d\n", i);
     
    820870  uint8_t cksumfields;
    821871
     872#if 0
     873  /* KATETODO : sc_align_tweak */
     874        /*
     875         * *_HDR_ALIGNED_P is constant 1 if __NO_STRICT_ALIGMENT is set.
     876         * There is a small but measurable benefit to avoiding the adjusment
     877         * of the descriptor so that the headers are aligned, for normal mtu,
     878         * on such platforms.  One possibility is that the DMA itself is
     879         * slightly more efficient if the front of the entire packet (instead
     880         * of the front of the headers) is aligned.
     881         *
     882         * Note we must always set align_tweak to 0 if we are using
     883         * jumbo frames.
     884         */
     885#ifdef __NO_STRICT_ALIGNMENT
     886        sc->sc_align_tweak = 0;
     887#else
     888        if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_CRC_LEN) > (MCLBYTES - 2))
     889                sc->sc_align_tweak = 0;
     890        else
     891                sc->sc_align_tweak = 2;
     892#endif /* __NO_STRICT_ALIGNMENT */
     893#endif
     894
    822895  /* Cancel any pending I/O. */
    823896  wm_stop(ifp, 0);
    824897
     898  /* update statistics before reset */
     899  ifp->if_collisions += CSR_READ(sc, WMREG_COLC);
     900  ifp->if_ierrors += CSR_READ(sc, WMREG_RXERRC);
     901
     902  /* Reset the chip to a known state. */
     903  wm_reset(sc);
     904
    825905  /* Initialize the error buffer ring */
    826   sc->intr_err_ptr1=0;
    827   sc->intr_err_ptr2=0;
    828   for (i=0; i< INTR_ERR_SIZE; i++) sc->intr_errsts[i]=0;
     906  sc->if_err_ptr1=0;
     907  sc->if_err_ptr2=0;
     908  for (i=0; i< IF_ERR_BUFSZE; i++) sc->if_errsts[i]=0;
    829909
    830910  /* Initialize the transmit descriptor ring. */
    831   memset(sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
     911  memset( (void *) sc->sc_txdescs, 0, sizeof(sc->sc_txdescs));
    832912  sc->txq_free = NTXDESC;
    833913  sc->txq_next = 0;
     
    848928  CSR_WRITE(sc,WMREG_TDH, 0);
    849929  CSR_WRITE(sc,WMREG_TDT, 0);
    850   CSR_WRITE(sc,WMREG_TIDV, 64 );
    851   CSR_WRITE(sc,WMREG_TADV, 128);
     930  CSR_WRITE(sc,WMREG_TIDV, 0 );
     931  /* CSR_WRITE(sc,WMREG_TADV, 128);  not for 82544 */
    852932
    853933  CSR_WRITE(sc,WMREG_TXDCTL, TXDCTL_PTHRESH(0) |
     
    863943   * this packet.
    864944   */
    865 #ifdef CKSUM_OFFLOAD
    866   if (m0->m_pkthdr.csum_flags &
    867      (M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4)) {
    868      if (wm_tx_cksum(sc, txs, &TxDescCmd,&cksumfields) != 0) {
     945#ifdef RTEMS_CKSUM_OFFLOAD
     946  if (m0->m_pkthdr.csum_flags & (M_CSUM_TSOv4|M_CSUM_TSOv6|
     947                    M_CSUM_IPv4|M_CSUM_TCPv4|M_CSUM_UDPv4|
     948                                 M_CSUM_TCPv6|M_CSUM_UDPv6)) {
     949     if (wm_tx_offload(sc, txs, &TxDescCmd,&cksumfields) != 0) {
    869950         /* Error message already displayed. */
    870951         continue;
     
    874955     TxDescCmd = 0;
    875956     cksumfields = 0;
    876 #ifdef CKSUM_OFFLOAD
     957#ifdef RTEMS_CKSUM_OFFLOAD
    877958  }
    878959#endif
     
    893974   * descriptor rings.
    894975   */
    895   memset(sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
     976  memset( (void *) sc->sc_rxdescs, 0, sizeof(sc->sc_rxdescs));
    896977  CSR_WRITE(sc,WMREG_RDBAH, 0);
    897978  CSR_WRITE(sc,WMREG_RDBAL, WM_CDRXADDR(sc));
     
    900981  CSR_WRITE(sc,WMREG_RDT, 0);
    901982  CSR_WRITE(sc,WMREG_RDTR, 0 |RDTR_FPD);
    902   CSR_WRITE(sc, WMREG_RADV, 256);
     983  /* CSR_WRITE(sc, WMREG_RADV, 256);  not for 82544.  */
    903984
    904985  for (i = 0; i < NRXDESC; i++) {
     
    9441025  CSR_WRITE(sc,WMREG_FCRTH, FCRTH_DFLT);
    9451026  CSR_WRITE(sc,WMREG_FCRTL, sc->sc_fcrtl);
    946   CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);
     1027  /*KATETO   CSR_WRITE(sc,WMREG_FCTTV, FCTTV_DFLT);*/
     1028  CSR_WRITE(sc,WMREG_FCTTV, 0x100);
    9471029
    9481030  sc->sc_ctrl &= ~CTRL_VME;
    949   /*sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE;*/
    950   /* enable Big Endian Mode for the powerPC
    951   sc->sc_ctrl |= CTRL_BEM;*/
     1031  /* KATETODo : not here.
     1032     Configures flow control settings after link is established
     1033     sc->sc_ctrl |= CTRL_TFCE | CTRL_RFCE; */
    9521034
    9531035  /* Write the control registers. */
     
    9571039#endif
    9581040
    959   /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */ 
     1041  /* MOTLoad : WMREG_RXCSUM (0x5000)= 0, no Rx checksum offloading */
     1042#ifdef RTEMS_CKSUM_OFFLOAD
     1043  /*
     1044   * Set up checksum offload parameters.
     1045   */
     1046   reg = CSR_READ(sc, WMREG_RXCSUM);
     1047   reg &= ~(RXCSUM_IPOFL | RXCSUM_IPV6OFL | RXCSUM_TUOFL);
     1048   if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx)
     1049            reg |= RXCSUM_IPOFL;
     1050   if (ifp->if_capenable & (IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx))
     1051            reg |= RXCSUM_IPOFL | RXCSUM_TUOFL;
     1052   if (ifp->if_capenable & (IFCAP_CSUM_TCPv6_Rx | IFCAP_CSUM_UDPv6_Rx))
     1053            reg |= RXCSUM_IPV6OFL | RXCSUM_TUOFL;
     1054   CSR_WRITE(sc, WMREG_RXCSUM, reg);
     1055#endif
    9601056
    9611057  /*
     
    9861082   */
    9871083  sc->sc_tctl = TCTL_EN | TCTL_PSP | TCTL_CT(TX_COLLISION_THRESHOLD) |
    988             TCTL_COLD(TX_COLLISION_DISTANCE_FDX) | TCTL_RTLC; /*transmitter enable*/
     1084            TCTL_COLD(TX_COLLISION_DISTANCE_FDX) |
     1085            TCTL_RTLC /* transmit on late collision */;
    9891086
    9901087  /*
     
    9941091   *
    9951092   * Only the i82544 has the ability to strip the incoming
    996    * CRC, so we don't enable that feature. (TODO)
     1093   * CRC, so we don't enable that feature. (TODO: |RCTL_SECRC)
    9971094   */
    9981095  sc->sc_mchash_type = 0;
    9991096  sc->sc_rctl = RCTL_EN | RCTL_LBM_NONE | RCTL_RDMTS_1_2 | RCTL_LPE |
    1000             RCTL_DPF | RCTL_MO(sc->sc_mchash_type);
    1001 
    1002   /* (MCLBYTES == 2048) */
    1003   sc->sc_rctl |= RCTL_2k;
     1097    RCTL_DPF | RCTL_MO(sc->sc_mchash_type)|RCTL_SECRC;
     1098
     1099  if (MCLBYTES == 2048) {
     1100     sc->sc_rctl |= RCTL_2k;
     1101  } else {
     1102        switch(MCLBYTES) {
     1103        case 4096:
     1104             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_4k;
     1105             break;
     1106        case 8192:
     1107             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_8k;
     1108             break;
     1109        case 16384:
     1110             sc->sc_rctl |= RCTL_BSEX | RCTL_BSEX_16k;
     1111             break;
     1112        default:
     1113             rtems_panic("wm_init: MCLBYTES %d unsupported",
     1114                    MCLBYTES);
     1115             break;
     1116        }
     1117  }
    10041118
    10051119#ifdef WM_DEBUG
     
    10191133}
    10201134
     1135void BSP_rdTIDV()
     1136{
     1137  printf("Reg TIDV: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV)));
     1138}
     1139void BSP_rdRDTR()
     1140{
     1141  printf("Reg RDTR: 0x%x\n", in_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR)));
     1142}
     1143
     1144void BSP_setTIDV(int val)
     1145{
     1146  out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_TIDV), val);
     1147}
     1148
     1149void BSP_setRDTR(int val)
     1150{
     1151  out_le32((volatile unsigned *) (BSP_1GHz_membase+WMREG_RDTR), val);
     1152}
    10211153/*
    10221154 * i82544EI_ifinit:             [ifnet interface function]
     
    12341366}
    12351367
     1368#if 0
    12361369/*
    12371370 * wm_acquire_eeprom:
     
    12651398  return (0);
    12661399}
     1400#endif
    12671401
    12681402/*
     
    13691503  sc->sc_rctl &= ~(RCTL_BAM | RCTL_UPE | RCTL_MPE);
    13701504
    1371   /*  if (ifp->if_flags & IFF_BROADCAST)*/
     1505  if (ifp->if_flags & IFF_BROADCAST)
    13721506     sc->sc_rctl |= RCTL_BAM;
    13731507  if (ifp->if_flags & IFF_PROMISC) {
     
    14391573{
    14401574  struct ifnet          *ifp = &sc->arpcom.ac_if;
    1441   unsigned long         intr_status= sc->intr_errsts[sc->intr_err_ptr1++];
     1575  unsigned long         intr_status= sc->if_errsts[sc->if_err_ptr1];
    14421576
    14431577  /* read and reset the status; because this is written
    14441578   * by the ISR, we must disable interrupts here
    14451579   */
    1446   sc->intr_err_ptr1 %=INTR_ERR_SIZE; /* Till Straumann */
    14471580  if (intr_status) {
    14481581    printk("Error %s%d:", ifp->if_name, ifp->if_unit);
     
    14541587  else
    14551588    printk("%s%d: Ghost interrupt ?\n",ifp->if_name,ifp->if_unit);
     1589  sc->if_errsts[sc->if_err_ptr1]=0; 
     1590  if ( (++sc->if_err_ptr1) == IF_ERR_BUFSZE) sc->if_err_ptr1=0; /* Till Straumann */
    14561591}
    14571592
     
    14941629     if (KILL_EVENT & events)  break;
    14951630
    1496      if (events & RX_EVENT)  i82544EI_rx(sc);
     1631     if (events & RX_EVENT)  i82544EI_rx(sc); /* in ISR instead */
    14971632
    14981633     /* clean up and try sending packets */
     
    15021637        while (sc->txq_free>0) {
    15031638           if (sc->txq_free>TXQ_HiLmt_OFF) {
     1639              m=0;
    15041640              IF_DEQUEUE(&ifp->if_snd,m);
    15051641              if (m==0) break;
     
    15101646              break;
    15111647           }
    1512            if (events & RX_EVENT)  i82544EI_rx(sc);
    15131648        }
    15141649         /* we leave this loop
     
    15181653          *    returned 0
    15191654          */
    1520      } while (m && sc->txq_free);
     1655     } while (m);
    15211656
    15221657     ifp->if_flags &= ~IFF_OACTIVE;
     
    15551690  rtems_task_delete(RTEMS_SELF);
    15561691}
     1692
     1693/*
     1694 * wm_gmii_reset:
     1695 *
     1696 *      Reset the PHY.
     1697 */
     1698static void wm_gmii_reset(struct wm_softc *sc)
     1699{
     1700
     1701  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl | CTRL_PHY_RESET);
     1702  rtems_bsp_delay(20000);
     1703
     1704  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
     1705  rtems_bsp_delay(20000);
     1706
     1707}
     1708
     1709/*
     1710 * wm_gmii_mediainit:
     1711 *
     1712 *      Initialize media for use on 1000BASE-T devices.
     1713 */
     1714static void wm_gmii_mediainit(struct wm_softc *sc)
     1715{
     1716  /*  struct ifnet *ifp = &sc->arpcom.ac_if;*/
     1717
     1718  /* We have MII. */
     1719  sc->sc_flags |= WM_F_HAS_MII;
     1720
     1721  sc->sc_tipg = TIPG_1000T_DFLT; /* 0x602008 */
     1722
     1723  /*
     1724   * Let the chip set speed/duplex on its own based on
     1725   * signals from the PHY.
     1726   * XXXbouyer - I'm not sure this is right for the 80003,
     1727   * the em driver only sets CTRL_SLU here - but it seems to work.
     1728   */
     1729  sc->sc_ctrl |= CTRL_SLU;
     1730  CSR_WRITE(sc, WMREG_CTRL, sc->sc_ctrl);
     1731
     1732  wm_gmii_reset(sc);
     1733
     1734#if 0
     1735  /* Initialize our media structures and probe the GMII. */
     1736  sc->sc_mii.mii_ifp = ifp;
     1737
     1738  sc->sc_mii.mii_readreg = wm_gmii_i82544_readreg;
     1739  sc->sc_mii.mii_writereg = wm_gmii_i82544_writereg;
     1740  sc->sc_mii.mii_statchg = wm_gmii_statchg;
     1741
     1742  ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, wm_gmii_mediachange,
     1743            wm_gmii_mediastatus);
     1744
     1745  mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY,
     1746            MII_OFFSET_ANY, MIIF_DOPAUSE);
     1747  if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
     1748     ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL);
     1749     ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE);
     1750  } else
     1751      ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
     1752#endif
     1753}
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/if_wmreg.h

    re1be2b3 rd7196bf  
    66 *
    77 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
     8 * Some are added by Shuchen Kate Feng <feng1@bnl.gov>,
     9 *            NSLS, Brookhaven National Laboratory. All rights reserved.
     10 *            under the Deaprtment of Energy contract DE-AC02-98CH10886
    811 *
    912 * Redistribution and use in source and binary forms, with or without
     
    5760 * and there must be an even multiple of 8 descriptors in the ring.
    5861 */
    59 typedef struct wiseman_rxdesc {
     62typedef volatile struct wiseman_rxdesc {
    6063        wiseman_addr_t  wrx_addr;       /* buffer address */
    6164
     
    104107        uint16_t wtxu_vlan;             /* VLAN info */
    105108} __attribute__((__packed__)) wiseman_txfields_t;
    106 typedef struct wiseman_txdesc {
     109typedef volatile struct wiseman_txdesc {
    107110        wiseman_addr_t  wtx_addr;       /* buffer address */
    108111        uint32_t        wtx_cmdlen;     /* command and length */
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pci_map.c

    re1be2b3 rd7196bf  
    44 * Copyright (c) 2004, 2005  Brookhaven National  Laboratory
    55 *               S. Kate Feng <feng1@bnl.gov>
     6 *               under the Deaprtment of Energy contract DE-AC02-98CH10886
    67 *
    78 * Copyright (c) 1998, 2000 The NetBSD Foundation, Inc.
  • c/src/lib/libbsp/powerpc/mvme5500/network/if_1GHz/pcireg.h

    re1be2b3 rd7196bf  
    55 *     Christopher G. Demetriou.  All rights reserved.
    66 * Copyright (c) 1994, 1996 Charles M. Hannum.  All rights reserved.
     7 * Copyright (C) 2007 Brookhaven National Laboratory, Shuchen Kate Feng
    78 *
    89 * Redistribution and use in source and binary forms, with or without
     
    3132 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    3233 */
     34#include <bsp.h>
    3335
    3436/*
     
    306308
    307309#define PCI_MAPREG_IO_ADDR(mr)                                          \
    308             ((mr) & PCI_MAPREG_IO_ADDR_MASK)
     310            ((mr+PCI0_IO_BASE) & PCI_MAPREG_IO_ADDR_MASK)
    309311#define PCI_MAPREG_IO_SIZE(mr)                                          \
    310312            (PCI_MAPREG_IO_ADDR(mr) & -PCI_MAPREG_IO_ADDR(mr))
  • c/src/lib/libbsp/powerpc/mvme5500/pci/detect_host_bridge.c

    re1be2b3 rd7196bf  
    77 *
    88 * Copyright (C) 2004 S. Kate Feng, <feng1@bnl.gov>
    9  * wrote it to support the MVME5500 board.
     9 * wrote it to support the MVME5500 board,
     10 * under the Deaprtment of Energy contract DE-AC02-98CH10886.
    1011 *
    1112 */
     
    2425#define PCI_INVALID_VENDORDEVICEID      0xffffffff
    2526#define PCI_MULTI_FUNCTION              0x80
    26 #define HOSTBRIDGET_ERROR               0xf0000000
    2727
    2828unsigned long _BSP_clear_hostbridge_errors(int enableMCP, int quiet)
    2929{
    30   unsigned int pcidata, pcidata1;
    31   int PciLocal, busNumber=0;
     30  unsigned long pcidata=0;
     31  unsigned short val;
     32  int PciLocal, busNumber=0, loop;
    3233 
    3334  /* On the mvme5500 board, the GT64260B system controller had the MCP
     
    3637   */
    3738  if (enableMCP) return(-1);
    38   for (PciLocal=0; PciLocal<1; PciLocal++ ) {
    39      pci_read_config_dword(busNumber,
    40                         0,
    41                         0,
    42                         PCI_COMMAND,
    43                         &pcidata);
     39  for (PciLocal=0; PciLocal<2; PciLocal++ ) {
     40      pci_read_config_word(busNumber,
     41                               0,
     42                               0,
     43                          PCI_STATUS,
     44                           &val);
     45    if ( (val & PCI_STATUS_CLRERR_MASK) && (!quiet))
     46       printk("Before _BSP_clear_hostbridge_errors(): PCI %d sts was 0x%x\n",
     47                       PciLocal, val);
     48      if (!busNumber)
     49        pcidata |= val;
     50      else
     51        pcidata |= (val <<16);
    4452
    45     if (!quiet)
    46     printk("Before _BSP_clear_hostbridge_errors(): 0x%x, cause 0x%x\n",
    47            pcidata, inl(0x1d58));
    48 
    49     outl(0,0x1d58);
    50 
    51     /* Clear the error on the host bridge */
    52     pcidata1= pcidata;
    53     pcidata1 |= PCI_STATUS_CLRERR_MASK;
    54     pcidata1 |= 0x140;
    55     pci_write_config_dword(busNumber,
     53      for ( loop=0; loop < 10; loop++) {
     54          /* Clear the error on the host bridge */
     55          pci_write_config_word(busNumber,
    5656                               0,
    5757                               0,
    58                           PCI_COMMAND,
    59                           pcidata1);
     58                          PCI_STATUS,
     59                          PCI_STATUS_CLRERR_MASK);
    6060
    61     pci_read_config_dword(busNumber,
     61          pci_read_config_word(busNumber,
    6262                               0,
    6363                               0,
    64                           PCI_COMMAND,
    65                           &pcidata1);
    66 
    67     if (!quiet) printk("After _BSP_clear_hostbridge_errors(): sts 0x%x\n",
    68                         pcidata1);
    69     if (pcidata1 & HOSTBRIDGET_ERROR) printk("BSP_clear_hostbridge_errors(): unable to clear pending hostbridge errors\n");
    70     busNumber += BSP_MAX_PCI_BUS_ON_PCI0;
     64                          PCI_STATUS,
     65                          &val);
     66          if ( !(val & PCI_STATUS_CLRERR_MASK))
     67             break;
     68          else {
     69            if (loop==9)
     70              printk("BSP_clear_hostbridge_errors(): unable to clear pending hostbridge errors\n");
     71          }
     72      }
     73      busNumber += BSP_MAX_PCI_BUS_ON_PCI0;
    7174  }
    72   return(pcidata &  HOSTBRIDGET_ERROR);
     75  return(pcidata);
    7376}
  • c/src/lib/libbsp/powerpc/mvme5500/pci/gtpcireg.h

    re1be2b3 rd7196bf  
    4747#define PCI_IO_BASE_ADDR  PCI_BASE_ADDRESS_5
    4848
    49 #define  PCI_STATUS_CLRERR_MASK 0xf9000000 /* <SKF> */
     49#define  PCI_STATUS_CLRERR_MASK 0xf900 /* <SKF> */
    5050
    5151#define PCI_BARE_IntMemEn     0x200
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci.c

    re1be2b3 rd7196bf  
    1717 *
    1818 *  Copyright 2004, Brookhaven National Laboratory and
    19  *                  Shuchen K. Feng, <feng1@bnl.gov>, 2004
    20  *   - modified and added support for MVME5500 board
    21  *   - added 2nd PCI support for the mvme5500/GT64260 PCI bridge
    22  *   - added bus support for the expansion of PMCSpan, thanks to
    23  *     Peter Dufault (dufault@hda.com) for inputs.
     19 *                  Shuchen K. Feng, <feng1@bnl.gov>, 2004, 2008
     20 *   
     21 *   - to be consistent with the original pci.c written by Eric Valette
     22 *   - added 2nd PCI support for discovery based PCI bridge (e.g. mvme5500/mvme6100)
     23 *   - added bus support for the expansion of PMCSpan as per request by Peter
    2424 */
    2525#define PCI_MAIN
     
    2828#include <rtems/bspIo.h>            /* printk */
    2929
     30#include <bsp/irq.h>
    3031#include <bsp/pci.h>
    3132#include <bsp/gtreg.h>
    3233#include <bsp/gtpcireg.h>
     34#include <bsp.h>
    3335
    3436#include <stdio.h>
     
    3638
    3739#define PCI_DEBUG 0
    38 #define PCI_PRINT 0
     40#define PCI_PRINT 1
    3941
    4042/* allow for overriding these definitions */
     
    5759#define HOSTBRIDGET_ERROR               0xf0000000
    5860
    59 /* define a shortcut */
    60 #define pci     BSP_pci_configuration
    61 
    62 static int                numPCIDevs=0;
     61#define GT64x60_PCI_CONFIG_ADDR         GT64x60_REG_BASE + PCI_CONFIG_ADDR
     62#define GT64x60_PCI_CONFIG_DATA         GT64x60_REG_BASE + PCI_CONFIG_DATA
     63
     64#define GT64x60_PCI1_CONFIG_ADDR        GT64x60_REG_BASE + PCI1_CONFIG_ADDR
     65#define GT64x60_PCI1_CONFIG_DATA        GT64x60_REG_BASE + PCI1_CONFIG_DATA
     66
     67static int      numPCIDevs=0;
     68static DiscoveryChipVersion BSP_sysControllerVersion = 0;
     69static BSP_VMEchipTypes BSP_VMEinterface = 0;
     70static pci_config BSP_pci[2]={
     71  {(volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR),
     72   (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA),
     73   0 /* defined at BSP_pci_configuration */},
     74  {(volatile unsigned char*) (GT64x60_PCI1_CONFIG_ADDR),
     75   (volatile unsigned char*) (GT64x60_PCI1_CONFIG_DATA),
     76   0 /* defined at BSP_pci_configuration */}
     77};
     78
    6379extern void pci_interface();
    6480
     
    6783 */
    6884#define pciConfigPack(bus,dev,func,offset)\
    69 (((func&7)<<8)|((dev&0x1f )<<11)|(( bus&0xff)<<16)|(offset&0xfc))|0x80000000
     85((offset&~3)<<24)|(PCI_DEVFN(dev,func)<<16)|(bus<<8)|0x80
    7086
    7187/*
     
    7692/* Please note that PCI0 and PCI1 does not correlate with the busNum 0 and 1.
    7793 */
    78 static int direct_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func,
     94static int indirect_pci_read_config_byte(unsigned char bus,unsigned char dev,unsigned char func,
    7995unsigned char offset,unsigned char *val)
    8096{
    81   volatile unsigned char *config_addr, *config_data;
    82 
    83   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    84      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    85      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    86      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    87   }
    88   else {
    89      config_addr = pci.pci_config_addr;
    90      config_data = pci.pci_config_data;
    91   }
     97  int n=0;
     98
     99  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     100     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     101     n=1;
     102  }
     103
    92104  *val = 0xff;
    93105  if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER;
    94106#if 0
    95   printk("addr %x, data %x, pack %x \n", config_addr,
    96     config_data,pciConfigPack(bus,dev,func,offset));
    97 #endif
    98   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    99   *val = inb(config_data + (offset&3));
    100   return PCIBIOS_SUCCESSFUL;
    101 }
    102 
    103 static int direct_pci_read_config_word(unsigned char bus, unsigned char dev,
     107  printk("addr %x, data %x, pack %x \n", BSP_pci[n].pci_config_addr),
     108    BSP_pci[n].config_data,pciConfigPack(bus,dev,func,offset));
     109#endif
     110
     111  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     112  *val = in_8(BSP_pci[n].pci_config_data + (offset&3));
     113  return PCIBIOS_SUCCESSFUL;
     114}
     115
     116static int indirect_pci_read_config_word(unsigned char bus, unsigned char dev,
    104117unsigned char func, unsigned char offset, unsigned short *val)
    105118{
    106   volatile unsigned char *config_addr, *config_data;
    107 
    108   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    109      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    110      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    111      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    112   }
    113   else {
    114      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    115      config_data = (volatile unsigned char*) pci.pci_config_data;
     119  int n=0;
     120
     121  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     122     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     123     n=1;
    116124  }
    117125
     
    122130    config_data,pciConfigPack(bus,dev,func,offset));
    123131#endif
    124   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    125   *val = inw(config_data + (offset&2));
    126   return PCIBIOS_SUCCESSFUL;
    127 }
    128 
    129 static int direct_pci_read_config_dword(unsigned char bus, unsigned char dev,
     132  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     133  *val = in_le16(BSP_pci[n].pci_config_data + (offset&2));
     134  return PCIBIOS_SUCCESSFUL;
     135}
     136
     137static int indirect_pci_read_config_dword(unsigned char bus, unsigned char dev,
    130138unsigned char func, unsigned char offset, unsigned int *val)
    131139{
    132   volatile unsigned char *config_addr, *config_data;
    133 
    134   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    135      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    136      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    137      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    138   }
    139   else {
    140      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    141      config_data = (volatile unsigned char*) pci.pci_config_data;
     140  int n=0;
     141
     142  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     143     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     144     n=1;
    142145  }
    143146
    144147  *val = 0xffffffff;
    145148  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    146 #if 0
    147   printk("addr %x, data %x, pack %x \n", config_addr,
    148     pci.pci_config_data,pciConfigPack(bus,dev,func,offset));
    149 #endif
    150   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    151   *val = inl(config_data);
    152   return PCIBIOS_SUCCESSFUL;
    153 }
    154 
    155 static int direct_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val)
    156 {
    157   volatile unsigned char *config_addr, *config_data;
    158 
    159   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    160      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    161      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    162      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    163   }
    164   else {
    165      config_addr = pci.pci_config_addr;
    166      config_data = pci.pci_config_data;
     149
     150  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     151  *val = in_le32(BSP_pci[n].pci_config_data);
     152  return PCIBIOS_SUCCESSFUL;
     153}
     154
     155static int indirect_pci_write_config_byte(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned char val)
     156{
     157  int n=0;
     158
     159  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     160     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     161     n=1;
    167162  }
    168163
    169164  if (offset & ~0xff) return PCIBIOS_BAD_REGISTER_NUMBER;
    170 #if 0
    171   printk("addr %x, data %x, pack %x \n", config_addr,
    172     config_data,pciConfigPack(bus,dev,func,offset));
    173 #endif
    174 
    175   outl(pciConfigPack(bus,dev,func,offset), config_addr);
    176   outb(val, config_data + (offset&3));
    177   return PCIBIOS_SUCCESSFUL;
    178 }
    179 
    180 static int direct_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val)
    181 {
    182   volatile unsigned char *config_addr, *config_data;
    183 
    184   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    185      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    186      config_addr = (volatile unsigned char*) PCI1_CONFIG_ADDR;
    187      config_data = (volatile unsigned char*) PCI1_CONFIG_DATA;
    188   }
    189   else {
    190      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    191      config_data = (volatile unsigned char*) pci.pci_config_data;
     165
     166  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     167  out_8(BSP_pci[n].pci_config_data + (offset&3), val);
     168  return PCIBIOS_SUCCESSFUL;
     169}
     170
     171static int indirect_pci_write_config_word(unsigned char bus, unsigned char dev,unsigned char func, unsigned char offset, unsigned short val)
     172{
     173  int n=0;
     174
     175  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     176     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     177     n=1;
    192178  }
    193179
    194180  if ((offset&1)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    195 #if 0
    196   printk("addr %x, data %x, pack %x \n", config_addr,
    197     config_data,pciConfigPack(bus,dev,func,offset));
    198 #endif
    199   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    200   outw(val, config_data + (offset&3));
    201   return PCIBIOS_SUCCESSFUL;
    202 }
    203 
    204 static int direct_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val)
    205 {
    206   volatile unsigned char *config_addr, *config_data;
    207 
    208   if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
    209      bus-=BSP_MAX_PCI_BUS_ON_PCI0;
    210      config_addr = (volatile unsigned char *) PCI1_CONFIG_ADDR;
    211      config_data = (volatile unsigned char *) PCI1_CONFIG_DATA;
    212   }
    213   else {
    214      config_addr = (volatile unsigned char*) pci.pci_config_addr;
    215      config_data = (volatile unsigned char*) pci.pci_config_data;
     181
     182  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     183  out_le16(BSP_pci[n].pci_config_data + (offset&3), val);
     184  return PCIBIOS_SUCCESSFUL;
     185}
     186
     187static int indirect_pci_write_config_dword(unsigned char bus,unsigned char dev,unsigned char func, unsigned char offset, unsigned int val)
     188{
     189  int n=0;
     190
     191  if (bus>= BSP_MAX_PCI_BUS_ON_PCI0) {
     192     bus-=BSP_MAX_PCI_BUS_ON_PCI0;
     193     n=1;
    216194  }
    217195
    218196  if ((offset&3)|| (offset & ~0xff)) return PCIBIOS_BAD_REGISTER_NUMBER;
    219 #if 0
    220   printk("addr %x, data %x, pack %x \n", config_addr,
    221     config_data,pciConfigPack(bus,dev,func,offset));
    222 #endif
    223   outl(pciConfigPack(bus,dev,func,offset),config_addr);
    224   outl(val,config_data);
    225   return PCIBIOS_SUCCESSFUL;
    226 }
    227 
    228 const pci_config_access_functions pci_direct_functions = {
    229         direct_pci_read_config_byte,
    230         direct_pci_read_config_word,
    231         direct_pci_read_config_dword,
    232         direct_pci_write_config_byte,
    233         direct_pci_write_config_word,
    234         direct_pci_write_config_dword
     197
     198  out_be32(BSP_pci[n].pci_config_addr, pciConfigPack(bus,dev,func,offset));
     199  out_le32(BSP_pci[n].pci_config_data, val);
     200  return PCIBIOS_SUCCESSFUL;
     201}
     202
     203const pci_config_access_functions pci_indirect_functions = {
     204        indirect_pci_read_config_byte,
     205        indirect_pci_read_config_word,
     206        indirect_pci_read_config_dword,
     207        indirect_pci_write_config_byte,
     208        indirect_pci_write_config_word,
     209        indirect_pci_write_config_dword
    235210};
    236211
    237212
    238 pci_config BSP_pci_configuration = {(volatile unsigned char*) PCI_CONFIG_ADDR,
    239                          (volatile unsigned char*)PCI_CONFIG_DATA,
    240                                     &pci_direct_functions};
     213pci_config BSP_pci_configuration = {
     214           (volatile unsigned char*) (GT64x60_PCI_CONFIG_ADDR),
     215           (volatile unsigned char*) (GT64x60_PCI_CONFIG_DATA),
     216           &pci_indirect_functions};
     217
     218DiscoveryChipVersion BSP_getDiscoveryChipVersion()
     219{
     220  return(BSP_sysControllerVersion);
     221}
     222
     223BSP_VMEchipTypes BSP_getVMEchipType()
     224{
     225  return(BSP_VMEinterface);
     226}
    241227
    242228/*
     
    249235{
    250236  int deviceFound;
    251   unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs;
    252   unsigned int ulHeader;
    253   unsigned int pcidata, ulClass, ulDeviceID;
    254 
    255   pci_interface();
    256  
     237  unsigned char ucBusNumber, ucSlotNumber, ucFnNumber, ucNumFuncs, data8;
     238  uint32_t ulHeader, ulClass, ulDeviceID;
     239#if PCI_DEBUG
     240  uint32_t pcidata;
     241#endif
     242
    257243  /*
    258244   * Scan PCI0 and PCI1 buses
     
    280266      switch(ulDeviceID) {
    281267        case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT6426xAB<<16)):
    282 #if PCI_PRINT
    283           printk("Marvell GT6426xA/B hostbridge detected at bus%d slot%d\n",
     268          pci_read_config_byte(0,0,0,PCI_REVISION_ID, &data8);
     269          switch(data8) {
     270          case 0x10:
     271            BSP_sysControllerVersion = GT64260A;
     272#if PCI_PRINT
     273            printk("Marvell GT64260A (Discovery I) hostbridge detected at bus%d slot%d\n",
     274                 ucBusNumber,ucSlotNumber);
     275#endif
     276            break;
     277          case 0x20:
     278            BSP_sysControllerVersion = GT64260B;
     279#if PCI_PRINT
     280            printk("Marvell GT64260B (Discovery I) hostbridge detected at bus%d slot%d\n",
     281                 ucBusNumber,ucSlotNumber);
     282#endif
     283            break;
     284          default:
     285            printk("Undefined revsion of GT64260 chip\n");
     286            break;
     287          }
     288          break;
     289        case (PCI_VENDOR_ID_MARVELL+(PCI_DEVICE_ID_MARVELL_GT64360<<16)):
     290          BSP_sysControllerVersion = MV64360;
     291#if PCI_PRINT
     292          printk("Marvell GT64360 (Discovery II) hostbridge detected at bus%d slot%d\n",
    284293                 ucBusNumber,ucSlotNumber);
    285294#endif
    286295          break;
    287296        case (PCI_VENDOR_ID_PLX2+(PCI_DEVICE_ID_PLX2_PCI6154_HB2<<16)):
     297          BSP_VMEinterface = UNIVERSE2;
    288298#if PCI_PRINT
    289299          printk("PLX PCI6154 PCI-PCI bridge detected at bus%d slot%d\n",
     
    297307#endif
    298308          break;
     309        case (PCI_VENDOR_ID_TUNDRA+(PCI_DEVICE_ID_TUNDRA_TSI148<<16)):
     310          BSP_VMEinterface = TSI148;
     311#if PCI_PRINT
     312          printk("TUNDRA Tsi148 PCI/X-VME bridge detected at bus%d slot%d\n",
     313                 ucBusNumber,ucSlotNumber);
     314#endif
     315          break;
    299316      case (PCI_VENDOR_ID_INTEL+(PCI_DEVICE_INTEL_82544EI_COPPER<<16)):
    300317#if PCI_PRINT
     
    304321          break;
    305322      case (PCI_VENDOR_ID_DEC+(PCI_DEVICE_ID_DEC_21150<<16)):
    306  #if PCI_PRINT
     323#if PCI_PRINT
    307324          printk("DEC21150 PCI-PCI bridge detected at bus%d slot%d\n",
    308325                 ucBusNumber,ucSlotNumber);
     
    310327          break;
    311328       default :
     329#if PCI_PRINT
    312330          printk("BSP unlisted vendor, Bus%d Slot%d DeviceID 0x%x \n",
    313331             ucBusNumber,ucSlotNumber, ulDeviceID);
     332#endif
     333          /* Kate Feng : device not supported by BSP needs to remap the IRQ line on mvme5500/mvme6100 */
     334          pci_read_config_byte(ucBusNumber,ucSlotNumber,0,PCI_INTERRUPT_LINE,&data8);
     335          if (data8 < BSP_GPP_IRQ_LOWEST_OFFSET)  pci_write_config_byte(ucBusNumber,
     336             ucSlotNumber,0,PCI_INTERRUPT_LINE,BSP_GPP_IRQ_LOWEST_OFFSET+data8);
     337
    314338          break;
    315339      }
     
    404428
    405429      }
    406 
    407       pci_read_config_dword(ucBusNumber,
    408                                ucSlotNumber,
    409                                0,
    410                           PCI_COMMAND,
    411                           &pcidata);
    412 #if PCI_DEBUG
    413       printk("MOTLoad command staus 0x%x, ", pcidata);
    414 #endif
    415       /* Clear the error on the host bridge */
    416       if ( (ucBusNumber==0) && (ucSlotNumber==0))
    417         pcidata |= PCI_STATUS_CLRERR_MASK;
    418       /* Enable bus,I/O and memory master access. */
    419       pcidata |= (PCI_COMMAND_MASTER|PCI_COMMAND_IO|PCI_COMMAND_MEMORY);
    420       pci_write_config_dword(ucBusNumber,
    421                                ucSlotNumber,
    422                                0,
    423                           PCI_COMMAND,
    424                           pcidata);
    425 
    426       pci_read_config_dword(ucBusNumber,
    427                                ucSlotNumber,
    428                                0,
    429                           PCI_COMMAND,
    430                           &pcidata);
    431 #if PCI_DEBUG     
    432       printk("Now command/staus 0x%x\n", pcidata);
    433 #endif
    434430    }
    435431    if (deviceFound) ucMaxPCIBus++;
     
    439435         pci_bus_count(), numPCIDevs);
    440436#endif
     437  pci_interface(BSP_sysControllerVersion);
    441438  return(0);
    442439}
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci.h

    re1be2b3 rd7196bf  
    1515 *      pci.h,v 1.2 2002/05/14 17:10:16 joel Exp
    1616 *
    17  *      S. Kate Feng : Added support for Marvell and PLX. 3/5/2004.
    18 
     17 *      S. Kate Feng : Added support for Marvell and PLX. 2004, 2007.
    1918 */
    2019
     
    2423#include <rtems/pci.h>
    2524
    26 #define PCI_CAPABILITY_LIST_POINTER    0x34  /* <SKF> */
     25/************   Beginning of added by Kate Feng **********************/
     26#define PCI_CAPABILITY_LIST_POINTER    0x34
    2727
    2828/* Device classes and subclasses */
    29 #define PCI_CLASS_GT6426xAB_BRIDGE_PCI  0x0580    /* <SKF> */
     29#define PCI_CLASS_GT6426xAB_BRIDGE_PCI  0x0580
    3030         
    3131/*
     
    3434 * <linux-pcisupport@cck.uni-kl.de>.
    3535 */
    36 #define PCI_VENDOR_ID_MARVELL           0x11ab   /* <SKF> */
    37 #define PCI_DEVICE_ID_MARVELL_GT6426xAB 0x6430   /* <SKF> */
     36#define PCI_VENDOR_ID_MARVELL           0x11ab 
     37#define PCI_DEVICE_ID_MARVELL_GT6426xAB 0x6430   
     38#define PCI_DEVICE_ID_MARVELL_GT64360   0x6460 
    3839
    3940/* Note : The PLX Technology Inc. had the old VENDOR_ID.
    4041 * See PCI_VENDOR_ID_PLX,  PCI_VENDOR_ID_PLX_9050, ..etc.
    4142 */
    42 #define PCI_VENDOR_ID_PLX2              0x3388   /* <SKF> */
    43 #define PCI_DEVICE_ID_PLX2_PCI6154_HB2  0x26     /* <SKF> */
     43#define PCI_VENDOR_ID_PLX2              0x3388   
     44#define PCI_DEVICE_ID_PLX2_PCI6154_HB2  0x26     
    4445
    45 #define PCI_DEVICE_INTEL_82544EI_COPPER 0x1008  /* <SKF> */
     46#define PCI_DEVICE_ID_TUNDRA_TSI148     0x0148 
     47#define PCI_DEVICE_INTEL_82544EI_COPPER 0x1008
     48
     49/* end of added by Kate Feng */
    4650
    4751struct _pin_routes
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pci_interface.c

    re1be2b3 rd7196bf  
    88 *
    99 * 8/17/2006 : S. Kate Feng
    10  *             uses in_le32()/out_le32(), instead of inl()/outl() so that
    11  *             it is easier to be ported.
     10 *             uses in_le32()/out_le32(), instead of inl()/outl() for compatibility.
    1211 *
     12 * 11/2008 : Enable "PCI Read Agressive Prefetch",
     13 *           "PCI Read Line Agressive Prefetch", and
     14 *           "PCI Read Multiple Agressive Prefetch" to improve the
     15 *           performance of the PCI based applications (e.g. 1GHz NIC).
    1316 */
     17
    1418#include <libcpu/io.h>
    1519#include <rtems/bspIo.h>            /* printk */
     
    2024#include <bsp/gtpcireg.h>
    2125
    22 #define REG32_READ(reg) in_le32((volatile unsigned int *)(GT64260_REG_BASE+reg))
    23 #define REG32_WRITE(data, reg) out_le32((volatile unsigned int *)(GT64260_REG_BASE+reg), data)
    24 
    2526#define PCI_DEBUG     0
    2627
    27 /* Please reference the GT64260B datasheet, for the PCI interface,
    28  * Synchronization Barriers and PCI ordering.
    29  *
    30  * Some PCI devices require Synchronization Barriers or PCI ordering
    31  * for synchronization (only one mechanism allowed. See section 11.1.2).
    32  * To use the former mechanism(default), one needs to call
    33  * CPU0_PciEnhanceSync() or CPU1_PciEnhanceSync() to perform software
    34  * synchronization between the CPU and PCI activities.
    35  *
    36  * To use the PCI-ordering, one can call pciToCpuSync() to trigger
    37  * the PCI-to-CPU sync barrier after the out_xx(). In this mode,
    38  * PCI configuration reads suffer sync barrier latency. Please reference
    39  * the datasheet to explore other options.
    40  *
    41  * Note : If PCI_ORDERING is needed for the PCI0, while disabling the
    42  * deadlock  for the PCI0, one should keep the CommDLEn bit enabled
    43  * for the deadlock mechanism so that the 10/100 MB ethernet will
    44  * function correctly.
    45  *
     28#if 0
     29#define CPU2PCI_ORDER
     30#define PCI2CPU_ORDER
     31#endif
     32
     33/* PCI Read Agressive Prefetch Enable (1<<16 ),
     34 * PCI Read Line Agressive Prefetch Enable( 1<<17),
     35 * PCI Read Multiple Agressive Prefetch Enable (1<<18).
    4636 */
    47 /*#define PCI_ORDERING*/
     37#ifdef PCI2CPU_ORDER
     38#define PCI_ACCCTLBASEL_VALUE          0x01079000
     39#else
     40#define PCI_ACCCTLBASEL_VALUE          0x01071000
     41#endif
    4842
    49 #define EN_SYN_BAR   /* take MOTLoad default for enhanced SYN Barrier mode */
    50 
    51 /*#define PCI_DEADLOCK*/
    52 
    53 #ifdef PCI_ORDERING
    54 #define PCI_ACCCTLBASEL_VALUE          0x01009000
    55 #else
    56 #define PCI_ACCCTLBASEL_VALUE          0x01001000
    57 #endif
    5843
    5944#define ConfSBDis     0x10000000  /* 1: disable, 0: enable */
     
    6146#define ConfIOSBDis   0x30000000
    6247#define CpuPipeline   0x00002000  /* optional, 1:enable, 0:disable */
    63 
    64 #define CPU0_SYNC_TRIGGER   0xD0  /* CPU0 Sync Barrier trigger */
    65 #define CPU0_SYNC_VIRTUAL   0xC0  /* CPU0 Sync Barrier Virtual */
    66 
    67 #define CPU1_SYNC_TRIGGER   0xD8  /* CPU1 Sync Barrier trigger */
    68 #define CPU1_SYNC_VIRTUAL   0xC8  /* CPU1 Sync Barrier Virtual */
    69 
    7048
    7149/* CPU to PCI ordering register */
     
    8765#define ADDR_PIPELINE 0x00020000
    8866
    89 void  pciAccessInit();
     67void  pciAccessInit(void);
    9068
    91 void pci_interface()
     69void pci_interface(void)
    9270{
    9371
    94 #ifdef PCI_DEADLOCK
    95   REG32_WRITE(0x07fff600, CNT_SYNC_REG);
     72#ifdef CPU2PCI_ORDER
     73    /* MOTLOad deafult : 0x07ff8600 */
     74    out_le32((volatile unsigned int *)(GT64x60_REG_BASE+CNT_SYNC_REG), 0x07fff600);
    9675#endif
    97 #ifdef PCI_ORDERING
    98   /* Let's leave this to be MOTLOad deafult : 0x80070000
    99      REG32_WRITE(0xc0070000, DLOCK_ORDER_REG);*/
    100   /* Leave the CNT_SYNC_REG b/c MOTload default had the SyncBarMode set to 1 */
    101 #endif
     76    /* asserts SERR upon various detection */
     77    out_le32((volatile unsigned int *)(GT64x60_REG_BASE+0xc28), 0x3fffff);
     78    pciAccessInit();
     79}
    10280
    103   /* asserts SERR upon various detection */
    104   REG32_WRITE(0x3fffff, 0xc28);
    105 
    106   pciAccessInit();
    107 }
    108 /* Use MOTLoad default for Writeback Priority and Buffer Depth
    109  */
    110 void pciAccessInit()
     81void pciAccessInit(void)
    11182{
    11283  unsigned int PciLocal, data;
    11384
    11485  for (PciLocal=0; PciLocal < 2; PciLocal++) {
    115     /* MOTLoad combines the two banks of SDRAM into
    116      * one PCI access control because the top = 0x1ff
    117      */
    118     data = REG32_READ(GT_SCS0_Low_Decode) & 0xfff;
     86    data = in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
     87#if 0
     88    printk("PCI%d_ACCESS_CNTL_BASE0_LOW was 0x%x\n",PciLocal,data);
     89#endif
    11990    data |= PCI_ACCCTLBASEL_VALUE;
    12091    data &= ~0x300000;
    121     REG32_WRITE(data, PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80));
    122 #if PCI_DEBUG
    123     printk("PCI%d_ACCESS_CNTL_BASE0_LOW 0x%x\n",PciLocal,REG32_READ(PCI_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)));
     92    out_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80)), data);
     93#if 0
     94      printf("PCI%d_ACCESS_CNTL_BASE0_LOW now 0x%x\n",PciLocal,in_le32((volatile unsigned int *)(GT64x60_REG_BASE+PCI0_ACCESS_CNTL_BASE0_LOW+(PciLocal * 0x80))));
    12495#endif
    125 
    12696  }
    12797}
    12898
    129 /* Sync Barrier Trigger. A write to the CPU_SYNC_TRIGGER register triggers
    130  * the sync barrier process.  The three bits, define which buffers should
    131  * be flushed.
    132  * Bit 0 = PCI0 slave write buffer.
    133  * Bit 1 = PCI1 slave write buffer.
    134  * Bit 2 = SDRAM snoop queue.
    135  */
    136 void CPU0_PciEnhanceSync(unsigned int syncVal)
    137 {
    138   REG32_WRITE(syncVal,CPU0_SYNC_TRIGGER);
    139   while (REG32_READ(CPU0_SYNC_VIRTUAL));
    140 }
    141 
    142 void CPU1_PciEnhanceSync(unsigned int syncVal)
    143 {
    144   REG32_WRITE(syncVal,CPU1_SYNC_TRIGGER);
    145   while (REG32_READ(CPU1_SYNC_VIRTUAL));
    146 }
    147 
    148 /* Currently, if PCI_ordering is used for synchronization, configuration
    149  * reads is programmed to be the PCI slave "synchronization barrier"
    150  * cycles.
    151  */
    152 void pciToCpuSync(int pci_num)
    153 {
    154   unsigned char data;
    155   unsigned char bus=0;
    156 
    157   if (pci_num) bus += BSP_MAX_PCI_BUS_ON_PCI0;
    158   pci_read_config_byte(bus,0,0,4, &data);
    159 }
  • c/src/lib/libbsp/powerpc/mvme5500/pci/pcifinddevice.c

    re1be2b3 rd7196bf  
    88 *
    99 * Kate Feng <feng1@bnl.gov>, modified it to support the mvme5500 board.
    10  *
     10 * Under the Deaprtment of Energy contract DE-AC02-98CH10886.
    1111 */
    1212
  • c/src/lib/libbsp/powerpc/mvme5500/startup/bspclean.c

    re1be2b3 rd7196bf  
     1/* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>,
     2 *                    NSLS,Brookhaven National Laboratory
     3 */
    14#include <bsp.h>
    25#include <rtems/bspIo.h>
  • c/src/lib/libbsp/powerpc/mvme5500/startup/bspstart.c

    re1be2b3 rd7196bf  
    1818 *  (C) by Till Straumann, <strauman@slac.stanford.edu>, 2002, 2004, 2005
    1919 *
    20  *  Modified to support the MVME5500 board.
    21  *  Also, the settings of L1, L2, and L3 caches is not necessary here.
    22  *  (C) by Brookhaven National Lab., S. Kate Feng <feng1@bnl.gov>, 2003, 2004, 2005
    23  * 
     20 *  Modified to support the mvme5500 BSP
     21 *  (C) S. Kate Feng,Brookhaven National Lab <feng1@bnl.gov>, 2003, 2004, 2005, 2008
     22 *
    2423 *  $Id$
    2524 */
     
    4342#include <bsp/vectors.h>
    4443#include <bsp/bspException.h>
     44#include <bsp/VPD.h>
    4545
    4646#include <rtems/bspIo.h>
     
    5151#endif
    5252
    53 /*
    54 #define SHOW_MORE_INIT_SETTINGS
     53/*efine SHOW_MORE_INIT_SETTINGS
    5554#define SHOW_LCR1_REGISTER
    5655#define SHOW_LCR2_REGISTER
     
    7574SPR_RW(SPRG0)
    7675SPR_RW(SPRG1)
     76extern uint32_t probeMemoryEnd();
    7777
    7878typedef struct CmdLineRec_ {
     
    9696#define MAX_LOADER_ADD_PARM 80
    9797char loaderParam[MAX_LOADER_ADD_PARM];
     98
     99BSP_BoardTypes BSP_boardType=0;
     100
     101DiscoveryChipVersion BSP_controller_version;
    98102
    99103/*
     
    223227}
    224228
     229BSP_BoardTypes BSP_getBoardType()
     230{
     231        return BSP_boardType;
     232}
     233
    225234/*
    226235 *  bsp_start
     
    234243  int i;
    235244#endif
     245  int x;
    236246  unsigned char *stack;
    237247  unsigned long  *r1sp;
     
    251261  ppc_cpu_revision_t myCpuRevision;
    252262  Triv121PgTbl  pt=0;
     263  ConfVpdRec_t *pVPD = (ConfVpdRec_t *) &ConfVPD_buff[0];
     264
    253265
    254266  /* Till Straumann: 4/2005
     
    261273  setdbat(2, PCI0_MEM_BASE, PCI0_MEM_BASE, 0x10000000, IO_PAGE);
    262274
    263   /* Till Straumann: 2004
    264    * map the PCI 0, 1 Domain I/O space, GT64260B registers
    265    * and the reserved area so that the size is the power of 2.
     275  /* map the PCI 0, 1 Domain I/O space, GT64260B registers,
     276   * Flash Bank 0 and Flash Bank 2.
    266277   *
    267278   */
    268   setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x2000000, IO_PAGE);
     279  setdbat(3,PCI0_IO_BASE, PCI0_IO_BASE, 0x10000000, IO_PAGE);
    269280
    270281
     
    323334  Cpu_table.exceptions_in_RAM = TRUE;
    324335  initialize_exceptions();
     336
     337  /* <SKF> pci_initialize() before BSP_rtems_irq_mng_init to identify the version of the
     338   * Discovery chip.
     339   */
     340#ifdef SHOW_MORE_INIT_SETTINGS
     341  printk("Going to start PCI buses scanning and initialization\n");
     342#endif 
     343  pci_initialize();
     344#ifdef SHOW_MORE_INIT_SETTINGS
     345  printk("Number of PCI buses found is : %d\n", pci_bus_count());
     346#endif
     347
     348  /*
     349   * Initalize RTEMS IRQ system
     350   */
     351  BSP_rtems_irq_mng_init(0);
     352
    325353  /*
    326354   * Init MMU block address translation to enable hardware
     
    329357   */
    330358  printk("-----------------------------------------\n");
    331   printk("Welcome to %s on MVME5500-0163\n", _RTEMS_version );
     359  printk("Welcome to %s on MVME5500\n", _RTEMS_version );
    332360  printk("-----------------------------------------\n");
    333361
    334 #ifdef TEST_RETURN_TO_PPCBUG 
    335   printk("Hit <Enter> to return to PPCBUG monitor\n");
    336   printk("When Finished hit GO. It should print <Back from monitor>\n");
    337   debug_getc();
    338   _return_to_ppcbug();
    339   printk("Back from monitor\n");
    340   _return_to_ppcbug();
    341 #endif /* TEST_RETURN_TO_PPCBUG  */
    342 
    343 #ifdef TEST_RAW_EXCEPTION_CODE 
    344   printk("Testing exception handling Part 1\n");
    345   /*
    346    * Cause a software exception
    347    */
    348   __asm__ __volatile ("sc");
    349   /*
    350    * Check we can still catch exceptions and returned coorectly.
    351    */
    352   printk("Testing exception handling Part 2\n");
    353   __asm__ __volatile ("sc");
    354 #endif 
    355 
    356   BSP_mem_size                          =  _512M;
    357   /* TODO: calculate the BSP_bus_frequency using the REF_CLK bit of System Status  register */
     362  BSP_mem_size                          =  probeMemoryEnd();
    358363  /* rtems_bsp_delay_in_bus_cycles are defined in registers.h */
    359364  BSP_bus_frequency                     = 133333333;
     
    402407  BSP_Configuration.work_space_start = work_space_start;
    403408
    404   /*
    405    * Initalize RTEMS IRQ system
    406    */
    407    BSP_rtems_irq_mng_init(0);
    408 
    409409#ifdef SHOW_LCR2_REGISTER
    410410  l2cr = get_L2CR();
     
    430430  }
    431431
    432   /*
    433    * PCI 1 domain memory space
    434    */
    435   setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE);
    436  
    437 
    438 #ifdef SHOW_MORE_INIT_SETTINGS
    439   printk("Going to start PCI buses scanning and initialization\n");
    440 #endif 
    441   pci_initialize();
    442 #ifdef SHOW_MORE_INIT_SETTINGS
    443   printk("Number of PCI buses found is : %d\n", pci_bus_count());
    444 #endif
    445 
    446   /* Install our own exception handler (needs PCI) */
    447   globalExceptHdl = BSP_exceptionHandler;
    448 
    449   /* clear hostbridge errors. MCP signal is not used on the MVME5500
    450    * PCI config space scanning code will trip otherwise :-(
    451    */
    452   _BSP_clear_hostbridge_errors(0, 1 /*quiet*/);
    453 
    454   /* Read Configuration Vital Product Data (VPD) */
    455   if ( I2Cread_eeprom(0xa8, 4,2, &ConfVPD_buff[0], 150))
     432  if ( I2Cread_eeprom(0xa8, 0,2, (void *) pVPD, sizeof(ConfVpdRec_t)))
    456433     printk("I2Cread_eeprom() error \n");
    457434  else {
     
    462439      if ((i % 20)==0 ) printk("\n");
    463440    }
    464     printk("\n");
    465441#endif
    466442  }
     443
     444  /*
     445   * PCI 1 domain memory space
     446   */
     447  setdbat(1, PCI1_MEM_BASE, PCI1_MEM_BASE, 0x10000000, IO_PAGE);
     448 
     449  /* Install our own exception handler (needs PCI) */
     450  globalExceptHdl = BSP_exceptionHandler;
     451
     452
     453#if 1
     454  /* clear hostbridge errors. MCP signal is not used on the MVME5500
     455   * PCI config space scanning code will trip otherwise :-(
     456   */
     457  _BSP_clear_hostbridge_errors(0, 1 /*quiet*/);
     458#endif
    467459
    468460#ifdef SHOW_MORE_INIT_SETTINGS
     
    470462  printk("Exit from bspstart\n");
    471463#endif
    472 
    473 }
     464}
  • c/src/lib/libbsp/powerpc/mvme5500/startup/pgtbl_activate.c

    re1be2b3 rd7196bf  
    1212/* Author: Till Straumann, <strauman@slac.stanford.edu>, 4/2002
    1313 * Kate Feng <feng1@bnl.gov> ported it to MVME5500, 4/2004
     14 *
    1415 */
    1516
  • c/src/lib/libbsp/powerpc/mvme5500/startup/reboot.c

    re1be2b3 rd7196bf  
     1/* Copyright 2003, Shuchen Kate Feng <feng1@bnl.gov>,
     2 *                    NSLS,Brookhaven National Laboratory
     3 *
     4 * Ported it from powerpc/shared/console/reboot.c for mvme5500
     5 *
     6 */
    17#include <rtems.h>
    28#include <bsp.h>
     
    1319  printk("RTEMS terminated; Rebooting ...\n");
    1420  /* Mvme5500 board reset : 2004 S. Kate Feng <feng1@bnl.gov>  */
    15   out_8((volatile unsigned char*) (GT64260_DEV1_BASE +2), 0x80);
     21  out_8((volatile unsigned char*) (GT64x60_DEV1_BASE +2), 0x80);
    1622}
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