Timestamp:
05/26/14 13:22:12 (10 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
4.11, 5, master
Children:
5f0ab5cf
Parents:
70eff78
git-author:
Daniel Hellstrom <daniel@…> (05/26/14 13:22:12)
git-committer:
Daniel Hellstrom <daniel@…> (05/28/14 15:33:22)
Message:

SPARC: syscall optimizations and PSR-write fix

The last optimization missed was incorrect in regards to
PSR write instruction delay must be 3 instructions.

New optimizations:

  • align to 32-byte cache line.
  • rearrange code into three "blocks" of 4 instructions that is executed by syscall 2 and 3. This is to optimize for 16/32 byte cache lines.
  • use delay-slot instruction in trap table to reduce by one instruction.
  • use the fact that "wr %PSR" implements XOR to reduce by one instruction.
(No files)

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