Changeset d6f1ec91 in rtems


Ignore:
Timestamp:
May 26, 2014, 1:22:12 PM (5 years ago)
Author:
Daniel Hellstrom <daniel@…>
Branches:
4.11, master
Children:
5f0ab5cf
Parents:
70eff78
git-author:
Daniel Hellstrom <daniel@…> (05/26/14 13:22:12)
git-committer:
Daniel Hellstrom <daniel@…> (05/28/14 15:33:22)
Message:

SPARC: syscall optimizations and PSR-write fix

The last optimization missed was incorrect in regards to
PSR write instruction delay must be 3 instructions.

New optimizations:

  • align to 32-byte cache line.
  • rearrange code into three "blocks" of 4 instructions that is executed by syscall 2 and 3. This is to optimize for 16/32 byte cache lines.
  • use delay-slot instruction in trap table to reduce by one instruction.
  • use the fact that "wr %PSR" implements XOR to reduce by one instruction.
Location:
c/src/lib
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/start/start.S

    r70eff78 rd6f1ec91  
    3232  nop; \
    3333  nop;
     34
     35/*
     36 * System call optimized trap table entry
     37 */
     38#define SYSCALL_TRAP(_vector, _handler)  \
     39  mov   %psr, %l0 ; \
     40  sethi %hi(_handler), %l4 ; \
     41  jmp   %l4+%lo(_handler); \
     42   subcc %g1, 3, %g0; ! prepare for syscall 3 check
    3443
    3544/*
     
    157166   */
    158167
    159   TRAP( 0x80, SYM(syscall) );                   ! 80 syscall SW trap
     168  SYSCALL_TRAP( 0x80, SYM(syscall) );           ! 80 syscall SW trap
    160169  SOFT_TRAP; SOFT_TRAP;                         ! 81 - 82
    161170  TRAP( 0x83, SYM(window_flush_trap_handler) ); ! 83 flush windows SW trap
  • c/src/lib/libcpu/sparc/syscall/syscall.S

    r70eff78 rd6f1ec91  
    3636         */
    3737
     38.align 32                               ! Align to 32-byte cache-line
    3839        PUBLIC(syscall)
    3940
    4041SYM(syscall):
    4142
    42         subcc   %g1, 2, %g0             ! syscall 2, disable interrupts
    43         bne     3f
    44          subcc   %g1, 3, %g0            ! syscall 3, enable interrupts
    45         or      %l0, 0x0f00, %l4        ! set PIL=15
    46         ba      9f
    47          or     %l0, SPARC_PSR_ET_MASK, %i0     ! return old psr with ET=1
    48 3:
    49         bne     1f
     43        ! "subcc, %g1, 3, %g0" done in trap table
     44        bne     2f                      ! syscall 3? enable interrupt
    5045         and    %i0, SPARC_PSR_PIL_MASK, %l4
    5146        andn    %l0, SPARC_PSR_PIL_MASK, %l5
    52         or      %l5, %l4, %l4
    53 9:                                      ! leave
    54         mov     %l4, %psr               ! Update PSR according to Syscall 2 or 3
     47        wr      %l4, %l5, %psr          ! Update PSR according to syscall 3
     481:                                      ! leave, with 3 inst PSR-write delay
    5549        mov     0, %g1                  ! clear %g1
    56         jmpl    %l2, %g0
    57          rett    %l2 + 4
    58 1:
     50        or      %l0, SPARC_PSR_ET_MASK, %i0     ! return old psr with ET=1. No
     51                                                ! effect on syscall 3
     52        jmpl    %l2, %g0
     53         rett   %l2 + 4
     54
     552:      or      %l0, 0x0f00, %l4        ! set PIL=15
     56        subcc   %g1, 2, %g0             ! syscall 2? disable interrupts
     57        beq,a   1b                      ! Annul delay-slot for syscall 1
     58         mov    %l4, %psr               ! Update PSR according to Syscall 2
    5959        ta      0                       ! syscall 1 (not 2 or 3), halt
    6060
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